WO2023195132A1 - Electronic device, electronic system and method for producing electronic device - Google Patents

Electronic device, electronic system and method for producing electronic device Download PDF

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Publication number
WO2023195132A1
WO2023195132A1 PCT/JP2022/017281 JP2022017281W WO2023195132A1 WO 2023195132 A1 WO2023195132 A1 WO 2023195132A1 JP 2022017281 W JP2022017281 W JP 2022017281W WO 2023195132 A1 WO2023195132 A1 WO 2023195132A1
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WIPO (PCT)
Prior art keywords
substrate
electronic device
insulator
forming
groove
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PCT/JP2022/017281
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French (fr)
Japanese (ja)
Inventor
誠 中村
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富士通株式会社
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Priority to PCT/JP2022/017281 priority Critical patent/WO2023195132A1/en
Publication of WO2023195132A1 publication Critical patent/WO2023195132A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

Definitions

  • the disclosed technology relates to an electronic device and a method for manufacturing the electronic device.
  • the following technology is known as a technology related to a device having a via that penetrates a substrate.
  • a method of manufacturing a superconducting device includes the steps of forming a recess in a substrate and depositing a superconducting layer in the recess to form a superconducting path.
  • a method for manufacturing a device having a via penetrating a substrate includes: forming a through hole in a silicon substrate; forming a seed layer containing Cu on one surface of the silicon substrate to close an open end of the through hole;
  • a manufacturing method is known that includes a step of embedding Sn into a through hole by a plating method using a seed layer, and a step of removing the seed layer. According to the above manufacturing method, there is a possibility that Cu forming the seed layer diffuses into Sn forming the via. Since Cu is a material that does not exhibit superconductivity, if Cu diffuses into the Sn via, there is a possibility that the Sn via will not be able to exhibit superconductivity.
  • the disclosed technology aims to enable application to superconducting devices in electronic devices having vias that penetrate through a substrate.
  • An electronic device includes a substrate and at least one via containing a silicon single crystal that penetrates the substrate.
  • the electronic device it is possible to apply the electronic device to a superconducting device in an electronic device having a via penetrating a substrate.
  • FIG. 1 is a cross-sectional view showing an example of the configuration of an electronic device according to an embodiment of the disclosed technology.
  • FIG. 1 is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to an embodiment of the disclosed technology.
  • FIG. 1 is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to an embodiment of the disclosed technology.
  • FIG. 1 is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to an embodiment of the disclosed technology.
  • FIG. 1 is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to an embodiment of the disclosed technology.
  • FIG. 1 is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to an embodiment of the disclosed technology.
  • FIG. 1 is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to an embodiment of the disclosed technology.
  • FIG. 1 is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to an embodiment of the disclosed technology.
  • FIG. 1 is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to an embodiment of the disclosed technology.
  • 1 is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to an embodiment of the disclosed technology.
  • FIG. 1 is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to an embodiment of the disclosed technology.
  • FIG. 1 is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to an embodiment of the disclosed technology.
  • FIG. 1 is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to an embodiment of the disclosed technology.
  • FIG. 2 is a plan view showing an example of the configuration of a substrate according to an embodiment of the disclosed technology.
  • FIG. 3 is a cross-sectional view showing an example of the configuration of an electronic device according to another embodiment of the disclosed technology.
  • FIG. 7 is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to another embodiment of the disclosed technology.
  • FIG. 1 is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to an embodiment of the disclosed technology.
  • FIG. 3 is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to another embodiment of the disclosed technology.
  • FIG. 3 is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to another embodiment of the disclosed technology.
  • FIG. 7 is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to another embodiment of the disclosed technology.
  • FIG. 7 is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to another embodiment of the disclosed technology.
  • FIG. 7 is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to another embodiment of the disclosed technology.
  • FIG. 7 is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to another embodiment of the disclosed technology.
  • 1 is a cross-sectional view showing an example of the configuration of an electronic system according to an embodiment of the disclosed technology.
  • 1 is a cross-sectional view showing an example of the configuration of an electronic system according to an embodiment of the disclosed technology.
  • 1 is a cross-sectional view showing an example of the configuration of an electronic system according to an embodiment of the disclosed technology.
  • FIG. 1 is a cross-sectional view showing an example of the configuration of an electronic device 10 according to a first embodiment of the disclosed technology.
  • the electronic device 10 includes a substrate 11, a via 12 penetrating the substrate 11, a quantum bit element 13 electrically connected to the via 12, and an electrode electrically connected to the quantum bit element 13 via the via 12. 14.
  • the electronic device 10 constitutes a quantum bit device.
  • the substrate 11 is a silicon single crystal substrate with a thickness of about 400 ⁇ m.
  • the via 12 is a through-silicon via (TSV) that reaches from the first surface S1 to the second surface S2 of the substrate 11.
  • the via 12 is made of silicon single crystal, which is the material of the substrate 11 . That is, the silicon single crystal forming the via 12 originates from the substrate 11, and the silicon single crystal forming the via 12 has the same crystal orientation as the silicon single crystal forming the substrate 11. Since silicon exhibits superconductivity at a temperature of 6.7 K or lower, the via 12 made of silicon single crystal can be used as a conductive path in a superconducting device that utilizes the superconducting phenomenon.
  • electronic device 10 may include multiple vias.
  • the crystal orientations of the silicon single crystals forming the plurality of vias 12 are the same.
  • the shape of the via 12 is not particularly limited, but may be, for example, a cylindrical shape or a prismatic shape.
  • the width (diameter) of the via 12 is, for example, about 40 ⁇ m.
  • Electronic device 10 includes an insulator 15 that surrounds via 12 and separates via 12 from substrate 11 .
  • the insulator 15 extends from the first surface S1 to the second surface S2 of the substrate 11, and covers the entire side surface of the via 12.
  • the shape of the insulator 15 in a plan view is annular, and depending on the shape of the via 12, it may be annular, rectangular, or polygonal.
  • SiO 2 can be used as the insulator 15.
  • the quantum bit element 13 is provided on the first surface S1 side of the substrate 11.
  • the quantum bit element 13 is an element that forms a coherent two-level system using superconductivity, and may include, for example, a superconducting Josephson element (not shown).
  • a superconducting Josephson device consists of a pair of superconductors that exhibit superconductivity at a temperature below a predetermined critical temperature, and an extremely thin insulator with a thickness of several nanometers sandwiched between the pair of superconductors. It is composed of:
  • the superconductor may be, for example , Al
  • the insulator may be, for example, Al2O3 . It is also possible to use Nb instead of Al.
  • electronic device 10 may include multiple qubit devices. Each of the plurality of qubit devices creates a quantum entangled state with other adjacent qubit devices to perform quantum operations.
  • the quantum bit element 13 is electrically connected to the via 12 via a wiring 16.
  • the wiring 16 is made of a metal that exhibits superconductivity at a temperature below a predetermined critical temperature.
  • a material for the wiring 16 for example, Al or TiN can be used. Note that although FIG. 1 illustrates a configuration in which the quantum bit element 13 is provided in a position that does not overlap with the via 12, the quantum bit element 13 may be provided in a position that overlaps with the via 12. This makes it possible to shorten the length of the wiring 16.
  • the quantum bit element 13 and the wiring 16 are covered with an insulating film 17.
  • the electrode 14 is provided on the second surface S2 of the substrate 11, which is opposite to the first surface S1.
  • the electrode 14 is electrically connected to the via 12 via a wiring 18.
  • the electrode 14 is electrically connected to the quantum bit element 13 via the via 12.
  • the electrode 14 has a so-called bump shape and has a portion protruding from the insulating film 19 covering the second surface S2 of the substrate 11.
  • Electrode 14 functions as an electrical and mechanical connection when laminating electronic device 10 to a wiring board or other device.
  • the wiring 18 and the electrode 14 are made of a metal that exhibits superconductivity at a temperature below a predetermined critical temperature. As the material of the wiring 18, for example, Al or TiN can be used.
  • the material of the electrode 14 for example, Sn, In, or Ga can be used.
  • a UBM Under Bump Metal
  • the UBM is composed of a metal that exhibits superconductivity at a temperature below a predetermined critical point.
  • TiN can be used as the material of the UBM.
  • 2A to 2G are cross-sectional views showing an example of a method for manufacturing the electronic device 10.
  • Substrate 11 is a silicon single crystal substrate.
  • a SiO 2 film 21 with a thickness of about 100 nm is formed on the first surface S1 of the substrate 11 by CVD (chemical vapor deposition).
  • a metal film 22 with a thickness of about 1 ⁇ m is formed by sputtering.
  • Al can be used as the material of the metal film 22 (FIG. 2A). Note that it is also possible to use a resist instead of the metal film 22.
  • the laminated film including the SiO 2 film 21 and the metal film 22 is patterned by reactive ion etching. Specifically, an annular opening 23 is formed in a region of the laminated film including the SiO 2 film 21 and the metal film 22 surrounding the area where the via 12 is to be formed.
  • Chlorine-based gas can be used for etching the metal film 22.
  • Fluorocarbon gas can be used for etching the SiO 2 film 21.
  • the substrate 11 is etched through the hard mask 20. That is, a region of the substrate 11 surrounding the portion where the via 12 is to be formed is etched from the first surface S1 side of the substrate 11. This forms an annular groove 30 that defines the via 12.
  • the groove 30 is formed to a depth that does not reach the second surface S2. That is, etching is stopped before the groove 30 penetrates the substrate 11.
  • the width of the groove 30 is, for example, about 5 ⁇ m, and the depth of the groove 30 is, for example, about 450 ⁇ m (FIG. 2C).
  • a method may be used in which the step of covering the side surfaces of the groove 30 that is being formed with a protective film and the step of further etching the bottom surface of the groove 30 that is being formed are performed alternately.
  • etching of the side surface of the groove 30 is suppressed during etching of the bottom surface of the groove 30.
  • CF gas is used in the step of covering the side surfaces of the trench 30 with a protective film
  • SF6 gas is used in the step of etching the bottom surface of the trench 30.
  • This etching process is called the Bosch Process and is applied to deep trenches in silicon substrates.
  • the groove 30 is filled with an insulator 15 such as SiO 2 by CVD (FIG. 2D).
  • the second surface S2 of the substrate 11 is ground to expose the insulator 15 on the second surface S2 (FIG. 2E).
  • a via 12 made of silicon single crystal that penetrates the substrate 11 and has the same crystal orientation as the substrate 11 is formed.
  • Via 12 is insulated from substrate 11 by an insulator 15 covering all of its sides. Further, by grinding the substrate 11, the substrate 11 is thinned to a thickness of about 400 ⁇ m.
  • the superconducting Josephson element constituting the quantum bit element 13 is manufactured by forming a first electrode (not shown) containing Al by vapor deposition, for example, or by forming a thickness on the surface of the first electrode by ALD (Atomic Layer Deposition).
  • Patterning of the first electrode and the second electrode may be performed, for example, by a lift-off method using a patterned resist (not shown).
  • the opening pattern of the resist is a cross shape including a first straight line section along the first direction and a second straight line section along the second direction perpendicular to the first direction
  • the first electrode may be formed in a portion corresponding to the first linear portion by performing vapor deposition with the first direction as the rotation axis.
  • the second electrode may be formed in a portion corresponding to the second linear portion by performing vapor deposition with the second direction as the rotation axis.
  • a wiring 16 connecting the quantum bit element 13 and the via 12 is formed using a sputtering method and an etching method (FIG. 2F).
  • a material for the wiring 16 for example, Al or TiN can be used.
  • an insulating film 17 made of an insulator such as SiO 2 that covers the quantum bit element 13 and the wiring 16 is formed on the first surface S1 of the substrate 11 by CVD (FIG. 2F).
  • the wiring 18 connected to the via 12 is formed on the second surface S2 side of the substrate 11 using a sputtering method and an etching method (FIG. 2G).
  • a material for the wiring 18 for example, Al or TiN can be used.
  • an insulating film 19 made of an insulator such as SiO 2 that covers the wiring 18 is formed on the second surface S2 of the substrate 11 by CVD (FIG. 2G).
  • an opening that partially exposes the wiring 18 is formed in the insulating film 19 by an etching method.
  • the electrode 14 is formed on the exposed portion of the wiring 18 using a plating method (FIG. 2G).
  • 3A to 3E are cross-sectional views showing an example of a method for manufacturing the electronic device 10 including a step of forming the via 12, which is applicable even when the length of the via 12 becomes long.
  • first groove 30A that defines a first portion 12A of the via.
  • the first groove 30A is formed to a depth that does not reach the second surface S2 (FIG. 3A).
  • the first trench 30A is filled with an insulator 15 such as SiO 2 by CVD (FIG. 3B).
  • an insulator 15 such as SiO 2 by CVD
  • a hard mask 20B similar to the hard mask 20A formed on the first surface S1 is formed on the second surface S2 of the substrate 11, and vias 12 are formed on the substrate 11 using the hard mask 20B.
  • a region surrounding the planned site is etched from the second surface S2 side of the substrate 11. This forms a second annular groove 30B that defines the second portion 12B of the via.
  • the second groove 30 has a depth that reaches the insulator 15 embedded in the first groove 30.
  • the second groove 30B is filled with an insulator 15 such as SiO 2 by CVD (FIG. 3D).
  • a quantum bit element 13 is formed on the first surface S1 of the substrate 11, a wiring 16 connecting the quantum bit element 13 and the via 12 is formed, and SiO 2 or the like is formed to cover the quantum bit element 13 and the wiring 16.
  • An insulating film 17 made of an insulator is formed on the first surface S1 of the substrate 11.
  • wiring 18 connected to the via 12 is formed on the second surface S2 of the substrate 11, and an insulating film 19 made of an insulator such as SiO 2 covering the wiring 18 is formed on the second surface S2 of the substrate 11.
  • the electrode 14 is formed on the exposed portion of the wiring 18 (FIG. 3E).
  • the electronic device 10 has at least one via 12 containing silicon single crystal that penetrates the substrate 11. Since silicon exhibits superconductivity at a temperature of 6.7 K or lower, the via 12 made of silicon single crystal can be used as a conductive path in a superconducting device that utilizes the superconducting phenomenon. By forming the via 12 with silicon single crystal, a substance that does not exhibit superconductivity, such as Cu, will not diffuse into the via 12. Therefore, the electronic device 10 according to this embodiment can be applied to superconducting devices.
  • the substrate 11 is made of the same silicon single crystal as the vias 12. If the substrate 11 and the vias 12 are made of different materials, there is a risk that the substrate 11 will warp due to temperature changes due to the difference in thermal expansion coefficients between the substrate 11 and the vias 12. Since superconducting devices are assumed to be used in extremely low temperature environments and the temperature changes are very large, it is preferable that the difference in thermal expansion coefficients between the substrate 11 and the vias 12 be small. According to the electronic device 10 according to the present embodiment, since the vias 12 are made of the same silicon single crystal as the substrate 11, the thermal expansion coefficients of the substrate 11 and the vias 12 can be made equal, and the substrate It becomes possible to suppress the occurrence of warpage.
  • the via 12 is formed by forming the groove 30 that defines the via 12 in the substrate 11, so that the problem of voids occurring in the via 12 can be avoided.
  • the disclosed technology is not limited to this aspect.
  • the disclosed technology can also be applied to an interposer that relays input/output signals of a quantum bit device.
  • the quantum bit device is a superconducting quantum bit device such as a Josephson device, but the quantum bit device may be a silicon quantum bit device.
  • FIG. 4 is a plan view showing an example of the configuration of the substrate 11.
  • a plurality of vias 12 may be provided in the substrate 11 in a dense manner.
  • Each of the plurality of vias 12 is made of a silicon single crystal having the same crystal orientation as the silicon single crystal forming the substrate 11 .
  • Each of the vias 12 is surrounded by an insulator 15 and is insulated from other vias 12 and the substrate 11 . All or some of the plurality of vias 12 may be used as a conductive path between the first surface S1 and the second surface S2 of the substrate 11. good.
  • FIG. 4 shows an example of a via 12 having a circular shape in a plan view, the shape of the via 12 in a plan view may be a quadrilateral, a hexagon, or another polygon.
  • FIG. 5 is a diagram illustrating an example of the configuration of an electronic device 10A according to the second embodiment of the disclosed technology.
  • the electronic device 10A differs from the electronic device 10 according to the first embodiment described above in that the substrate 11 is made of an insulator 40.
  • the via 12 is made of silicon single crystal similarly to the electronic device 10 according to the first embodiment.
  • SiO 2 can be used as the insulator 40 that constitutes the substrate 11.
  • a molded resin may be used as the insulator 40 constituting the substrate 11.
  • an epoxy resin containing silica filler can be used.
  • 6A to 6G are cross-sectional views showing an example of a method for manufacturing the electronic device 10.
  • Substrate 11 is a silicon single crystal substrate.
  • a SiO 2 film 21 with a thickness of about 100 nm is formed on the first surface S1 of the substrate 11 by CVD.
  • a metal film 22 with a thickness of about 1 ⁇ m is formed by sputtering.
  • Al can be used as the material of the metal film 22 (FIG. 6A). Note that it is also possible to use a resist instead of the metal film 22.
  • the laminated film including the SiO 2 film 21 and the metal film 22 is patterned by reactive ion etching. Specifically, an opening 23 is formed in a region of the laminated film including the SiO 2 film 21 and the metal film 22 surrounding the area where the via 12 is to be formed. As a result, a hard mask 20 including the SiO 2 film 21 and the metal film 22 is formed. In this embodiment, only the portion where the via 12 is to be formed is covered with the hard mask 20 (FIG. 6B).
  • the substrate 11 is etched through the hard mask 20. That is, a region of the substrate 11 surrounding the portion where the via 12 is to be formed is etched from the first surface S1 side of the substrate 11. In this embodiment, a portion of the substrate 11 other than the portion where the via 12 is planned to be formed is etched so as to cut out the via 12 . As a result, grooves 30 defining vias 12 are formed. The groove 30 is formed to a depth that does not reach the second surface S2. That is, etching is stopped before the groove 30 penetrates the substrate 11 (FIG. 6C).
  • the groove 30 is filled with an insulator 40 such as SiO 2 by CVD. It is also possible to use molded resin as the insulator 40.
  • the members of the substrate 11, except for the portions forming the vias 12, are replaced by the insulator 40 from silicon single crystal. A portion of the silicon single crystal substrate constituting the via 12 is buried inside the insulator 40 (FIG. 6D).
  • the first surface S1 of the substrate 11 (the upper surface of the insulator 40) is ground to expose the upper end of the via 12.
  • the second surface S2 of the substrate 11 (the lower surface of the silicon single crystal substrate) is ground to expose the lower ends of the vias 12.
  • a via 12 made of silicon single crystal and penetrating the substrate 11 (insulator 40) is formed (FIG. 6E).
  • the quantum bit element 13 is formed on the first surface S1 of the substrate 11 (FIG. 6F).
  • a wiring 16 connecting the quantum bit element 13 and the via 12 is formed using a sputtering method and an etching method (FIG. 6F).
  • Al can be used as a material for the wiring 16.
  • an insulating film 17 made of an insulator such as SiO 2 that covers the quantum bit element 13 and the wiring 16 is formed on the first surface S1 of the substrate 11 by CVD (FIG. 6F).
  • the wiring 18 connected to the via 12 is formed on the second surface S2 side of the substrate 11 using a sputtering method and an etching method (FIG. 6G).
  • a sputtering method and an etching method For example, Al can be used as the material for the wiring 18.
  • an insulating film 19 made of an insulator such as SiO 2 that covers the wiring 18 is formed on the second surface S2 of the substrate 11 by CVD (FIG. 6G).
  • an opening that partially exposes the wiring 18 is formed in the insulating film 19 by an etching method.
  • the electrode 14 is formed on the exposed portion of the wiring 18 using a plating method (FIG. 6G).
  • the electronic device 10A according to the second embodiment of the disclosed technology has at least one via 12 containing silicon single crystal that penetrates the substrate 11, and the substrate 11 is made of the insulator 40. There is.
  • the electronic device 10A according to this embodiment can be applied to a superconducting device like the electronic device 10 according to the first embodiment.
  • FIG. 7 is a cross-sectional view showing an example of the configuration of an electronic system 100 according to a third embodiment of the disclosed technology.
  • the electronic system 100 includes an electronic device 10B that constitutes a quantum bit device, and an electronic device 10C that constitutes a control device for controlling the electronic device 10B.
  • the electronic device 10B is mounted on the wiring board 50, and the electronic device 10C is stacked on the electronic device 10B.
  • the electronic device 10B constituting the quantum bit device includes a plurality of quantum bit elements 13 provided on the first surface S1 side of the substrate 11, and a plurality of vias 12 electrically connected to the plurality of quantum bit elements 13. has.
  • the substrate 11 is a silicon single crystal substrate, and each of the plurality of vias 12 is made of a silicon single crystal having the same crystal orientation as the silicon single crystal forming the substrate 11.
  • Insulator 15 surrounds the via and separates via 12 from substrate 11 .
  • a plurality of electrodes 14 are provided on the second surface S2 of the substrate 11. At least some of the plurality of electrodes 14 are electrically connected to the quantum bit element 13 via the via 12.
  • the plurality of electrodes 14 function as electrical and mechanical connections when mounting the electronic device 10B on the wiring board 50.
  • the electronic device 10C constituting the control device includes a circuit element 61 such as a transistor formed on the surface of a substrate 60 made of a semiconductor such as silicon single crystal, and a plurality of electrodes 62 electrically connected to the circuit element 61. has.
  • the electrode 62 has a so-called bump shape and has a portion protruding from the insulating film 63 covering the surface of the substrate 60.
  • Each of the plurality of electrodes 62 is connected to an electrode pad 70 provided on the surface of the electronic device 10B. At least a portion of electrode pad 70 is electrically connected to quantum bit element 13 .
  • the electronic device 10C is stacked face down on the electronic device 10B.
  • the electronic device 10C controls, for example, reading out the signal output from the quantum bit element 13.
  • the electronic device 10C constituting the control device may be stacked face-up on the electronic device 10B. In this case, the electronic device 10C is provided with a via that penetrates the substrate 60.
  • FIG. 8 is a cross-sectional view showing another example of the configuration of an electronic system 100A according to a modification.
  • the electronic system 100A includes an electronic device 10B that constitutes a quantum bit device, and an electronic device 10C that constitutes a control device that controls the electronic device 10B.
  • the electronic device 10C is mounted on the wiring board 50, and the electronic device 10B is stacked on the electronic device 10C.
  • the electronic device 10C constituting the control device has a plurality of circuit elements 61 such as transistors provided on the upper surface side of the substrate 60, and a plurality of vias 64 electrically connected to the plurality of circuit elements 61.
  • the substrate 60 is a silicon single crystal substrate, and each of the plurality of vias 64 is made of a silicon single crystal having the same crystal orientation as the silicon single crystal forming the substrate 60.
  • An insulator 65 surrounds the via and separates the via 64 from the substrate 60.
  • a plurality of electrodes 62 are provided on the lower surface side of the substrate 60. At least some of the plurality of electrodes 62 are electrically connected to the circuit element 61 via vias 64.
  • the plurality of electrodes 62 function as electrical and mechanical connections when the electronic device 10C is mounted on the wiring board 50.
  • the electronic device 10B constituting the quantum bit device has a quantum bit element 13 formed on the surface of the substrate 11 and a plurality of electrodes 14 electrically connected to the quantum bit element 13. Each of the plurality of electrodes 14 is connected to an electrode pad 66 provided on the surface of the electronic device 10C. At least some of the plurality of electrode pads 66 are electrically connected to the circuit element 61.
  • the electronic device 10B is stacked face down on the electronic device 10C.
  • the electronic device 10C controls, for example, reading out the signal output from the quantum bit element 13.
  • the electronic device 10B constituting the quantum bit device may be stacked face-up on the electronic device 10C. In this case, the electronic device 10B is provided with a via penetrating the substrate 11.
  • FIG. 9 is a sectional view showing another example of the configuration of an electronic system 100B according to a modification.
  • the electronic system 100B relays signals transmitted and received between the electronic device 10B that constitutes a quantum bit device, the electronic device 10C that constitutes a control device that controls the electronic device 10B, and the electronic device 10B and the electronic device 10C. and an electronic device 10D that constitutes an interposer.
  • An electronic device 10C that constitutes a control device is mounted on the wiring board 50, an electronic device 10D that constitutes an interposer is stacked on the electronic device 10C, and an electronic device 10B that constitutes a quantum bit device. It is stacked on the electronic device 10D. That is, the electronic device 10D forming the interposer is provided between the electronic device 10B forming the quantum bit device and the electronic device 10C forming the control device.
  • the configurations of the electronic device 10B and the electronic device 10C are the same as those shown in FIG.
  • the electronic device 10D that constitutes the interposer has a plurality of vias 81 that penetrate the substrate 80.
  • the substrate 80 is a silicon single crystal substrate, and each of the plurality of vias 81 is made of a silicon single crystal having the same crystal orientation as the silicon single crystal forming the substrate 80.
  • Insulator 82 surrounds via 81 and separates via 81 from substrate 80 .
  • a plurality of electrodes 83 are provided on the lower surface of the substrate 80. Each of the plurality of electrodes 83 is connected to an electrode pad 66 provided on the surface of the electronic device 10C that constitutes the control device. At least a portion of the electrode pad 66 is electrically connected to the circuit element 61.
  • Each of the plurality of electrodes 14 included in the electronic device 10B that constitutes the quantum bit device is connected to an electrode pad 84 provided on the surface of the electronic device 10D that constitutes the interposer.
  • the electronic device 10B is stacked face down on the electronic device 10D.
  • the electronic device 10C controls, for example, reading out the signal output from the quantum bit element 13.
  • the signal output from the quantum bit element 13 is transmitted to the electronic device 10C forming a control device via the via 81 included in the electronic device 10D.
  • the electronic device 10B constituting the quantum bit device may be stacked on the electronic device 10D in a face-up manner. In this case, the electronic device 10B is provided with a via penetrating the substrate 11.

Abstract

An electronic device 10 comprises a substrate 11 and at least one via that passes through the substrate 11 and contains single crystal silicon.

Description

電子装置、電子システム及び電子装置の製造方法Electronic devices, electronic systems, and methods for manufacturing electronic devices
　開示の技術は、電子装置及び電子装置の製造方法に関する。 The disclosed technology relates to an electronic device and a method for manufacturing the electronic device.
　基板を貫通するビアを有するデバイスに関する技術として、以下の技術が知られている。例えば、基板内に、凹部を形成する工程と、凹部内に超伝導層を堆積させ、超伝導経路を形成する工程と、を含む超伝導デバイスの製造方法が知られている。 The following technology is known as a technology related to a device having a via that penetrates a substrate. For example, a method of manufacturing a superconducting device is known that includes the steps of forming a recess in a substrate and depositing a superconducting layer in the recess to form a superconducting path.
米国特許出願公開第２０２０／０３４３４３４号明細書US Patent Application Publication No. 2020/0343434
　基板を貫通するビアを有するデバイスの製造方法として、シリコン基板に貫通孔を形成する工程と、シリコン基板の一方の面に、貫通孔の開口端を塞ぐＣｕを含むシード層を形成する工程と、シード層を用いためっき法によって貫通孔の内部にＳｎを埋め込む工程と、シード層を除去する工程とを含む製造方法が知られている。上記の製造方法によれば、ビアを構成するＳｎに、シード層を構成するＣｕが拡散する可能性がある。Ｃｕは、超伝導性を発現しない材料であることから、ＳｎビアにＣｕが拡散した場合には、当該Ｓｎビアについては超伝導特性を発現させることができない恐れがある。 A method for manufacturing a device having a via penetrating a substrate includes: forming a through hole in a silicon substrate; forming a seed layer containing Cu on one surface of the silicon substrate to close an open end of the through hole; A manufacturing method is known that includes a step of embedding Sn into a through hole by a plating method using a seed layer, and a step of removing the seed layer. According to the above manufacturing method, there is a possibility that Cu forming the seed layer diffuses into Sn forming the via. Since Cu is a material that does not exhibit superconductivity, if Cu diffuses into the Sn via, there is a possibility that the Sn via will not be able to exhibit superconductivity.
　開示の技術は、基板を貫通するビアを有する電子装置において、超伝導デバイスへの適用を可能とすることを目的とする。 The disclosed technology aims to enable application to superconducting devices in electronic devices having vias that penetrate through a substrate.
　開示の技術に係る電子装置は、基板と、前記基板を貫通する、シリコン単結晶を含む少なくとも１つのビアと、を有する。 An electronic device according to the disclosed technology includes a substrate and at least one via containing a silicon single crystal that penetrates the substrate.
　開示の技術によれば、基板を貫通するビアを有する電子装置において、超伝導デバイスへの適用を可能にすることができる。 According to the disclosed technology, it is possible to apply the electronic device to a superconducting device in an electronic device having a via penetrating a substrate.
開示の技術の実施形態に係る電子装置の構成の一例を示す断面図である。1 is a cross-sectional view showing an example of the configuration of an electronic device according to an embodiment of the disclosed technology. 開示の技術の実施形態に係る電子装置の製造方法の一例を示す断面図である。FIG. 1 is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to an embodiment of the disclosed technology. 開示の技術の実施形態に係る電子装置の製造方法の一例を示す断面図である。FIG. 1 is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to an embodiment of the disclosed technology. 開示の技術の実施形態に係る電子装置の製造方法の一例を示す断面図である。FIG. 1 is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to an embodiment of the disclosed technology. 開示の技術の実施形態に係る電子装置の製造方法の一例を示す断面図である。FIG. 1 is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to an embodiment of the disclosed technology. 開示の技術の実施形態に係る電子装置の製造方法の一例を示す断面図である。FIG. 1 is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to an embodiment of the disclosed technology. 開示の技術の実施形態に係る電子装置の製造方法の一例を示す断面図である。FIG. 1 is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to an embodiment of the disclosed technology. 開示の技術の実施形態に係る電子装置の製造方法の一例を示す断面図である。FIG. 1 is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to an embodiment of the disclosed technology. 開示の技術の実施形態に係る電子装置の製造方法の一例を示す断面図である。FIG. 1 is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to an embodiment of the disclosed technology. 開示の技術の実施形態に係る電子装置の製造方法の一例を示す断面図である。1 is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to an embodiment of the disclosed technology. 開示の技術の実施形態に係る電子装置の製造方法の一例を示す断面図である。FIG. 1 is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to an embodiment of the disclosed technology. 開示の技術の実施形態に係る電子装置の製造方法の一例を示す断面図である。FIG. 1 is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to an embodiment of the disclosed technology. 開示の技術の実施形態に係る電子装置の製造方法の一例を示す断面図である。FIG. 1 is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to an embodiment of the disclosed technology. 開示の技術の実施形態に係る基板の構成の一例を示す平面図である。FIG. 2 is a plan view showing an example of the configuration of a substrate according to an embodiment of the disclosed technology. 開示の技術の他の実施形態に係る電子装置の構成の一例を示す断面図である。FIG. 3 is a cross-sectional view showing an example of the configuration of an electronic device according to another embodiment of the disclosed technology. 開示の技術の他の実施形態に係る電子装置の製造方法の一例を示す断面図である。FIG. 7 is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to another embodiment of the disclosed technology. 開示の技術の他実施形態に係る電子装置の製造方法の一例を示す断面図である。FIG. 3 is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to another embodiment of the disclosed technology. 開示の技術の他実施形態に係る電子装置の製造方法の一例を示す断面図である。FIG. 3 is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to another embodiment of the disclosed technology. 開示の技術の他の実施形態に係る電子装置の製造方法の一例を示す断面図である。FIG. 7 is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to another embodiment of the disclosed technology. 開示の技術の他の実施形態に係る電子装置の製造方法の一例を示す断面図である。FIG. 7 is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to another embodiment of the disclosed technology. 開示の技術の他の実施形態に係る電子装置の製造方法の一例を示す断面図である。FIG. 7 is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to another embodiment of the disclosed technology. 開示の技術の他の実施形態に係る電子装置の製造方法の一例を示す断面図である。FIG. 7 is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to another embodiment of the disclosed technology. 開示の技術の実施形態に係る電子システムの構成の一例を示す断面図である。1 is a cross-sectional view showing an example of the configuration of an electronic system according to an embodiment of the disclosed technology. 開示の技術の実施形態に係る電子システムの構成の一例を示す断面図である。1 is a cross-sectional view showing an example of the configuration of an electronic system according to an embodiment of the disclosed technology. 開示の技術の実施形態に係る電子システムの構成の一例を示す断面図である。1 is a cross-sectional view showing an example of the configuration of an electronic system according to an embodiment of the disclosed technology.
　以下、開示の技術の実施形態の一例を、図面を参照しつつ説明する。なお、各図面において同一又は等価な構成要素及び部分には同一の参照符号を付与し、重複する説明は省略する。 Hereinafter, an example of an embodiment of the disclosed technology will be described with reference to the drawings. In addition, the same reference numerals are given to the same or equivalent components and parts in each drawing, and overlapping explanation will be omitted.
［第１の実施形態］
　図１は、開示の技術の第１の実施形態に係る電子装置１０の構成の一例を示す断面図である。電子装置１０は、基板１１と、基板１１を貫通するビア１２と、ビア１２に電気的に接続された量子ビット素子１３と、ビア１２を介して量子ビット素子１３に電気的に接続された電極１４とを有する。本実施形態において、電子装置１０は、量子ビットデバイスを構成するものである。 [First embodiment]
FIG. 1 is a cross-sectional view showing an example of the configuration of an electronic device 10 according to a first embodiment of the disclosed technology. The electronic device 10 includes a substrate 11, a via 12 penetrating the substrate 11, a quantum bit element 13 electrically connected to the via 12, and an electrode electrically connected to the quantum bit element 13 via the via 12. 14. In this embodiment, the electronic device 10 constitutes a quantum bit device.
　基板１１は、厚さ４００μｍ程度のシリコン単結晶基板である。ビア１２は、基板１１の第１の面Ｓ１から第２の面Ｓ２にまで達する貫通ビア（TSV：Through-Silicon Via）である。ビア１２は、基板１１の材料であるシリコン単結晶によって構成されている。すなわち、ビア１２を構成するシリコン単結晶は、基板１１に由来するものであり、ビア１２を構成するシリコン単結晶は、基板１１を構成するシリコン単結晶と同じ結晶方位を有する。シリコンは、６．７Ｋ以下の温度で超伝導性を発現することから、シリコン単結晶によって構成されるビア１２は、超伝導現象を利用する超伝導デバイスの導電経路として用いることが可能である。 The substrate 11 is a silicon single crystal substrate with a thickness of about 400 μm. The via 12 is a through-silicon via (TSV) that reaches from the first surface S1 to the second surface S2 of the substrate 11. The via 12 is made of silicon single crystal, which is the material of the substrate 11 . That is, the silicon single crystal forming the via 12 originates from the substrate 11, and the silicon single crystal forming the via 12 has the same crystal orientation as the silicon single crystal forming the substrate 11. Since silicon exhibits superconductivity at a temperature of 6.7 K or lower, the via 12 made of silicon single crystal can be used as a conductive path in a superconducting device that utilizes the superconducting phenomenon.
　図１には、単一のビア１２が示されているが、電子装置１０は、複数のビアを含み得る。この場合、複数のビア１２を構成するシリコン単結晶の結晶方位は、互いに同じである。ビア１２の形状は、特に限定されないが、例えば、円柱形状又は角柱形状であってもよい。ビア１２の幅（直径）は、例えば４０μｍ程度である。 Although a single via 12 is shown in FIG. 1, electronic device 10 may include multiple vias. In this case, the crystal orientations of the silicon single crystals forming the plurality of vias 12 are the same. The shape of the via 12 is not particularly limited, but may be, for example, a cylindrical shape or a prismatic shape. The width (diameter) of the via 12 is, for example, about 40 μm.
　電子装置１０は、ビア１２の周囲を囲み、ビア１２と基板１１とを隔てる絶縁体１５を有する。絶縁体１５は、ビア１２と同様、基板１１の第１の面Ｓ１から第２の面Ｓ２にまで達しており、ビア１２の側面全体を覆っている。基板１１とビア１２との間に絶縁体１５が設けられることで、基板１１とビア１２は絶縁される。絶縁体１５の平面視における形状は、環状であり、ビア１２の形状に応じて、円環状、矩形環状、多角形環状とされる。絶縁体１５として例えばＳｉＯ２を用いることができる。 Electronic device 10 includes an insulator 15 that surrounds via 12 and separates via 12 from substrate 11 . Like the via 12, the insulator 15 extends from the first surface S1 to the second surface S2 of the substrate 11, and covers the entire side surface of the via 12. By providing the insulator 15 between the substrate 11 and the via 12, the substrate 11 and the via 12 are insulated. The shape of the insulator 15 in a plan view is annular, and depending on the shape of the via 12, it may be annular, rectangular, or polygonal. For example, SiO 2 can be used as the insulator 15.
　量子ビット素子１３は、基板１１の第１の面Ｓ１の側に設けられている。量子ビット素子１３は、超伝導を用いてコヒーレントな２準位系を形成する素子であり、例えば、超伝導ジョセフソン素子（図示せず）を含んで構成され得る。超伝導ジョセフソン素子は、所定の臨界温度以下の温度で超伝導性を発現する一対の超伝導体と、一対の超伝導体の間に挟まれた厚さ数ｎｍ程度の極薄の絶縁体とを含んで構成されている。超伝導体は例えばＡｌであってもよく、絶縁体は、例えばＡｌ２Ｏ３であってもよい。Ａｌに代えてＮｂを用いることも可能である。図１には、単一の量子ビット素子１３が示されているが、電子装置１０は、複数の量子ビット素子を含み得る。複数の量子ビット素子の各々は隣接する他の量子ビット素子との間で量子もつれ状態を作り出して量子演算を行う。 The quantum bit element 13 is provided on the first surface S1 side of the substrate 11. The quantum bit element 13 is an element that forms a coherent two-level system using superconductivity, and may include, for example, a superconducting Josephson element (not shown). A superconducting Josephson device consists of a pair of superconductors that exhibit superconductivity at a temperature below a predetermined critical temperature, and an extremely thin insulator with a thickness of several nanometers sandwiched between the pair of superconductors. It is composed of: The superconductor may be, for example , Al, and the insulator may be, for example, Al2O3 . It is also possible to use Nb instead of Al. Although a single qubit device 13 is shown in FIG. 1, electronic device 10 may include multiple qubit devices. Each of the plurality of qubit devices creates a quantum entangled state with other adjacent qubit devices to perform quantum operations.
　量子ビット素子１３は、配線１６を介してビア１２に電気的に接続されている。配線１６は、所定の臨界温度以下の温度で超伝導性を発現する金属によって構成される。配線１６の材料として、例えば、Ａｌ又はＴｉＮを用いることができる。なお、図１には、量子ビット素子１３が、ビア１２と重ならない位置に設けられた構成が例示されているが、量子ビット素子１３がビア１２と重なる位置に設けられていてもよい。これにより、配線１６の長さを短くすることが可能となる。量子ビット素子１３及び配線１６は、絶縁膜１７によって覆われている。 The quantum bit element 13 is electrically connected to the via 12 via a wiring 16. The wiring 16 is made of a metal that exhibits superconductivity at a temperature below a predetermined critical temperature. As a material for the wiring 16, for example, Al or TiN can be used. Note that although FIG. 1 illustrates a configuration in which the quantum bit element 13 is provided in a position that does not overlap with the via 12, the quantum bit element 13 may be provided in a position that overlaps with the via 12. This makes it possible to shorten the length of the wiring 16. The quantum bit element 13 and the wiring 16 are covered with an insulating film 17.
　電極１４は、基板１１の第１の面Ｓ１とは反対側の第２の面Ｓ２の側に設けられている。電極１４は、配線１８を介してビア１２に電気的に接続されている。これにより、電極１４は、ビア１２を介して量子ビット素子１３に電気的に接続される。電極１４は、いわゆるバンプの形態を有し、基板１１の第２の面Ｓ２を覆う絶縁膜１９から突出した部分を有する。電極１４は、電子装置１０を配線基板又は他のデバイスに積層する際の、電気的及び機械的接続部として機能する。配線１８及び電極１４は、所定の臨界温度以下の温度で超伝導性を発現する金属によって構成される。配線１８の材料として、例えば、Ａｌ又はＴｉＮを用いることができる。電極１４の材料として、例えばＳｎ、Ｉｎ又はＧａを用いることができる。電極１４と配線１８の間にＵＢＭ(Under Bump Metal）が設けられていてもよい。ＵＢＭは、所定の臨界点以下の温度で超伝導性を発現する金属によって構成される。ＵＢＭの材料として例えばＴｉＮを用いることが可能である。 The electrode 14 is provided on the second surface S2 of the substrate 11, which is opposite to the first surface S1. The electrode 14 is electrically connected to the via 12 via a wiring 18. Thereby, the electrode 14 is electrically connected to the quantum bit element 13 via the via 12. The electrode 14 has a so-called bump shape and has a portion protruding from the insulating film 19 covering the second surface S2 of the substrate 11. Electrode 14 functions as an electrical and mechanical connection when laminating electronic device 10 to a wiring board or other device. The wiring 18 and the electrode 14 are made of a metal that exhibits superconductivity at a temperature below a predetermined critical temperature. As the material of the wiring 18, for example, Al or TiN can be used. As the material of the electrode 14, for example, Sn, In, or Ga can be used. A UBM (Under Bump Metal) may be provided between the electrode 14 and the wiring 18. The UBM is composed of a metal that exhibits superconductivity at a temperature below a predetermined critical point. For example, TiN can be used as the material of the UBM.
　以下に、電子装置１０の製造方法について説明する。図２Ａ～図２Ｇは、電子装置１０の製造方法の一例を示す断面図である。 A method for manufacturing the electronic device 10 will be described below. 2A to 2G are cross-sectional views showing an example of a method for manufacturing the electronic device 10.
　初めに基板１１を用意する。基板１１はシリコン単結晶基板である。基板１１の第１の面Ｓ１に、ＣＶＤ（chemical vapor deposition）により、厚さ１００ｎｍ程度のＳｉＯ２膜２１を形成する。続いて、スパッタ法により、厚さ１μｍ程度の金属膜２２を形成する。金属膜２２の材料として、例えばＡｌを用いることができる（図２Ａ）。なお、金属膜２２に代えてレジストを用いることも可能である。 First, a substrate 11 is prepared. Substrate 11 is a silicon single crystal substrate. A SiO 2 film 21 with a thickness of about 100 nm is formed on the first surface S1 of the substrate 11 by CVD (chemical vapor deposition). Subsequently, a metal film 22 with a thickness of about 1 μm is formed by sputtering. For example, Al can be used as the material of the metal film 22 (FIG. 2A). Note that it is also possible to use a resist instead of the metal film 22.
　次に、反応性イオンエッチングにより、ＳｉＯ２膜２１及び金属膜２２を含む積層膜にパターニングを施す。具体的には、ＳｉＯ２膜２１及び金属膜２２を含む積層膜の、ビア１２の形成予定部位を囲む領域に環状の開口部２３を形成する。これにより、ＳｉＯ２膜２１及び金属膜２２を含むハードマスク２０が構成される（図２Ｂ）。金属膜２２のエッチングには塩素系ガスを用いることができる。ＳｉＯ２膜２１のエッチングにはフロロカーボン系ガスを用いることができる。 Next, the laminated film including the SiO 2 film 21 and the metal film 22 is patterned by reactive ion etching. Specifically, an annular opening 23 is formed in a region of the laminated film including the SiO 2 film 21 and the metal film 22 surrounding the area where the via 12 is to be formed. This forms a hard mask 20 including the SiO 2 film 21 and the metal film 22 (FIG. 2B). Chlorine-based gas can be used for etching the metal film 22. Fluorocarbon gas can be used for etching the SiO 2 film 21.
　次に、ハードマスク２０を介して基板１１をエッチングする。すなわち、基板１１の、ビア１２の形成予定部位を囲む領域を、基板１１の第１の面Ｓ１の側からエッチングする。これにより、ビア１２を画定する環状の溝３０が形成される。溝３０は、第２の面Ｓ２にまで達しない深さで形成される。すなわち、溝３０が基板１１を貫通する前にエッチングが停止される。溝３０の幅は例えば５μｍ程度であり、溝３０の深さは、例えば４５０μｍ程度である（図２Ｃ）。 Next, the substrate 11 is etched through the hard mask 20. That is, a region of the substrate 11 surrounding the portion where the via 12 is to be formed is etched from the first surface S1 side of the substrate 11. This forms an annular groove 30 that defines the via 12. The groove 30 is formed to a depth that does not reach the second surface S2. That is, etching is stopped before the groove 30 penetrates the substrate 11. The width of the groove 30 is, for example, about 5 μm, and the depth of the groove 30 is, for example, about 450 μm (FIG. 2C).
　本エッチング工程においては、形成途中の溝３０の側面を保護膜で覆うステップと、形成途中の溝３０の底面を更にエッチングするステップとが交互に実施する手法を用いてもよい。溝３０の側面を保護膜で覆うことで、溝３０の底面のエッチングにおいて、溝３０の側面のエッチングが抑制される。溝３０の側面を保護膜で覆うステップではＣＦガスが用いられ、溝３０の底面をエッチングするステップではＳＦ６ガスが用いられる。このエッチングプロセスは、Bosch Processと称され、シリコン基板の深堀りに適用される。 In this etching process, a method may be used in which the step of covering the side surfaces of the groove 30 that is being formed with a protective film and the step of further etching the bottom surface of the groove 30 that is being formed are performed alternately. By covering the side surfaces of the groove 30 with the protective film, etching of the side surface of the groove 30 is suppressed during etching of the bottom surface of the groove 30. CF gas is used in the step of covering the side surfaces of the trench 30 with a protective film, and SF6 gas is used in the step of etching the bottom surface of the trench 30. This etching process is called the Bosch Process and is applied to deep trenches in silicon substrates.
　次に、ハードマスク２０を構成する金属膜２２を、薬液を用いて除去した後、ＣＶＤにより、溝３０にＳｉＯ２等の絶縁体１５を埋め込む（図２Ｄ）。 Next, after removing the metal film 22 constituting the hard mask 20 using a chemical solution, the groove 30 is filled with an insulator 15 such as SiO 2 by CVD (FIG. 2D).
　次に、基板１１の第２の面Ｓ２を研削して、第２の面Ｓ２において絶縁体１５を露出させる（図２Ｅ）。これにより、基板１１を貫通し、基板１１と同じ結晶方位を有するシリコン単結晶からなるビア１２が形成される。ビア１２は、その側面全体を覆う絶縁体１５によって、基板１１から絶縁される。また、基板１１の研削により、基板１１は、厚さ４００μｍ程度にまで薄化される。 Next, the second surface S2 of the substrate 11 is ground to expose the insulator 15 on the second surface S2 (FIG. 2E). As a result, a via 12 made of silicon single crystal that penetrates the substrate 11 and has the same crystal orientation as the substrate 11 is formed. Via 12 is insulated from substrate 11 by an insulator 15 covering all of its sides. Further, by grinding the substrate 11, the substrate 11 is thinned to a thickness of about 400 μm.
　次に、基板１１の第１の面Ｓ１に、量子ビット素子１３を形成する（図２Ｆ）。量子ビット素子１３を構成する超伝導ジョセフソン素子は、例えば、蒸着法によってＡｌを含む第１電極（図示せず）を形成する工程、ＡＬＤ(Atomic Layer Deposition)によって第１電極の表面に厚さ数ｎｍ程度の極薄のＡｌ２Ｏ３膜（図示せず）を形成する工程、蒸着法によってＡｌ２Ｏ３膜の表面にＡｌを含む第２電極（図示せず）を形成する工程を経ることによって形成される。第１電極及び第２電極のパターニングは、例えば、パターニングされたレジスト（図示せず）を用いたリフトオフ法によって行ってもよい。この場合、レジストの開口パターンを、第１の方向に沿った第１の直線部と、第１の方向と直交する第２の方向に沿った第２の直線部とを含む十字型とし、第１の方向を回転軸として傾けて蒸着を行うことで、第１の直線部に対応する部分に第１電極を形成してもよい。続いて、第２の方向を回転軸として傾けて蒸着を行うことで、第２の直線部に対応する部分に第２電極を形成してもよい。上記の方法によれば、第１電極及び第２電極のパターニングを単一のレジストによって行うことが可能となる。 Next, the quantum bit element 13 is formed on the first surface S1 of the substrate 11 (FIG. 2F). The superconducting Josephson element constituting the quantum bit element 13 is manufactured by forming a first electrode (not shown) containing Al by vapor deposition, for example, or by forming a thickness on the surface of the first electrode by ALD (Atomic Layer Deposition). A process of forming an extremely thin Al 2 O 3 film (not shown) of approximately several nm, and a process of forming a second electrode (not shown) containing Al on the surface of the Al 2 O 3 film by vapor deposition. formed by Patterning of the first electrode and the second electrode may be performed, for example, by a lift-off method using a patterned resist (not shown). In this case, the opening pattern of the resist is a cross shape including a first straight line section along the first direction and a second straight line section along the second direction perpendicular to the first direction, and The first electrode may be formed in a portion corresponding to the first linear portion by performing vapor deposition with the first direction as the rotation axis. Subsequently, the second electrode may be formed in a portion corresponding to the second linear portion by performing vapor deposition with the second direction as the rotation axis. According to the above method, it is possible to pattern the first electrode and the second electrode using a single resist.
　次に、スパッタ法及びエッチング法を用いて量子ビット素子１３とビア１２とを接続する配線１６を形成する（図２Ｆ）。配線１６の材料として、例えばＡｌ又はＴｉＮを用いることができる。次に、ＣＶＤにより、量子ビット素子１３及び配線１６を覆うＳｉＯ２等の絶縁体からなる絶縁膜１７を、基板１１の第１の面Ｓ１上に形成する（図２Ｆ）。 Next, a wiring 16 connecting the quantum bit element 13 and the via 12 is formed using a sputtering method and an etching method (FIG. 2F). As a material for the wiring 16, for example, Al or TiN can be used. Next, an insulating film 17 made of an insulator such as SiO 2 that covers the quantum bit element 13 and the wiring 16 is formed on the first surface S1 of the substrate 11 by CVD (FIG. 2F).
　次に、スパッタ法及びエッチング法を用いて基板１１の第２の面Ｓ２の側に、ビア１２に接続された配線１８を形成する（図２Ｇ）。配線１８の材料として、例えばＡｌ又はＴｉＮを用いることができる。次に、ＣＶＤにより配線１８を覆うＳｉＯ２等の絶縁体からなる絶縁膜１９を基板１１の第２の面Ｓ２上に形成する（図２Ｇ）。次に、エッチング法により、配線１８を部分的に露出させる開口部を絶縁膜１９に形成する。次に、めっき法を用いて配線１８の露出部分に電極１４を形成する（図２Ｇ）。電極１４の材料として、例えばＳｎ、Ｉｎ又はＧａを用いることができる。 Next, the wiring 18 connected to the via 12 is formed on the second surface S2 side of the substrate 11 using a sputtering method and an etching method (FIG. 2G). As a material for the wiring 18, for example, Al or TiN can be used. Next, an insulating film 19 made of an insulator such as SiO 2 that covers the wiring 18 is formed on the second surface S2 of the substrate 11 by CVD (FIG. 2G). Next, an opening that partially exposes the wiring 18 is formed in the insulating film 19 by an etching method. Next, the electrode 14 is formed on the exposed portion of the wiring 18 using a plating method (FIG. 2G). As the material of the electrode 14, for example, Sn, In, or Ga can be used.
　ここで、ビア１２の長さが長くなる程、より深い溝３０の形成が必要となる。しかしながら、溝３０の幅に対する溝３０の深さの割合であるアスペクト比（深さ／幅）が、例えば１００を超えると、エッチングによる溝３０の形成が困難となる。図３Ａ～図３Ｅは、ビア１２の長さが長くなる場合にも適用可能なビア１２の形成工程を含む電子装置１０の製造方法の一例を示す断面図である。 Here, the longer the length of the via 12, the deeper the groove 30 needs to be formed. However, if the aspect ratio (depth/width), which is the ratio of the depth of the groove 30 to the width of the groove 30, exceeds 100, for example, it becomes difficult to form the groove 30 by etching. 3A to 3E are cross-sectional views showing an example of a method for manufacturing the electronic device 10 including a step of forming the via 12, which is applicable even when the length of the via 12 becomes long.
　基板１１の第１の面Ｓ１に形成されたハードマスク２０Ａを用いて、基板１１の、ビア１２の形成予定部位を囲む領域を、基板１１の第１の面Ｓ１の側からエッチングする。これにより、ビアの第１の部分１２Ａを画定する環状の第１の溝３０Ａが形成される。第１の溝３０Ａは、第２の面Ｓ２にまで達しない深さで形成される（図３Ａ）。 Using the hard mask 20A formed on the first surface S1 of the substrate 11, a region of the substrate 11 surrounding the area where the via 12 is to be formed is etched from the first surface S1 side of the substrate 11. This forms an annular first groove 30A that defines a first portion 12A of the via. The first groove 30A is formed to a depth that does not reach the second surface S2 (FIG. 3A).
　次に、ハードマスク２０Ａを構成する金属膜２２を、薬液を用いて除去した後、ＣＶＤにより、第１の溝３０ＡにＳｉＯ２等の絶縁体１５を埋め込む（図３Ｂ）。ここまでの工程は、図２Ａ～図２Ｄに示されたものと同様である。 Next, after removing the metal film 22 constituting the hard mask 20A using a chemical solution, the first trench 30A is filled with an insulator 15 such as SiO 2 by CVD (FIG. 3B). The steps up to this point are similar to those shown in FIGS. 2A to 2D.
　次に、基板１１の第２の面Ｓ２に、第１の面Ｓ１に形成されたハードマスク２０Ａと同様のハードマスク２０Ｂを形成し、ハードマスク２０Ｂを用いて、基板１１の、ビア１２の形成予定部位を囲む領域を、基板１１の第２の面Ｓ２の側からエッチングする。これにより、ビアの第２の部分１２Ｂを画定する環状の第２の溝３０Ｂが形成される。第２の溝３０は、第１の溝３０に埋め込まれた絶縁体１５にまで到達する深さを有する。これにより、ビア１２の第１の部分１２Ａと、ビアの第２の部分１２Ｂとが連結され、基板１１を貫通するビア１２が形成される（図３Ｃ）。 Next, a hard mask 20B similar to the hard mask 20A formed on the first surface S1 is formed on the second surface S2 of the substrate 11, and vias 12 are formed on the substrate 11 using the hard mask 20B. A region surrounding the planned site is etched from the second surface S2 side of the substrate 11. This forms a second annular groove 30B that defines the second portion 12B of the via. The second groove 30 has a depth that reaches the insulator 15 embedded in the first groove 30. As a result, the first portion 12A of the via 12 and the second portion 12B of the via are connected, and the via 12 penetrating the substrate 11 is formed (FIG. 3C).
　次に、ハードマスク２０Ｂを構成する金属膜２２を、薬液を用いて除去した後、ＣＶＤにより、第２の溝３０ＢにＳｉＯ２等の絶縁体１５を埋め込む（図３Ｄ）。次に、基板１１の第１の面Ｓ１に、量子ビット素子１３を形成し、量子ビット素子１３とビア１２とを接続する配線１６を形成し、量子ビット素子１３及び配線１６を覆うＳｉＯ２等の絶縁体からなる絶縁膜１７を、基板１１の第１の面Ｓ１上に形成する。その後、基板１１の第２の面Ｓ２の側にビア１２に接続された配線１８を形成し、配線１８を覆うＳｉＯ２等の絶縁体からなる絶縁膜１９を基板１１の第２の面Ｓ２上に形成し、配線１８の露出部分に電極１４を形成する（図３Ｅ）。 Next, after removing the metal film 22 constituting the hard mask 20B using a chemical solution, the second groove 30B is filled with an insulator 15 such as SiO 2 by CVD (FIG. 3D). Next, a quantum bit element 13 is formed on the first surface S1 of the substrate 11, a wiring 16 connecting the quantum bit element 13 and the via 12 is formed, and SiO 2 or the like is formed to cover the quantum bit element 13 and the wiring 16. An insulating film 17 made of an insulator is formed on the first surface S1 of the substrate 11. Thereafter, wiring 18 connected to the via 12 is formed on the second surface S2 of the substrate 11, and an insulating film 19 made of an insulator such as SiO 2 covering the wiring 18 is formed on the second surface S2 of the substrate 11. The electrode 14 is formed on the exposed portion of the wiring 18 (FIG. 3E).
　以上のように、開示の技術の第１の実施形態に係る電子装置１０は、基板１１を貫通するシリコン単結晶を含む少なくとも１つのビア１２を有する。シリコンは、６．７Ｋ以下の温度で超伝導性を発現することから、シリコン単結晶によって構成されるビア１２は、超伝導現象を利用する超伝導デバイスの導電経路として用いることが可能である。ビア１２をシリコン単結晶によって構成することで、Ｃｕ等の超伝導性を発現しない物質がビア１２内に拡散することはない。従って、本実施形態に係る電子装置１０は、超伝導デバイスへの適用が可能である。 As described above, the electronic device 10 according to the first embodiment of the disclosed technology has at least one via 12 containing silicon single crystal that penetrates the substrate 11. Since silicon exhibits superconductivity at a temperature of 6.7 K or lower, the via 12 made of silicon single crystal can be used as a conductive path in a superconducting device that utilizes the superconducting phenomenon. By forming the via 12 with silicon single crystal, a substance that does not exhibit superconductivity, such as Cu, will not diffuse into the via 12. Therefore, the electronic device 10 according to this embodiment can be applied to superconducting devices.
　また、本実施形態に係る電子装置１０は、基板１１がビア１２と同じシリコン単結晶によって構成される。基板１１とビア１２とが異なる材料によって構成される場合には、基板１１とビア１２との熱膨張係数の差に起因して、温度変化に伴って基板１１に反りが発生するおそれがある。超伝導デバイスは、極低温環境で使用されることが想定され、温度変化が非常に大きいため、基板１１とビア１２の熱膨張係数の差が小さいことが好ましい。本実施形態に係る電子装置１０によれば、ビア１２が基板１１と同じシリコン単結晶によって構成されるので、基板１１及びビア１２の熱膨張係数を等しくすることができ、温度変化に伴う基板１１の反りの発生を抑制することが可能となる。 Furthermore, in the electronic device 10 according to this embodiment, the substrate 11 is made of the same silicon single crystal as the vias 12. If the substrate 11 and the vias 12 are made of different materials, there is a risk that the substrate 11 will warp due to temperature changes due to the difference in thermal expansion coefficients between the substrate 11 and the vias 12. Since superconducting devices are assumed to be used in extremely low temperature environments and the temperature changes are very large, it is preferable that the difference in thermal expansion coefficients between the substrate 11 and the vias 12 be small. According to the electronic device 10 according to the present embodiment, since the vias 12 are made of the same silicon single crystal as the substrate 11, the thermal expansion coefficients of the substrate 11 and the vias 12 can be made equal, and the substrate It becomes possible to suppress the occurrence of warpage.
　基板に設けられた貫通孔に超伝導部材を埋め込むことによりビアを形成する場合、貫通孔内に超伝導部材の未充填部分（ボイド）が形成されるおそれがある。本実施形態に係る電子装置１０は、基板１１にビア１２を画定する溝３０を形成することによりビア１２が形成されるので、ビア１２内にボイドが発生する問題を回避することができる。 When a via is formed by burying a superconducting member in a through hole provided in a substrate, there is a risk that an unfilled portion (void) of the superconducting member may be formed in the through hole. In the electronic device 10 according to the present embodiment, the via 12 is formed by forming the groove 30 that defines the via 12 in the substrate 11, so that the problem of voids occurring in the via 12 can be avoided.
　なお、以上の説明では、量子ビットデバイスに開示の技術を適用する場合を例示したが、開示の技術は、この態様に限定されるものではない。例えば、量子ビットデバイスを制御するための制御デバイスに開示の技術を適用することも可能である。また、量子ビットデバイスの入出力信号を中継するインターポーザに開示の技術を適用することも可能である。また、以上の説明では、量子ビット素子が、ジョセフソン素子等の超伝導量子ビット素子である場合を例示したが、量子ビット素子は、シリコン量子ビット素子であってよい。 Note that in the above description, the case where the disclosed technology is applied to a quantum bit device has been exemplified, but the disclosed technology is not limited to this aspect. For example, it is also possible to apply the disclosed technology to a control device for controlling a quantum bit device. Further, the disclosed technology can also be applied to an interposer that relays input/output signals of a quantum bit device. Furthermore, in the above description, the quantum bit device is a superconducting quantum bit device such as a Josephson device, but the quantum bit device may be a silicon quantum bit device.
　図４は、基板１１の構成の一例を示す平面図である。図４に示すように、基板１１には、複数のビア１２が密集して設けられていてもよい。複数のビア１２の各々は、基板１１を構成するシリコン単結晶と同じ結晶方位を有するシリコン単結晶によって構成されている。ビア１２の各々は、周囲を絶縁体１５によって囲まれており、他のビア１２及び基板１１から絶縁されている。複数のビア１２は、基板１１の第１の面Ｓ１と第２の面Ｓ２との間の導電経路として、これらの全てが使用されてもよいし、これらのうちの一部が使用されてもよい。図４には、平面視における形状が円形であるビア１２が例示されているが、ビア１２の平面視における形状は、四角形、六角形又はその他の多角形であってもよい。 FIG. 4 is a plan view showing an example of the configuration of the substrate 11. As shown in FIG. 4, a plurality of vias 12 may be provided in the substrate 11 in a dense manner. Each of the plurality of vias 12 is made of a silicon single crystal having the same crystal orientation as the silicon single crystal forming the substrate 11 . Each of the vias 12 is surrounded by an insulator 15 and is insulated from other vias 12 and the substrate 11 . All or some of the plurality of vias 12 may be used as a conductive path between the first surface S1 and the second surface S2 of the substrate 11. good. Although FIG. 4 shows an example of a via 12 having a circular shape in a plan view, the shape of the via 12 in a plan view may be a quadrilateral, a hexagon, or another polygon.
［第２の実施形態］
　図５は、開示の技術の第２の実施形態に係る電子装置１０Ａの構成の一例を示す図である。電子装置１０Ａは、基板１１が絶縁体４０によって構成されている点が、上記した第１の実施形態に係る電子装置１０と異なる。ビア１２は、第１の実施形態に係る電子装置１０と同様、シリコン単結晶によって構成される。基板１１を構成する絶縁体４０としてＳｉＯ２を用いることができる。また、製造効率を重視する場合、基板１１を構成する絶縁体４０としてモールド樹脂を用いてもよい。モールド樹脂は、例えば、エポキシ樹脂に、シリカフィラーを含有させたものを用いることができる。 [Second embodiment]
FIG. 5 is a diagram illustrating an example of the configuration of an electronic device 10A according to the second embodiment of the disclosed technology. The electronic device 10A differs from the electronic device 10 according to the first embodiment described above in that the substrate 11 is made of an insulator 40. The via 12 is made of silicon single crystal similarly to the electronic device 10 according to the first embodiment. SiO 2 can be used as the insulator 40 that constitutes the substrate 11. Furthermore, when manufacturing efficiency is important, a molded resin may be used as the insulator 40 constituting the substrate 11. As the molding resin, for example, an epoxy resin containing silica filler can be used.
　以下に、電子装置１０Ａの製造方法について説明する。図６Ａ～図６Ｇは、電子装置１０の製造方法の一例を示す断面図である。 A method for manufacturing the electronic device 10A will be described below. 6A to 6G are cross-sectional views showing an example of a method for manufacturing the electronic device 10.
　初めに基板１１を用意する。基板１１はシリコン単結晶基板である。基板１１の第１の面Ｓ１に、ＣＶＤにより、厚さ１００ｎｍ程度のＳｉＯ２膜２１を形成する。続いて、スパッタ法により、厚さ１μｍ程度の金属膜２２を形成する。金属膜２２の材料として、例えばＡｌを用いることができる（図６Ａ）。なお、金属膜２２に代えてレジストを用いることも可能である。 First, a substrate 11 is prepared. Substrate 11 is a silicon single crystal substrate. A SiO 2 film 21 with a thickness of about 100 nm is formed on the first surface S1 of the substrate 11 by CVD. Subsequently, a metal film 22 with a thickness of about 1 μm is formed by sputtering. For example, Al can be used as the material of the metal film 22 (FIG. 6A). Note that it is also possible to use a resist instead of the metal film 22.
　次に、反応性イオンエッチングにより、ＳｉＯ２膜２１及び金属膜２２を含む積層膜にパターニングを施す。具体的には、ＳｉＯ２膜２１及び金属膜２２を含む積層膜の、ビア１２の形成予定部位を囲む領域に開口部２３を形成する。これにより、ＳｉＯ２膜２１及び金属膜２２を含むハードマスク２０が構成される。本実施形態においては、ビア１２の形成予定部位のみがハードマスク２０によって覆われる（図６Ｂ）。 Next, the laminated film including the SiO 2 film 21 and the metal film 22 is patterned by reactive ion etching. Specifically, an opening 23 is formed in a region of the laminated film including the SiO 2 film 21 and the metal film 22 surrounding the area where the via 12 is to be formed. As a result, a hard mask 20 including the SiO 2 film 21 and the metal film 22 is formed. In this embodiment, only the portion where the via 12 is to be formed is covered with the hard mask 20 (FIG. 6B).
　次に、ハードマスク２０を介して基板１１をエッチングする。すなわち、基板１１の、ビア１２の形成予定部位を囲む領域を、基板１１の第１の面Ｓ１の側からエッチングする。本実施形態においては、ビア１２を切り出すように基板１１の、ビア１２の形成予定部位以外の部位をエッチングする。これにより、ビア１２を画定する溝３０が形成される。溝３０は、第２の面Ｓ２にまで達しない深さで形成される。すなわち、溝３０が基板１１を貫通する前にエッチングが停止される（図６Ｃ）。 Next, the substrate 11 is etched through the hard mask 20. That is, a region of the substrate 11 surrounding the portion where the via 12 is to be formed is etched from the first surface S1 side of the substrate 11. In this embodiment, a portion of the substrate 11 other than the portion where the via 12 is planned to be formed is etched so as to cut out the via 12 . As a result, grooves 30 defining vias 12 are formed. The groove 30 is formed to a depth that does not reach the second surface S2. That is, etching is stopped before the groove 30 penetrates the substrate 11 (FIG. 6C).
　次に、ハードマスク２０を構成する金属膜２２を、薬液を用いて除去した後、ＣＶＤにより、溝３０にＳｉＯ２等の絶縁体４０を埋め込む。絶縁体４０としてモールド樹脂を用いることも可能である。基板１１の部材は、ビア１２を構成する部分を除き、シリコン単結晶から絶縁体４０に置き換わる。シリコン単結晶基板のビア１２を構成する部分は、絶縁体４０の内部に埋設される（図６Ｄ）。 Next, after removing the metal film 22 constituting the hard mask 20 using a chemical solution, the groove 30 is filled with an insulator 40 such as SiO 2 by CVD. It is also possible to use molded resin as the insulator 40. The members of the substrate 11, except for the portions forming the vias 12, are replaced by the insulator 40 from silicon single crystal. A portion of the silicon single crystal substrate constituting the via 12 is buried inside the insulator 40 (FIG. 6D).
　次に、基板１１の第１の面Ｓ１を（絶縁体４０の上面）を研削して、ビア１２の上端を露出させる。続いて、基板１１の第２の面Ｓ２（シリコン単結晶基板の下面）を研削して、ビア１２の下端を露出させる。これにより、基板１１（絶縁体４０）を貫通するシリコン単結晶からなるビア１２が形成される（図６Ｅ）。 Next, the first surface S1 of the substrate 11 (the upper surface of the insulator 40) is ground to expose the upper end of the via 12. Subsequently, the second surface S2 of the substrate 11 (the lower surface of the silicon single crystal substrate) is ground to expose the lower ends of the vias 12. As a result, a via 12 made of silicon single crystal and penetrating the substrate 11 (insulator 40) is formed (FIG. 6E).
　次に、基板１１の第１の面Ｓ１に、量子ビット素子１３を形成する（図６Ｆ）。続いて、スパッタ法及びエッチング法を用いて量子ビット素子１３とビア１２とを接続する配線１６を形成する（図６Ｆ）。配線１６の材料として、例えばＡｌを用いることができる。次に、ＣＶＤにより、量子ビット素子１３及び配線１６を覆うＳｉＯ２等の絶縁体からなる絶縁膜１７を基板１１の第１の面Ｓ１上に形成する（図６Ｆ）。 Next, the quantum bit element 13 is formed on the first surface S1 of the substrate 11 (FIG. 6F). Subsequently, a wiring 16 connecting the quantum bit element 13 and the via 12 is formed using a sputtering method and an etching method (FIG. 6F). For example, Al can be used as a material for the wiring 16. Next, an insulating film 17 made of an insulator such as SiO 2 that covers the quantum bit element 13 and the wiring 16 is formed on the first surface S1 of the substrate 11 by CVD (FIG. 6F).
　次に、スパッタ法及びエッチング法を用いて基板１１の第２の面Ｓ２の側に、ビア１２に接続された配線１８を形成する（図６Ｇ）。配線１８の材料として、例えばＡｌを用いることができる。次に、ＣＶＤにより配線１８を覆うＳｉＯ２等の絶縁体からなる絶縁膜１９を、基板１１の第２の面Ｓ２上に形成する（図６Ｇ）。次に、エッチング法により、配線１８を部分的に露出させる開口部を絶縁膜１９に形成する。次に、めっき法を用いて配線１８の露出部分に電極１４を形成する（図６Ｇ）。電極１４の材料として、例えばＳｎ、Ｉｎ又はＧａを用いることができる。 Next, the wiring 18 connected to the via 12 is formed on the second surface S2 side of the substrate 11 using a sputtering method and an etching method (FIG. 6G). For example, Al can be used as the material for the wiring 18. Next, an insulating film 19 made of an insulator such as SiO 2 that covers the wiring 18 is formed on the second surface S2 of the substrate 11 by CVD (FIG. 6G). Next, an opening that partially exposes the wiring 18 is formed in the insulating film 19 by an etching method. Next, the electrode 14 is formed on the exposed portion of the wiring 18 using a plating method (FIG. 6G). As the material of the electrode 14, for example, Sn, In, or Ga can be used.
　以上のように、開示の技術の第２の実施形態に係る電子装置１０Ａは、基板１１を貫通するシリコン単結晶を含む少なくとも１つのビア１２を有し、基板１１が絶縁体４０によって構成されている。本実施形態に係る電子装置１０Ａは、第１の実施形態に係る電子装置１０と同様、超伝導デバイスへの適用が可能である。 As described above, the electronic device 10A according to the second embodiment of the disclosed technology has at least one via 12 containing silicon single crystal that penetrates the substrate 11, and the substrate 11 is made of the insulator 40. There is. The electronic device 10A according to this embodiment can be applied to a superconducting device like the electronic device 10 according to the first embodiment.
［第３の実施形態］
　図７は、開示の技術の第３の実施形態に係る電子システム１００の構成の一例を示す断面図である。電子システム１００は、量子ビットデバイスを構成する電子装置１０Ｂと、電子装置１０Ｂを制御するための制御デバイスを構成する電子装置１０Ｃとを有する。電子装置１０Ｂは、配線基板５０上に搭載されており、電子装置１０Ｃは、電子装置１０Ｂ上に積層されている。 [Third embodiment]
FIG. 7 is a cross-sectional view showing an example of the configuration of an electronic system 100 according to a third embodiment of the disclosed technology. The electronic system 100 includes an electronic device 10B that constitutes a quantum bit device, and an electronic device 10C that constitutes a control device for controlling the electronic device 10B. The electronic device 10B is mounted on the wiring board 50, and the electronic device 10C is stacked on the electronic device 10B.
　量子ビットデバイスを構成する電子装置１０Ｂは、基板１１の第１の面Ｓ１の側に設けられた複数の量子ビット素子１３と、複数の量子ビット素子１３に電気的に接続された複数のビア１２を有する。基板１１はシリコン単結晶基板であり、複数のビア１２の各々は、基板１１を構成するシリコン単結晶と同じ結晶方位を有するシリコン単結晶によって構成されている。絶縁体１５は、ビアの周囲を囲み、ビア１２と基板１１とを隔てている。基板１１の第２の面Ｓ２には、複数の電極１４が設けられている。複数の電極１４の少なくとも一部は、ビア１２を介して量子ビット素子１３に電気的に接続されている。複数の電極１４は、電子装置１０Ｂを配線基板５０上に搭載する際の、電気的及び機械的接続部として機能する。 The electronic device 10B constituting the quantum bit device includes a plurality of quantum bit elements 13 provided on the first surface S1 side of the substrate 11, and a plurality of vias 12 electrically connected to the plurality of quantum bit elements 13. has. The substrate 11 is a silicon single crystal substrate, and each of the plurality of vias 12 is made of a silicon single crystal having the same crystal orientation as the silicon single crystal forming the substrate 11. Insulator 15 surrounds the via and separates via 12 from substrate 11 . A plurality of electrodes 14 are provided on the second surface S2 of the substrate 11. At least some of the plurality of electrodes 14 are electrically connected to the quantum bit element 13 via the via 12. The plurality of electrodes 14 function as electrical and mechanical connections when mounting the electronic device 10B on the wiring board 50.
　制御デバイスを構成する電子装置１０Ｃは、シリコン単結晶等の半導体によって構成された基板６０の表面に形成されたトランジスタ等の回路素子６１と、回路素子６１に電気的に接続された複数の電極６２を有する。電極６２はいわゆるバンプの形態を有し、基板６０の表面を覆う絶縁膜６３から突出した部分を有する。複数の電極６２の各々は、電子装置１０Ｂの表面に設けられた電極パッド７０に接続されている。電極パッド７０の少なくとも一部は、量子ビット素子１３に電気的に接続されている。電子装置１０Ｃは、フェイスダウンの形態で電子装置１０Ｂ上に積層されている。電子装置１０Ｃは、例えば、量子ビット素子１３から出力される信号を読み出す制御を行う。なお、制御デバイスを構成する電子装置１０Ｃは、フェイスアップの形態で電子装置１０Ｂ上に積層されてもよい。この場合、電子装置１０Ｃには、基板６０を貫通するビアが設けられる。 The electronic device 10C constituting the control device includes a circuit element 61 such as a transistor formed on the surface of a substrate 60 made of a semiconductor such as silicon single crystal, and a plurality of electrodes 62 electrically connected to the circuit element 61. has. The electrode 62 has a so-called bump shape and has a portion protruding from the insulating film 63 covering the surface of the substrate 60. Each of the plurality of electrodes 62 is connected to an electrode pad 70 provided on the surface of the electronic device 10B. At least a portion of electrode pad 70 is electrically connected to quantum bit element 13 . The electronic device 10C is stacked face down on the electronic device 10B. The electronic device 10C controls, for example, reading out the signal output from the quantum bit element 13. Note that the electronic device 10C constituting the control device may be stacked face-up on the electronic device 10B. In this case, the electronic device 10C is provided with a via that penetrates the substrate 60.
　図８は、変形例に係る電子システム１００Ａの構成の他の例を示す断面図である。電子システム１００Ａは、量子ビットデバイスを構成する電子装置１０Ｂと、電子装置１０Ｂを制御する制御デバイスを構成する電子装置１０Ｃと、を有する。電子装置１０Ｃは、配線基板５０上に搭載されており、電子装置１０Ｂは、電子装置１０Ｃ上に積層されている。 FIG. 8 is a cross-sectional view showing another example of the configuration of an electronic system 100A according to a modification. The electronic system 100A includes an electronic device 10B that constitutes a quantum bit device, and an electronic device 10C that constitutes a control device that controls the electronic device 10B. The electronic device 10C is mounted on the wiring board 50, and the electronic device 10B is stacked on the electronic device 10C.
　制御デバイスを構成する電子装置１０Ｃは、基板６０の上面側に設けられたトランジスタ等の複数の回路素子６１と、複数の回路素子６１に電気的に接続された複数のビア６４を有する。基板６０はシリコン単結晶基板であり、複数のビア６４の各々は、基板６０を構成するシリコン単結晶と同じ結晶方位を有するシリコン単結晶によって構成されている。絶縁体６５は、ビアの周囲を囲み、ビア６４と基板６０とを隔てている。基板６０の下面側には、複数の電極６２が設けられている。複数の電極６２の少なくとも一部は、ビア６４を介して回路素子６１に電気的に接続されている。複数の電極６２は、電子装置１０Ｃを配線基板５０上に搭載する際の、電気的及び機械的接続部として機能する。 The electronic device 10C constituting the control device has a plurality of circuit elements 61 such as transistors provided on the upper surface side of the substrate 60, and a plurality of vias 64 electrically connected to the plurality of circuit elements 61. The substrate 60 is a silicon single crystal substrate, and each of the plurality of vias 64 is made of a silicon single crystal having the same crystal orientation as the silicon single crystal forming the substrate 60. An insulator 65 surrounds the via and separates the via 64 from the substrate 60. A plurality of electrodes 62 are provided on the lower surface side of the substrate 60. At least some of the plurality of electrodes 62 are electrically connected to the circuit element 61 via vias 64. The plurality of electrodes 62 function as electrical and mechanical connections when the electronic device 10C is mounted on the wiring board 50.
　量子ビットデバイスを構成する電子装置１０Ｂは、基板１１の表面に形成された量子ビット素子１３と、量子ビット素子１３に電気的に接続された複数の電極１４を有する。複数の電極１４の各々は、電子装置１０Ｃの表面に設けられた電極パッド６６に接続されている。複数の電極パッド６６の少なくとも一部は、回路素子６１に電気的に接続されている。電子装置１０Ｂは、フェイスダウンの形態で電子装置１０Ｃ上に積層されている。電子装置１０Ｃは、例えば、量子ビット素子１３から出力される信号を読み出す制御を行う。なお、量子ビットデバイスを構成する電子装置１０Ｂは、フェイスアップの形態で電子装置１０Ｃ上に積層されてもよい。この場合、電子装置１０Ｂには、基板１１を貫通するビアが設けられる。 The electronic device 10B constituting the quantum bit device has a quantum bit element 13 formed on the surface of the substrate 11 and a plurality of electrodes 14 electrically connected to the quantum bit element 13. Each of the plurality of electrodes 14 is connected to an electrode pad 66 provided on the surface of the electronic device 10C. At least some of the plurality of electrode pads 66 are electrically connected to the circuit element 61. The electronic device 10B is stacked face down on the electronic device 10C. The electronic device 10C controls, for example, reading out the signal output from the quantum bit element 13. Note that the electronic device 10B constituting the quantum bit device may be stacked face-up on the electronic device 10C. In this case, the electronic device 10B is provided with a via penetrating the substrate 11.
　図９は、変形例に係る電子システム１００Ｂの構成の他の例を示す断面図である。電子システム１００Ｂは、量子ビットデバイスを構成する電子装置１０Ｂと、電子装置１０Ｂを制御する制御デバイスを構成する電子装置１０Ｃと、電子装置１０Ｂと電子装置１０Ｃとの間で送受信される信号を中継するインターポーザを構成する電子装置１０Ｄとを有する。 FIG. 9 is a sectional view showing another example of the configuration of an electronic system 100B according to a modification. The electronic system 100B relays signals transmitted and received between the electronic device 10B that constitutes a quantum bit device, the electronic device 10C that constitutes a control device that controls the electronic device 10B, and the electronic device 10B and the electronic device 10C. and an electronic device 10D that constitutes an interposer.
　制御デバイスを構成する電子装置１０Ｃは、配線基板５０上に搭載されており、インターポーザを構成する電子装置１０Ｄは、電子装置１０Ｃ上に積層されており、量子ビットデバイスを構成する電子装置１０Ｂは、電子装置１０Ｄ上に積層されている。すなわち、インターポーザを構成する電子装置１０Ｄは、量子ビットデバイスを構成する電子装置１０Ｂと制御デバイスを構成する電子装置１０Ｃとの間に設けられている。電子装置１０Ｂ及び電子装置１０Ｃの構成は、図８に示されたものと同じである。 An electronic device 10C that constitutes a control device is mounted on the wiring board 50, an electronic device 10D that constitutes an interposer is stacked on the electronic device 10C, and an electronic device 10B that constitutes a quantum bit device. It is stacked on the electronic device 10D. That is, the electronic device 10D forming the interposer is provided between the electronic device 10B forming the quantum bit device and the electronic device 10C forming the control device. The configurations of the electronic device 10B and the electronic device 10C are the same as those shown in FIG.
　インターポーザを構成する電子装置１０Ｄは、基板８０を貫通する複数のビア８１を有する。基板８０はシリコン単結晶基板であり、複数のビア８１の各々は、基板８０を構成するシリコン単結晶と同じ結晶方位を有するシリコン単結晶によって構成されている。絶縁体８２は、ビア８１の周囲を囲み、ビア８１と基板８０とを隔てている。基板８０の下面には、複数の電極８３が設けられている。複数の電極８３の各々は、制御デバイスを構成する電子装置１０Ｃの表面に設けられた電極パッド６６に接続されている。電極パッド６６の少なくとも一部は、回路素子６１に電気的に接続されている。 The electronic device 10D that constitutes the interposer has a plurality of vias 81 that penetrate the substrate 80. The substrate 80 is a silicon single crystal substrate, and each of the plurality of vias 81 is made of a silicon single crystal having the same crystal orientation as the silicon single crystal forming the substrate 80. Insulator 82 surrounds via 81 and separates via 81 from substrate 80 . A plurality of electrodes 83 are provided on the lower surface of the substrate 80. Each of the plurality of electrodes 83 is connected to an electrode pad 66 provided on the surface of the electronic device 10C that constitutes the control device. At least a portion of the electrode pad 66 is electrically connected to the circuit element 61.
　量子ビットデバイスを構成する電子装置１０Ｂが備える複数の電極１４の各々は、インターポーザを構成する電子装置１０Ｄの表面に設けられた電極パッド８４に接続されている。電子装置１０Ｂは、フェイスダウンの形態で電子装置１０Ｄ上に積層されている。電子装置１０Ｃは、例えば、量子ビット素子１３から出力される信号を読み出す制御を行う。量子ビット素子１３から出力される信号は、電子装置１０Ｄが備えるビア８１を経由して制御デバイスを構成する電子装置１０Ｃに伝送される。なお、量子ビットデバイスを構成する電子装置１０Ｂは、フェイスアップの形態で電子装置１０Ｄ上に積層されてもよい。この場合、電子装置１０Ｂには、基板１１を貫通するビアが設けられる。 Each of the plurality of electrodes 14 included in the electronic device 10B that constitutes the quantum bit device is connected to an electrode pad 84 provided on the surface of the electronic device 10D that constitutes the interposer. The electronic device 10B is stacked face down on the electronic device 10D. The electronic device 10C controls, for example, reading out the signal output from the quantum bit element 13. The signal output from the quantum bit element 13 is transmitted to the electronic device 10C forming a control device via the via 81 included in the electronic device 10D. Note that the electronic device 10B constituting the quantum bit device may be stacked on the electronic device 10D in a face-up manner. In this case, the electronic device 10B is provided with a via penetrating the substrate 11.
１０、１０Ａ、１０Ｂ、１０Ｃ、１０Ｄ　電子装置
１１、６０、８０　基板
１２、６４、８１　ビア
１２Ａ　第１の部分
１２Ｂ　第２の部分
１３　量子ビット素子
１４　電極
１５　絶縁体
３０、３０Ａ、３０Ｂ　溝
４０　絶縁体
１００、１００Ａ、１００Ｂ　電子システム 10, 10A, 10B, 10C, 10D Electronic device 11, 60, 80 Substrate 12, 64, 81 Via 12A First part 12B Second part 13 Qubit element 14 Electrode 15 Insulator 30, 30A, 30B Groove 40 Insulation Body 100, 100A, 100B Electronic system

Claims (13)

  1. 　第１の基板と、
    　前記第１の基板を貫通する、シリコン単結晶を含むビアと、
    　を有する電子装置。     a first substrate;
    a via that penetrates the first substrate and includes silicon single crystal;
    Electronic device with.
  2. 　前記第１の基板はシリコン単結晶基板であり、
    　前記ビアを構成するシリコン単結晶は、前記第１の基板を構成するシリコン単結晶と同じ結晶方位を有する
    　請求項１に記載の電子装置。     The first substrate is a silicon single crystal substrate,
    The electronic device according to claim 1, wherein the silicon single crystal forming the via has the same crystal orientation as the silicon single crystal forming the first substrate.
  3. 　前記ビアが複数設けられ、複数の前記ビアの結晶方位が互いに同じである
    　請求項１又は請求項２に記載の電子装置。     The electronic device according to claim 1 or 2, wherein a plurality of the vias are provided, and the crystal orientations of the plurality of vias are the same.
  4. 　前記ビアの周囲を囲み、前記ビアと前記第１の基板とを隔てる絶縁体を有する
    　請求項２に記載の電子装置。     The electronic device according to claim 2 , further comprising an insulator surrounding the via and separating the via and the first substrate.
  5. 　前記第１の基板が絶縁体によって構成された
    　請求項１に記載の電子装置。     The electronic device according to claim 1, wherein the first substrate is made of an insulator.
  6. 　前記第１の基板の第１の面に設けられ、前記ビアに電気的に接続された量子ビット素子を有する
    　請求項１又は２に記載の電子装置。     The electronic device according to claim 1 , further comprising a quantum bit element provided on the first surface of the first substrate and electrically connected to the via.
  7. 　前記ビアと前記量子ビット素子とを接続する配線が超伝導性を発現する金属によって構成された
    　請求項６に記載の電子装置。     The electronic device according to claim 6, wherein the wiring connecting the via and the quantum bit element is made of a metal that exhibits superconductivity.
  8. 　前記第１の基板の前記第１の面とは反対側の第２の面に接続され、前記ビアに電気的に接続された第２の基板と、
    　を含む請求項６に記載の電子装置。     a second substrate connected to a second surface of the first substrate opposite to the first surface and electrically connected to the via;
    The electronic device according to claim 6, comprising:
  9. 　シリコン基板を貫通するビアを有する電子装置の製造方法であって、
    　前記シリコン基板の、前記ビアの形成予定部位を囲む領域を、前記シリコン基板の第１の面の側からエッチングすることにより溝を形成する工程と、
    　前記溝の内部に第１の絶縁体を形成する工程と、
    　前記シリコン基板の前記第１の面の反対側の第２の面を研削して、前記第２の面に前記第１の絶縁体を露出させる工程と
    を含む電子装置の製造方法。     A method of manufacturing an electronic device having a via penetrating a silicon substrate, the method comprising:
    forming a groove by etching a region of the silicon substrate surrounding the area where the via is to be formed from a first surface side of the silicon substrate;
    forming a first insulator inside the groove;
    A method for manufacturing an electronic device, comprising: grinding a second surface of the silicon substrate opposite to the first surface to expose the first insulator on the second surface.
  10. 　シリコン基板を貫通するビアを有する電子装置の製造方法であって、
    　前記シリコン基板の、前記ビアの形成予定部位を囲む領域を、前記シリコン基板の第１の面の側からエッチングすることにより第１の溝を形成する工程と、
    　前記第１の溝の内部に第１の絶縁体を形成する工程と、
    　前記第１の溝の内部に前記第１の絶縁体を形成する工程の後に、前記シリコン基板を前記第１の面とは反対側の第２の面の側からエッチングすることにより、前記第１の溝に連通する第２の溝を形成する工程と、
    　前記第２の溝の内部に第２の絶縁体を形成する工程と
    を含む電子装置の製造方法。     A method of manufacturing an electronic device having a via penetrating a silicon substrate, the method comprising:
    forming a first groove by etching a region of the silicon substrate surrounding the area where the via is to be formed from a first surface side of the silicon substrate;
    forming a first insulator inside the first groove;
    After the step of forming the first insulator inside the first groove, the silicon substrate is etched from the second surface side opposite to the first surface. forming a second groove communicating with the groove;
    forming a second insulator inside the second groove.
  11. 　前記シリコン基板の前記ビアの形成予定部位以外の部位をエッチングすることにより前記溝を形成する
    　請求項９に記載の製造方法。     The manufacturing method according to claim 9, wherein the groove is formed by etching a portion of the silicon substrate other than a portion where the via is planned to be formed.
  12. 　前記第１の絶縁体はモールド樹脂である
    　請求項１１に記載の製造方法。     The manufacturing method according to claim 11, wherein the first insulator is a molded resin.
  13. 　前記シリコン基板の表面に前記ビアに接続された量子ビット素子を形成する工程を含む
    　請求項９又は請求項１０に記載の製造方法。     The manufacturing method according to claim 9 or claim 10, comprising the step of forming a quantum bit element connected to the via on the surface of the silicon substrate.
PCT/JP2022/017281 2022-04-07 2022-04-07 Electronic device, electronic system and method for producing electronic device WO2023195132A1 (en)

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Citations (6)

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JPS6118165A (en) * 1984-07-04 1986-01-27 Hitachi Ltd Semiconductor integrated circuit device
JPS61248471A (en) * 1985-04-26 1986-11-05 Hitachi Ltd Semiconductor device
JP2002076269A (en) * 2000-04-28 2002-03-15 Stmicroelectronics Srl Structure for electrically connecting first main body of semiconductor material with second main body thereof lapped thereon, composite structure using electrical connecting structure and method of manufacturing the same
JP2008229833A (en) * 2007-02-22 2008-10-02 Denso Corp Semiconductor device and its manufacturing method
JP2017208368A (en) * 2016-05-16 2017-11-24 新日本無線株式会社 Substrate with through electrodes
JP2021072351A (en) * 2019-10-30 2021-05-06 日本電気株式会社 Superconducting circuit device, spacer, and manufacturing method of superconducting circuit device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6118165A (en) * 1984-07-04 1986-01-27 Hitachi Ltd Semiconductor integrated circuit device
JPS61248471A (en) * 1985-04-26 1986-11-05 Hitachi Ltd Semiconductor device
JP2002076269A (en) * 2000-04-28 2002-03-15 Stmicroelectronics Srl Structure for electrically connecting first main body of semiconductor material with second main body thereof lapped thereon, composite structure using electrical connecting structure and method of manufacturing the same
JP2008229833A (en) * 2007-02-22 2008-10-02 Denso Corp Semiconductor device and its manufacturing method
JP2017208368A (en) * 2016-05-16 2017-11-24 新日本無線株式会社 Substrate with through electrodes
JP2021072351A (en) * 2019-10-30 2021-05-06 日本電気株式会社 Superconducting circuit device, spacer, and manufacturing method of superconducting circuit device

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