JP2021072351A - Superconducting circuit device, spacer, and manufacturing method of superconducting circuit device - Google Patents

Abstract

To provide a superconducting circuit device in which a distance between a quantum circuit chip and a substrate can be adjusted with extremely high accuracy.SOLUTION: A superconducting circuit device 1 has a quantum circuit chip 20, a substrate 40, and a spacer 50. In the quantum circuit chip 20, a quantum circuit 22 using a superconducting material and an electrode 24 (first electrode) are formed. An electrode 44 (second electrode) is formed on the substrate 40. The electrode 24 and the electrode 44 are connected by a bump 10. The spacer 50 is made of titanium or a titanium alloy. The spacer 50 is arranged at a predetermined position between the quantum circuit chip 20 and the substrate 40.SELECTED DRAWING: Figure 3

Description

The present invention relates to a superconducting circuit device, a spacer, and a method for manufacturing the superconducting circuit device.

A quantum computer using a superconducting element operates by being cooled to an extremely low temperature so that the superconducting materials constituting the superconducting element, such as niobium (Nb) and aluminum (Al), are in a superconducting state. .. The lower the temperature at which the superconducting quantum computer is operated, the more preferable it is. This is because the lower the temperature, the less the influence of noise, and the better the performance of the quantum computer. Specifically, the superconducting quantum computer is preferably operated at a temperature of 100 mK (millikelvin; absolute temperature) or less, and if it is 100 mK or less, the lower the temperature, the more preferable. For example, a superconducting quantum computer is operated by cooling it to an extremely low temperature of about 10 mK. In a quantum computer using a superconducting element, a quantum circuit chip in which superconducting qubits (superconducting qubits) are integrated is often connected to a substrate by flip-chip connection. Here, Patent Document 1 discloses a flip chip mounting method. In Patent Document 1, the IC chip is provided with an electrical connection member and a height regulating member provided on the electrode pad. Then, the electrical connection member provided on the IC chip is positioned and mounted on the electrode pad on the substrate, and the height of the IC chip is controlled by the height regulating member provided on the IC chip.

Japanese Unexamined Patent Publication No. 2001-15552

In a quantum computer using a superconducting element, the distance between the quantum circuit chip and the substrate is required to achieve both the performance of the superconducting quantum circuit (hereinafter, simply referred to as the quantum circuit) and the reading of the state of the quantum circuit. Needs to be adjusted with extremely high precision, which is not required for semiconductor devices. On the other hand, Patent Document 1 described above describes that the accuracy of the distance between the IC chip and the substrate can be regulated to ± 5 μm or less. However, in a quantum computer using a superconducting element, the accuracy of the distance between the quantum circuit chip and the substrate is required to be much stricter than ± 5 μm or less.

An object of the present disclosure is to solve such a problem, and superconducting circuit devices, spacers, and superconducting circuits capable of adjusting the distance between a quantum circuit chip and a substrate with extremely high accuracy. The purpose is to provide a method for manufacturing a conduction circuit device.

The superconducting circuit apparatus according to the present disclosure includes a quantum circuit chip in which a quantum circuit using a superconducting material and a first electrode are formed, a substrate on which a second electrode is formed, and a spacer. The first electrode and the second electrode are connected by bumps, and the spacer is made of titanium or a titanium alloy and is arranged at a predetermined position between the quantum circuit chip and the substrate. There is.

Further, the spacer according to the present disclosure is made of titanium or a titanium alloy and is used in a superconducting circuit device.

Further, in the method for manufacturing a superconducting circuit device according to the present disclosure, a quantum circuit chip using a superconducting material and a quantum circuit chip on which a first electrode is formed and a substrate on which a second electrode is formed face each other. Then, a spacer formed of titanium or a titanium alloy is arranged at a predetermined position on the substrate, and the spacer is arranged at a predetermined position on the substrate, and the first electrode and the said The second electrode is connected with a bump.

According to the present disclosure, it is possible to provide a superconducting circuit device, a spacer, and a method for manufacturing a superconducting circuit device capable of adjusting the distance between a quantum circuit chip and a substrate with extremely high accuracy.

It is a figure which shows the superconducting circuit apparatus which concerns on a comparative example. It is a figure which shows the method of controlling the distance between a chip and a substrate in flip chip mounting of a semiconductor circuit which concerns on Patent Document 1. FIG. It is a figure which shows the superconducting circuit apparatus which concerns on this embodiment. It is a figure which shows the 1st example of the manufacturing method of the superconducting circuit apparatus which concerns on Embodiment 1. FIG. It is a figure which shows the 2nd example of the manufacturing method of the superconducting circuit apparatus which concerns on Embodiment 1. FIG. It is a figure which shows the example of the arrangement method of the spacer with respect to the substrate in the superconducting circuit apparatus which concerns on Embodiment 1. FIG. It is a figure which shows the example of the arrangement method of the spacer with respect to the substrate in the superconducting circuit apparatus which concerns on Embodiment 1. FIG. It is a figure which shows the example of the arrangement method of the spacer with respect to the substrate in the superconducting circuit apparatus which concerns on Embodiment 1. FIG. It is a figure which shows the example of the arrangement method of the spacer with respect to the substrate in the superconducting circuit apparatus which concerns on Embodiment 1. FIG. It is a figure which shows the example of the arrangement method of the spacer with respect to the substrate in the superconducting circuit apparatus which concerns on Embodiment 1. FIG. It is a figure which shows the example of the arrangement method of the spacer with respect to the substrate in the superconducting circuit apparatus which concerns on Embodiment 1. FIG. It is a figure which shows the superconducting circuit apparatus which concerns on Embodiment 2. It is a figure which shows the example of the arrangement method of the spacer with respect to the substrate in the superconducting circuit apparatus which concerns on Embodiment 3. FIG. It is a figure which shows the example of the arrangement method of the spacer with respect to the substrate in the superconducting circuit apparatus which concerns on Embodiment 3. FIG. It is a figure which shows the example of the arrangement method of the spacer with respect to the substrate in the superconducting circuit apparatus which concerns on Embodiment 3. FIG.

(Outline of Embodiments of the present disclosure)
Prior to the description of the embodiments of the present disclosure, an outline of the embodiments according to the present disclosure will be described. FIG. 1 is a diagram showing a superconducting circuit device 1 according to a comparative example. FIG. 1 is a cross-sectional view taken from the side surface of the superconducting circuit device 1. The superconducting circuit device 1 is, for example, a quantum computer. The superconducting circuit device 1 according to the comparative example has a superconducting circuit mounting structure 2, a reading unit 3, and a control unit 4. The superconducting circuit mounting structure 2 has a quantum circuit chip 20 and a substrate 40. The quantum circuit chip 20 and the substrate 40 are connected by a flip chip connection.

The reading unit 3 and the control unit 4 are used at room temperature of about 300K (K: Kelvin). On the other hand, the superconducting circuit mounting structure 2 (quantum circuit chip 20 and substrate 40) is cooled to an extremely low temperature of about 10 mK. Specifically, the substrate 40 is in thermal contact with the cold stage (not shown). The cold stage is a stage of a refrigerator cooled to about 10 mK. As a result, the superconducting circuit mounting structure 2 can be cooled to an extremely low temperature of about 10 mK.

The quantum circuit chip 20 has a quantum circuit 22 using a superconducting material. The quantum circuit 22 is formed on the surface 20a (front surface; surface facing the substrate 40) of the quantum circuit chip 20. Further, electrodes 24 (24A, 24B), which are conductive portions, are formed on the surface 20a of the quantum circuit chip 20. The electrode 24 (first electrode) is a ground electrode of the quantum circuit chip 20.

The quantum circuit 22 is a superconducting quantum circuit in which a plurality of superconducting qubits are integrated. Each superconducting qubit is constructed using a resonator. Then, the higher the Q value of the qubit, the longer the coherence time of the qubit can be, and as a result, the quantum calculation can be executed for a longer time. Therefore, it is desirable to increase the Q value of each qubit as much as possible.

The substrate 40 is, for example, a silicon substrate. Electrodes 42 (42A, 42B) and electrodes 44 (44A, 44B), which are conductive portions, are formed on the surface 40a (front surface; surface facing the quantum circuit chip 20) of the substrate 40. The electrode 44 (second electrode) is a ground electrode of the substrate 40. Further, as will be described later, the electrodes 42A and 42B (third electrode) and the quantum circuit 22 are non-contactly coupled by the capacity coupling 12 or the inductive coupling 14.

The back surface 40b of the substrate 40 is in contact with the cold stage. Further, electrodes 46 (46A, 46B) and electrodes 48 (48A, 48B), which are conductive portions, are formed on the back surface 40b of the substrate 40. The electrodes 48A and 48B are ground electrodes of the substrate 40. The electrode 46A and the electrode 48A are electrically connected to the reading unit 3 via wiring. Further, the electrodes 46B and 48B are electrically connected to the control unit 4 via wiring. Further, a through electrode 45 (TSV; Through Silicon Via) penetrating the substrate 40 is formed between the electrode 42A and the electrode 46A and between the electrode 42B and the electrode 46B. Similarly, a through electrode 45 is formed between the electrode 44A and the electrode 48A and between the electrode 44B and the electrode 48B.

The electrode 24 formed on the surface 20a of the quantum circuit chip 20 and the electrode 44 formed on the surface 40a of the substrate 40 are connected by a bump 10. That is, the electrode 24A (first electrode) formed on the surface 20a of the quantum circuit chip 20 and the electrode 44A (second electrode) formed on the surface 40a of the substrate 40 are connected by a bump 10A. .. Similarly, the electrode 24B (first electrode) formed on the surface 20a of the quantum circuit chip 20 and the electrode 44B (second electrode) formed on the surface 40a of the substrate 40 are connected by a bump 10B. There is.

Further, the conductive portion of the quantum circuit 22 formed on the surface 20a of the quantum circuit chip 20 and the electrode 42B formed on the surface 40a of the substrate 40 face each other. Then, the quantum circuit 22 and the electrode 42B are coupled by the inductive coupling 14 via the mutual inductance existing between the quantum circuit 22 and the electrode 42B. Here, the inductive coupling is a non-contact coupling via the mutual inductance described above.

Further, another conductive portion of the quantum circuit 22 formed on the surface 20a of the quantum circuit chip 20 and the electrode 42A formed on the surface 40a of the substrate 40 face each other. Then, the quantum circuit 22 and the electrode 42A are coupled by the capacitive coupling 12 via the capacitance existing between the quantum circuit 22 and the electrode 42A. Here, the capacity coupling is a non-contact coupling via the above-mentioned capacitance.

Then, the quantum circuit 22 is controlled and read by connecting the reading unit 3 and the control unit 4 to the electrodes 46 and 48 on the back surface 40b of the substrate 40. Specifically, the control signal output from the control unit 4 passes through the through electrode 45 and reaches the electrode 42 formed on the surface 40a of the substrate 40. Then, the control signal is transmitted to the quantum circuit 22 via the inductive coupling 14. In this way, the control unit 4 controls the quantum circuit 22 on the quantum circuit chip 20 in a non-contact manner by inductive coupling. Similarly, the state of the quantum circuit 22 of the quantum circuit chip 20 is the electrode 42A and the through electrode 45 formed on the surface 40a of the substrate 40 via the non-contact capacitive coupling 12 between the quantum circuit chip 20 and the substrate 40. It is read by the reading unit 3 via and.

Here, the distance between the quantum circuit chip 20 and the substrate 40 is required to be as close to the design value as possible and uniform over the entire area of the quantum circuit chip 20 having a size of several mm square to several cm square. To. This is because the performance of the quantum circuit 22 and the strength of the capacity coupling 12 (and the inductive coupling 14) depend on the distance between the quantum circuit chip 20 and the substrate 40. Specifically, it is necessary to design the distance between the quantum circuit chip 20 and the substrate 40 to be, for example, 1 μm to 10 μm. Further, it is necessary to keep the error of the distance between the quantum circuit chip 20 and the substrate 40 within ± 20% (± 0.2 μm to ± 2 μm) over the entire area of the quantum circuit chip 20 of several mm square to several cm square. There is.

The capacitance of the capacitive coupling 12 increases as the distance between the quantum circuit chip 20 and the substrate 40 decreases. If the capacitance of the capacitive coupling 12 is too large, the Q value of the quantum circuit 22 will decrease, and the performance of the quantum circuit 22 will decrease. On the other hand, if the capacitance of the capacitive coupling 12 is reduced, the Q value becomes high and the performance of the quantum circuit 22 is improved. However, if the capacitance of the capacitive coupling 12 is too small, the capacitive coupling 12 becomes weak, and it becomes difficult for the reading unit 3 to read the state of the quantum circuit 22.

The capacitance of the capacity coupling 12 has the above-mentioned trade-off relationship. Therefore, the magnitude of the capacitance of the capacitive coupling 12, that is, the distance between the quantum circuit chip 20 and the substrate 40 has an appropriate value. In the case of a practical superconducting quantum circuit chip in which a large number of superconducting qubits are integrated, there is a strict requirement that this distance must be set to an extremely accurate and appropriate value over the entire chip of several mm square to several cm square. There is. As described above, when the quantum circuit chip 20 is mounted on the substrate 40 by the flip chip connection, it is required to control (adjust) the distance between the quantum circuit chip 20 and the substrate 40 with very high accuracy. Such strict conditions are peculiar to superconducting quantum circuits, which are not required for semiconductor circuits other than superconducting quantum circuits.

FIG. 2 is a diagram showing a method of controlling a distance between a chip and a substrate in flip-chip mounting of a semiconductor circuit 90 according to Patent Document 1. In Patent Document 1, as shown in (a), the IC chip 93 is provided with an electrical connection member 95 provided on the electrode pad 94 and a height regulating member 96 such as copper (Cu). Then, the electrical connection member 95 is positioned and mounted on the electrode pad 92 on the substrate 91. Then, as shown in (b), the height of the IC chip 93 is controlled by the height regulating member 96, the electrical connection member 95 is heat-bonded, and the electrode pad 94 of the IC chip 93 and the electrode pad 92 of the substrate 91 are joined. And connect. Since the height regulating member 96 hits the substrate 91 when the flip chip is mounted, the distance between the IC chip 93 and the substrate 91 can be regulated.

However, in the method according to Patent Document 1 as shown in FIG. 2, the accuracy of the distance between the chip and the substrate may become coarse. In Patent Document 1, it is an object to obtain an accuracy of ± 5 μm or less with respect to the distance between the IC chip 93 and the substrate 91. However, there is a problem that this method cannot be applied because the flip-chip mounting of the superconducting quantum circuit requires higher accuracy than this accuracy. Solving this problem and realizing a highly accurate flip-chip mounting method has become an indispensable issue for the practical application of superconducting quantum circuits.

FIG. 3 is a diagram showing a superconducting circuit device 1 according to the present embodiment. FIG. 3 is a cross-sectional view seen from the side surface of the superconducting circuit device 1. In FIG. 3, the reading unit 3 and the control unit 4 are omitted (the same applies to the following figures). The superconducting circuit device 1 according to the present embodiment has substantially the same configuration as the superconducting circuit device 1 shown in FIG. That is, the superconducting circuit device 1 according to the present embodiment has a quantum circuit chip 20 and a substrate 40. The quantum circuit chip 20 is formed with a quantum circuit 22 using a superconducting material and an electrode 24 (first electrode). An electrode 44 (second electrode) is formed on the substrate 40. The electrode 24 and the electrode 44 are connected by a bump 10.

Further, the superconducting circuit device 1 according to the present embodiment has a spacer 50. The spacer 50 is made of titanium (Ti) or a titanium alloy. Further, the spacer 50 is arranged at a predetermined position between the quantum circuit chip 20 and the substrate 40 in a state of being in contact with the quantum circuit chip 20 and the substrate 40. Since the superconducting circuit device 1 according to the present embodiment is configured in this way, it is possible to adjust the distance between the quantum circuit chip 20 and the substrate 40 with extremely high accuracy, as will be described later. .. Therefore, the superconducting circuit device 1 according to the present embodiment can achieve both the performance of the quantum circuit 22 and the ease of reading the state of the quantum circuit 22. Therefore, the superconducting circuit device 1 according to the present embodiment can improve the performance of the device as a whole.

In addition, the method for manufacturing the superconducting circuit device 1 according to the present embodiment includes the following processing. That is, the quantum circuit chip 20 in which the quantum circuit 22 and the electrode 24 are formed and the substrate 40 in which the electrode 44 is formed are opposed to each other. Further, a spacer 50 made of titanium or a titanium alloy is arranged at a predetermined position on the substrate 40. Then, the electrode 24 and the electrode 44 are connected by bumps in a state where the spacer 50 is arranged at a predetermined position on the substrate 40. This makes it possible to adjust the distance between the quantum circuit chip 20 and the substrate 40 with extremely high accuracy. The order of the process of facing the quantum circuit chip 20 and the substrate 40 and the process of arranging the spacer 50 on the substrate 40 does not matter (the same applies to the description shown below).

(Embodiment 1)
Hereinafter, embodiments will be described with reference to the drawings. In order to clarify the explanation, the following description and drawings have been omitted or simplified as appropriate. Further, in each drawing, the same elements are designated by the same reference numerals, and duplicate explanations are omitted as necessary.

First, the first embodiment will be described. The configuration of the superconducting circuit device 1 according to the first embodiment is substantially the same as that shown in FIG. That is, the superconducting circuit device 1 according to the first embodiment is formed of a quantum circuit chip 20 in which a quantum circuit 22 and an electrode 24 are formed, a substrate 40 in which an electrode 44 is formed, and titanium or a titanium alloy. It has a spacer 50 and. Hereinafter, the method of manufacturing the superconducting circuit device 1 according to the first embodiment will be described with reference to FIGS. 4 and 5, but the method of manufacturing the superconducting circuit device 1 according to the first embodiment is shown in FIG. And not limited to those shown in FIG.

FIG. 4 is a diagram showing a first example of the method for manufacturing the superconducting circuit device 1 according to the first embodiment. As shown in (a), the quantum circuit chip 20 in which the quantum circuit 22 and the electrode 24 are formed and the substrate 40 in which the electrode 44 is formed are opposed to each other. At this time, the bump 10 is attached to the electrode 24. Further, the spacer 50A is arranged at a position corresponding to the alignment mark 60A (positioning member 60) formed on the substrate 40. Specifically, when a conveying machine such as an industrial robot conveys the spacer 50A, the spacer 50 may be arranged with the alignment mark 60A as a target. As a result, the spacer 50A is arranged at a predetermined position on the substrate 40.

Then, as shown in (b), the quantum circuit chip 20 and the substrate 40 are connected by bumps 10 in a state where the spacer 50A is arranged at a predetermined position on the substrate 40 (flip chip connection). Specifically, the bump 10 attached to the electrode 24 of the quantum circuit chip 20 is pressed against the electrode 44 on the substrate 40, so that the electrode 24 and the electrode 44 are connected by the bump 10. As a result, the spacer 50A is sandwiched between the quantum circuit chip 20 and the substrate 40, and the quantum circuit chip 20 comes into contact with the spacer 50. That is, the spacer 50A is in contact with the quantum circuit chip 20 and the substrate 40.

Here, since the spacer 50A (50) is made of titanium or a titanium alloy, the plate thickness of the spacer 50A (50) is set to a value corresponding to the design value of the distance between the quantum circuit chip 20 and the substrate 40. In addition, it can be processed with high accuracy. Therefore, the distance (distance) between the quantum circuit chip 20 and the substrate 40 can be set to a value extremely close to the design value over the entire area of the quantum circuit chip 20. As a result, as described above, the capacity coupling 12 and the inductive coupling 14 are formed between the quantum circuit 22 and the electrode 42.

FIG. 5 is a diagram showing a second example of the manufacturing method of the superconducting circuit device 1 according to the first embodiment. As shown in (a), the quantum circuit chip 20 in which the quantum circuit 22 and the electrode 24 are formed and the substrate 40 in which the electrode 44 is formed are opposed to each other. At this time, the bump 10 is attached to the electrode 24. Further, the spacer 50A is arranged at a position corresponding to the positioning convex portion 60B (positioning member 60) formed on the substrate 40. Specifically, when a conveying machine such as an industrial robot conveys the spacer 50A, the spacer 50 may be arranged so that the side surface of the spacer 50 is in contact with the positioning convex portion 60B. As a result, the spacer 50A is arranged at a predetermined position on the substrate 40.

After that, as shown in (b), the quantum circuit chip 20 and the substrate 40 are connected by the bump 10 in a state where the spacer 50A is arranged at a predetermined position on the substrate 40 in the same manner as in FIG. (Flip chip connection). As a result, the spacer 50A is sandwiched between the quantum circuit chip 20 and the substrate 40, and the quantum circuit chip 20 comes into contact with the spacer 50. Therefore, as described above, the distance (interval) between the quantum circuit chip 20 and the substrate 40 can be set to a value extremely close to the design value over the entire area of the quantum circuit chip 20. As a result, as described above, the capacity coupling 12 and the inductive coupling 14 are formed between the quantum circuit 22 and the electrode 42.

The positioning convex portion 60B may be formed of, for example, silicon oxide (SiO ₂ ) or copper (Cu). When the positioning convex portion 60B is _{formed of SiO 2} , first, a SiO ₂ film is formed on the substrate 40 by sputtering. Then, the SiO ₂ film is patterned by photolithography and etched to form a convex portion 60B for positioning _{the SiO 2} having a desired shape at a desired position on the substrate 40. When the positioning convex portion 60B is formed of Cu, a resist is applied onto the substrate 40, patterning is performed by photolithography, and copper is formed by plating. Finally, by removing the resist, a Cu positioning convex portion 60B having a desired shape can be formed at a desired position on the substrate 40.

Further, as for the method of arranging the spacer 50A, for example, the following method may be used. For example, using vacuum tweezers, the spacer 50A can be placed at a predetermined position on the substrate 40. In this case, the spacer 50A is placed at a predetermined position on the substrate 40 with the spacer 50A adsorbed by the vacuum tweezers. Then, by releasing the vacuum and separating the spacer 50A from the vacuum tweezers, the spacer 50A can be arranged at a predetermined position on the substrate 40. In addition, instead of using vacuum tweezers, a method of pinching the spacer 50A with simple tweezers and placing it at a predetermined position on the substrate 40 may be used.

Further, the spacer 50A can be arranged at a predetermined position on the substrate 40 by using a release film (release sheet). In this case, with the release film attached to the back surface of the spacer 50A, the spacer 50A is placed at a predetermined position on the substrate 40 together with the release film, and then the release film is peeled off from the spacer 50A to form the substrate 40. The spacer 50A can be arranged at a predetermined position on the top. By attaching the release film to the spacer 50A, the shape of the spacer 50A is not easily deformed (not destroyed), so that the spacer 50A is placed at a predetermined position on the substrate 40 while maintaining the shape of the spacer 50A. It will be easy to put. Further, in order to peel off the release film so as not to move the spacer 50A after placing the spacer 50A in a predetermined position, for example, the release film is kept in a state of two parts cut to the left and right at the center. Can be considered. In this case, after placing the spacer 50A in a predetermined position, first, the release film on the right half of the spacer 50A with the release film is peeled off while holding an arbitrary place on the left half with tweezers or the like. After that, the release film on the left half is peeled off while holding an arbitrary place on the right half of the spacer 50A after the release film is peeled off with tweezers or the like.

The material of the electrodes 42, 44, 46, 48 formed on the substrate 40 may be any conductive material. However, considering that the quantum circuit 22 using the superconducting material is mounted, the electrodes 42, 44, 46, 48 include a superconducting material such as Nb (niobium) or Al (aluminum). Is preferable.

Further, the material of the bump 10 is also arbitrary as long as it has conductivity. However, considering that the quantum circuit 22 using the superconducting material is mounted, the bump 10 preferably contains a superconducting material such as In (indium) or Sn (tin). The thickness of the electrodes formed on the substrate 40 or the quantum circuit chip 20 is about 50 nm to 300 nm. The thickness of the substrate 40 and the quantum circuit chip 20 is about 200 μm to 600 μm.

Next, the features (required specifications) of the spacer 50A according to the first embodiment will be described. First, as a design condition, the spacer 50A is required to have a thickness of 1 μm or more and 10 μm or less, and a thickness error of ± 20% or less over the entire width of the quantum circuit chip 20 of several mm square to several cm square. Will be done. As described above, in order to improve the operation of the superconducting circuit device 1, an error in the distance between the quantum circuit chip 20 and the substrate 40 is set over the entire area of the quantum circuit chip 20 of several mm square to several cm square. It must be within ± 20% (± 0.2 μm to ± 2 μm). In order to meet this requirement, the above design conditions are indispensable.

Next, the melting point of the spacer 50A is required to be higher than the melting point of the material of the bump 10. This is to prevent the spacer 50A from melting when the flip chip is connected. Further, the spacer 50A is required to be harder than the material of the bump 10. This is to prevent the spacer 50A from being deformed in the thickness direction when the flip chip is connected. Further, the spacer 50A is required to be non-magnetic. This condition is an indispensable condition for the quantum circuit 22 to operate normally.

Further, even if the spacer 50A has a very thin plate shape having a thickness of about 1 μm and a width of about several mm square to several cm square, it can be handled so as not to be bent when placed on the substrate 40. Is required.
Titanium or a titanium alloy (titanium material) is suitable as a material satisfying the above conditions. Therefore, in the present embodiment, titanium or a titanium alloy is adopted as the spacer 50.

As the titanium alloy, for example, an Nb—Ti alloy can be considered, but the composition is arbitrary as long as it is a titanium alloy that satisfies the conditions described later. Further, the spacer 50A can be formed by rolling a titanium material, processing it into a foil having a thickness of several μm, and cutting it into a predetermined size by laser processing. The laser machining can realize that the thickness variation due to burrs generated by cutting does not affect the above-mentioned thickness error (accuracy) (the thickness variation is within an allowable range). Further, as described above, in the present embodiment, since the spacer 50A and the substrate 40 are manufactured and processed separately, the accuracy of the height from the substrate 40 to the upper surface of the spacer 50 can be made extremely high. Examples of the processing method of the spacer 50A include a method of cutting with pressure of water, air, gas, etc., etching using chemicals, cutting, and molding processing using a die, in addition to laser processing.

The spacer 50A according to the first embodiment is required not to become superconducting at the temperature at which the quantum circuit 22 is operated, that is, to be in a normal conducting state. Here, the temperature at which the quantum circuit 22 is operated is preferably 100 mK or less, and if it is 100 mK or less, the lower the temperature, the more preferable. For example, the quantum circuit 22 is operated by cooling to an extremely low temperature of about 10 mK. This is to function as a heat path between the substrate 40 and the quantum circuit chip 20 in order to efficiently cool the quantum circuit chip 20. The details will be described below.

As described above, the substrate 40 is cooled by the cold stage. In this case, the quantum circuit chip 20 is in thermal contact with the cold stage only through the substrate 40 and the bump 10. In other words, the quantum circuit chip 20 is deprived of heat by the cold stage only through the substrate 40 and the bump 10. This is because there is a vacuum around the quantum circuit chip 20 and the substrate 40, and the vacuum basically does not function as a heat conduction path. Here, it is common to use a superconducting material such as In (indium) for the bump 10. The bump 10 (superconducting bump) using the superconducting material hardly conducts heat. Therefore, as a result, the heat conduction path between the cold stage and the quantum circuit chip 20 becomes very weak. Therefore, there is a problem that the cooling of the quantum circuit chip 20 becomes inefficient.

On the other hand, the spacer 50A according to the first embodiment is made of a titanium material that does not become superconducting (in a normal conduction state) at the temperature at which the quantum circuit 22 is operated. Since such a material has a very high thermal conductivity as compared with the superconducting bump even at the temperature at which the quantum circuit 22 is operated, a strong heat conduction path can be formed between the substrate 40 and the quantum circuit chip 20. Therefore, as a result, there is an effect that the quantum circuit chip 20 can be efficiently cooled.

It is known that titanium is in a superconducting state at an extremely low temperature such as 100 mK or less, which causes the quantum circuit 22 to operate, when a sample having extremely high purity and high crystallinity can be prepared. On the other hand, when titanium is molded into the shape of a spacer, the superconducting transition temperature becomes extremely low due to factors such as a decrease in crystallinity due to the molding process, and as a result, an extremely low temperature such that the quantum circuit 22 is operated, for example. At extremely low temperatures such as 100 mK or less, the superconducting state may not be achieved. In the first embodiment, heat conduction between the substrate 40 and the quantum circuit chip 20 is performed by intentionally using a spacer 50A made of a titanium material that does not become a superconducting state (normal conduction state) at the temperature at which the quantum circuit 22 is operated. The path can be realized.

6 to 11 are views showing an example of a method of arranging the spacer 50A with respect to the substrate 40 in the superconducting circuit device 1 according to the first embodiment. 6 to 11 are plan views of the superconducting circuit device 1 as viewed from above (upward in FIG. 3). However, for the sake of explanation, the quantum circuit chip 20 is shown to be transparent in FIGS. 6 to 11. Further, in FIGS. 6 to 11, the cold stage and the positioning member 60 are not shown.

FIG. 6 is a diagram showing a first example of a method of arranging the spacer 50A with respect to the substrate 40 in the superconducting circuit device 1 according to the first embodiment. In the first example, the quantum circuit 22 is arranged in the region 20c near the center of the quantum circuit chip 20, and the spacer 50A is arranged around the region 20c. That is, in the first example, the spacer 50A is arranged around the region where the quantum circuit 22 is arranged.

Normally, since the quantum circuit 22 is often arranged near the center of the quantum circuit chip 20, there is often an empty space near the outer periphery (peripheral end) of the quantum circuit chip 20. Therefore, as in the first example shown in FIG. 6, by arranging the spacer 50A in the vicinity of the outer periphery which is an empty space, the empty space can be effectively used.

Further, in the first example, the spacer 50A is arranged near the outer periphery of the quantum circuit chip 20. As a result, bending of the outer peripheral side of the quantum circuit chip 20 is suppressed. Therefore, the accuracy of the distance between the quantum circuit chip 20 and the substrate 40 can be improved over the entire area of the quantum circuit chip 20 (the same applies to other examples described later).

FIG. 7 is a diagram showing a second example of a method of arranging the spacer 50A with respect to the substrate 40 in the superconducting circuit device 1 according to the first embodiment. Similar to the first example, in the second example, the quantum circuit 22 is arranged in the region 20c near the center of the quantum circuit chip 20, and the spacer 50A-1 is arranged around the region 20c. However, a region in which the quantum circuit 22 is not arranged is provided in the substantially center of the region 20c, and the spacer 50A-2 is arranged in that region.

That is, in the second example, the spacer 50A-1 is arranged in a region (first region) around the region in which the quantum circuit 22 is arranged. Further, in the second example, the spacer 50A-2 is arranged in a region (second region) sandwiched between the regions in which the quantum circuit 22 is arranged. In other words, the spacer 50A-2 is arranged in a region (second region) surrounded by at least a part of the region in which the quantum circuit 22 is arranged.

By arranging the spacer 50A-2 near the center of the quantum circuit chip 20 in this way, bending of the quantum circuit chip 20 near the center can be suppressed. That is, in the first example, since the vicinity of the center of the quantum circuit chip 20 is not supported, the vicinity of the center of the quantum circuit chip 20 may be bent. On the other hand, by arranging the spacer 50A-2 near the center of the quantum circuit chip 20 as in the second example, bending near the center of the quantum circuit chip 20 can be suppressed. Therefore, the accuracy of the distance between the quantum circuit chip 20 and the substrate 40 described above can be further improved as compared with the first example.

FIG. 8 is a diagram showing a third example of a method of arranging the spacer 50A with respect to the substrate 40 in the superconducting circuit device 1 according to the first embodiment. In the third example, the spacer 50A is a spacer 50A-1 arranged around the region where the quantum circuit 22 is arranged, and a spacer 50A- arranged in the region sandwiched between the region where the quantum circuit 22 is arranged. 3 is integrally configured.

Specifically, as in the first example, the spacer 50A-1 is arranged near the outer circumference of the quantum circuit chip 20. Further, in the third example, the quantum circuit 22 is divided into a region 20cA and a region 20cB in the vicinity of the center of the quantum circuit chip 20. Then, a rod-shaped spacer 50A-3 is arranged between the region 20cA and the region 20cB.

That is, the spacer 50A-1 is arranged in a region (first region) around the region (regions 20cA, 20cB) in which the quantum circuit 22 is arranged. Further, the spacer 50A-3 is arranged in a region (second region) sandwiched between regions (regions 20cA and 20cB) in which the quantum circuit 22 is arranged. In other words, the spacer 50A-3 is arranged in a region (second region) surrounded by at least a part of the region in which the quantum circuit 22 is arranged.

In this way, by arranging the spacer 50A-3 near the center of the quantum circuit chip 20 as in the third example, the deflection of the quantum circuit chip 20 can be suppressed as in the second example. Therefore, the accuracy of the distance between the quantum circuit chip 20 and the substrate 40 described above can be further improved as compared with the first example. Further, in the third example, since the spacer 50A-1 and the spacer 50A-3 are integrated, the spacer 50A can be easily arranged on the substrate 40 as compared with the second example.

In the example of FIG. 8, the shape of the region (regions 20cA, 20cB) where the quantum circuit 22 is arranged is rectangular, but the configuration is not limited to this. Spacers 50A-3 may be provided diagonally to spacers 50A-1. In this case, the shape of the region (regions 20cA, 20cB) where the quantum circuit 22 is arranged is triangular. This also applies to the example of FIG. 9 described later.

FIG. 9 is a diagram showing a fourth example of a method of arranging the spacer 50A with respect to the substrate 40 in the superconducting circuit device 1 according to the first embodiment. In the fourth example, the spacer 50A is arranged in a region sandwiched between two spacers 50A-4 arranged in a part around the region in which the quantum circuit 22 is arranged and the region in which the quantum circuit 22 is arranged. It is composed of the spacer 50A-3.

Specifically, as in the third example, in the fourth example, the quantum circuit 22 is divided into a region 20cA and a region 20cB in the vicinity of the center of the quantum circuit chip 20. Then, a rod-shaped spacer 50A-3 is arranged between the region 20cA and the region 20cB. Further, the two spacers 50A-4 are arranged on opposite sides of the quantum circuit chip 20, respectively. In the fourth example, the spacer 50A-4 is arranged so as to completely cover one side of the arranged quantum circuit chip 20.

The spacer 50A-4 is arranged in a region (first region) around the region (regions 20cA, 20cB) in which the quantum circuit 22 is arranged. Further, the spacer 50A-3 is arranged in a region (second region) sandwiched between regions (regions 20cA and 20cB) in which the quantum circuit 22 is arranged. In other words, the spacer 50A-3 is arranged in a region (second region) surrounded by at least a part of the region in which the quantum circuit 22 is arranged.

By arranging the two spacers 50A-4 on the opposite sides of the quantum circuit chip 20 in this way, the outer peripheral side of the quantum circuit chip 20 is suppressed from bending. Further, by arranging the spacer 50A-3 near the center of the quantum circuit chip 20, it is possible to suppress the deflection of the quantum circuit chip 20 near the center as in the second example. Therefore, the accuracy of the distance between the quantum circuit chip 20 and the substrate 40 described above can be further improved as compared with the first example.

In FIG. 9, the spacer 50A-3 and the spacer 50A-4 are arranged separately. However, among the sides of the quantum circuit chip 20, the spacer 50A-4 may be arranged on the sides (two sides in the vertical direction of FIG. 9) near both ends of the rod-shaped spacer 50A-3. By doing so, the spacer 50A-3 and the spacer 50A-4 can be integrated (in an H shape). In this case, the spacer 50A can be easily arranged on the substrate 40 as in the third example.

FIG. 10 is a diagram showing a fifth example of a method of arranging the spacer 50A with respect to the substrate 40 in the superconducting circuit device 1 according to the first embodiment. In the fifth example, the spacer 50A is a spacer 50A-1 arranged around the region where the quantum circuit 22 is arranged, and a spacer 50A- arranged in the region sandwiched between the region where the quantum circuit 22 is arranged. 5 is integrally configured.

Specifically, as in the first example, in the fifth example, the spacer 50A-1 is arranged near the outer periphery of the quantum circuit chip 20. Further, in the fifth example, the quantum circuit 22 is divided into a region 20cC, a region 20cD, a region 20cE, and a region 20cF near the center of the quantum circuit chip 20. Then, between these four regions 20c, spacers 50A-5 having a shape (X-shape) in which two rods intersect are arranged.

That is, the spacer 50A-1 is arranged in a region (first region) around the region (regions 20cC, 20cD, 20cE, 20cF) in which the quantum circuit 22 is arranged. Further, the spacer 50A-5 is arranged in a region (second region) sandwiched between regions (regions 20cC, 20cD, 20cE, 20cF) in which the quantum circuit 22 is arranged. In other words, the spacer 50A-5 is arranged in a region (second region) surrounded by at least a part of the region in which the quantum circuit 22 is arranged. In FIG. 10, the spacer 50A-5 has a shape in which two diagonal rods intersect, but the spacer 50A-5 has a shape in which the vertical horizontal and horizontal rods intersect. Good.

In this way, by arranging the spacer 50A-5 near the center of the quantum circuit chip 20 as in the fifth example, it is possible to suppress the deflection of the quantum circuit chip 20 near the center as in the second example. Therefore, the accuracy of the distance between the quantum circuit chip 20 and the substrate 40 described above can be further improved as compared with the first example. Further, in the fifth example, since the spacer 50A-1 and the spacer 50A-3 are integrated, the spacer 50A can be easily arranged on the substrate 40 as compared with the second example and the like. ..

Further, the area of the spacer 50A-5 in FIG. 10 is larger than the area of the spacer 50A-3 in FIG. Therefore, in the fifth example, the area of the spacer 50A that supports the quantum circuit chip 20 is larger in the vicinity of the center of the quantum circuit chip 20 than in the third example. Therefore, the deflection of the entire quantum circuit chip 20 can be further suppressed.

FIG. 11 is a diagram showing a sixth example of a method of arranging the spacer 50A with respect to the substrate 40 in the superconducting circuit device 1 according to the first embodiment. In the sixth example, the spacer 50A is a spacer arranged in a region sandwiched between four spacers 50A-6 arranged around the region where the quantum circuit 22 is arranged and the region where the quantum circuit 22 is arranged. 50A-5 and 50A-5 are integrally configured.

Specifically, the four spacers 50A-6 are arranged near the four corners of the quantum circuit chip 20. Further, similarly to the fifth example, in the sixth example, the quantum circuit 22 is divided into a region 20cC, a region 20cD, a region 20cE, and a region 20cF in the vicinity of the center of the quantum circuit chip 20. ing. Then, between these four regions 20c, spacers 50A-5 having a shape in which two rods intersect are arranged.

That is, the spacer 50A-6 is arranged in a region (first region) around the region (regions 20cC, 20cD, 20cE, 20cF) in which the quantum circuit 22 is arranged. Further, the spacer 50A-5 is arranged in a region (second region) sandwiched between regions (regions 20cC, 20cD, 20cE, 20cF) in which the quantum circuit 22 is arranged. In other words, the spacer 50A-5 is arranged in a region (second region) surrounded by at least a part of the region in which the quantum circuit 22 is arranged.

By arranging the four spacers 50A-6 in the vicinity of the four corners of the quantum circuit chip 20 as in the sixth example, it is possible to prevent the corners of the quantum circuit chip 20 from bending. Further, by arranging the spacer 50A-5 near the center of the quantum circuit chip 20 as in the sixth example, it is possible to suppress the deflection of the quantum circuit chip 20 near the center as in the second example. Therefore, the accuracy of the distance between the quantum circuit chip 20 and the substrate 40 described above can be further improved as compared with the first example. Further, in the sixth example, since the four spacers 50A-6 and the spacers 50A-3 are integrated, the spacers 50A can be easily arranged on the substrate 40 as compared with the second example and the like. Can be done.

In the examples shown in FIGS. 6 to 11, a spacer 50A made of titanium material, which is in a normal conduction state at a temperature at which the quantum circuit 22 is operated, can be used. Therefore, the heat conduction path between the substrate 40 and the quantum circuit chip 20 can be effectively realized. In particular, as in the fifth example shown in FIG. 10, the larger the area of the spacer 50A in contact with the substrate 40, the higher the cooling effect due to the heat conduction path can be.

Further, the spacer 50A is arranged so as not to come into contact with the region 20c in which the quantum circuit 22 of the quantum circuit chip 20 is arranged. If the spacer 50A comes into contact with the quantum circuit 22, the spacer 50A may be present in the middle of the inductive coupling 14 or the capacitive coupling 12. In this case, the inductive bond 14 or the capacity bond 12 may not be able to function effectively. On the other hand, in the present embodiment, since the spacer 50A is arranged so as not to come into contact with the region 20c in which the quantum circuit 22 of the quantum circuit chip 20 is arranged, the function of the inductive coupling 14 or the capacity coupling 12 is deteriorated. It can be suppressed.

However, in order to prevent the quantum circuit chip 20 from bending in the vicinity of the quantum circuit 22, the spacer 50A is preferably arranged as close as possible to the region 20c in which the quantum circuit 22 is arranged. That is, the shortest distance between the region 20c in which the quantum circuit 22 is arranged and the spacer 50A should be as short as possible.

As described above, in the present embodiment, the spacer 50 made of the titanium material (titanium or titanium alloy) is arranged at a predetermined position between the quantum circuit chip 20 and the substrate 40. This makes it possible to adjust the distance between the quantum circuit chip 20 and the substrate 40 with extremely high accuracy. Therefore, the superconducting circuit device 1 according to the present embodiment can improve the performance of the device as a whole, as described above.

Further, in the present embodiment, the spacer 50 may be arranged in a region around the region 20c in which the quantum circuit 22 is arranged. As a result, as described above, bending of the vicinity of the outer circumference of the quantum circuit chip 20 is suppressed. Therefore, the distance between the quantum circuit chip 20 and the substrate 40 can be adjusted with extremely high accuracy over the entire area of the quantum circuit chip 20. Further, the spacer 50 may be arranged in a region sandwiched between the regions 20c in which the quantum circuit 22 is arranged. As a result, the quantum circuit chip 20 is prevented from bending near the center of the quantum circuit chip 20 in which the quantum circuit 22 is arranged. Therefore, the distance between the quantum circuit chip 20 and the substrate 40 can be adjusted more accurately over the entire area of the quantum circuit chip 20. Further, the spacer 50A is a region (second region) sandwiched between a portion arranged in a region (first region) around the region in which the quantum circuit 22 is arranged and a region in which the quantum circuit 22 is arranged. The portions arranged in the can be formed so as to be integrated with each other. Thereby, the spacer 50A can be easily arranged on the substrate 40.

Further, in the first embodiment, the spacer 50A is made of a titanium material which is in a normal conduction state at a temperature at which the quantum circuit 22 is operated. Therefore, as described above, the heat conduction path between the substrate 40 and the quantum circuit chip 20 can be effectively realized. Therefore, the quantum circuit chip 20 can be cooled efficiently.

In the method shown in FIG. 2, a height regulating member 96 made of copper is formed on the IC chip 93. In this method, in order to form the height regulating member 96, copper is laminated by plating on a wafer on which a large number of IC chips 93 are formed, and then flattened by CMP (Chemical Mechanical Polishing) to form a height. It is necessary to form the regulating member 96, and then cut the wafer to separate it into individual chips. In that case, it is inevitable that the flatness of the wafer after being flattened by CMP will be uneven, so that the height of the height regulating member 96 will differ depending on the position of the wafer. Therefore, there is a problem that it is difficult to accurately manufacture the height regulating member 96 at the height as designed. In addition, this method requires a plating device, a polishing device, and the like, which may complicate the work process and increase the cost.

On the other hand, the spacer 50 according to the present embodiment is manufactured separately from the quantum circuit chip 20. Therefore, it is only necessary to place the spacer 50 on the substrate 40 after the quantum circuit chip 20 is fragmented. Therefore, in the present embodiment, since the plating device and the polishing device are not required, the work process can be simplified and the cost can be reduced as compared with the example of FIG. Further, the spacer 50 can be molded with extremely high accuracy. Further, the spacer 50 may be manufactured separately from the substrate 40. Therefore, by placing the spacer 50 after performing the surface treatment of the substrate 40 with high accuracy, the accuracy of the height from the substrate 40 to the upper surface of the spacer 50 can be made extremely high.

(Embodiment 2)
Next, the second embodiment will be described. In order to clarify the explanation, the following description and drawings have been omitted or simplified as appropriate. Further, in each drawing, the same elements are designated by the same reference numerals, and duplicate explanations are omitted as necessary. The second embodiment is different from the first embodiment in that the characteristics of the spacer 50 are different from those of the first embodiment.

FIG. 12 is a diagram showing a superconducting circuit device 1 according to the second embodiment. The configuration of the superconducting circuit device 1 according to the second embodiment is substantially the same as that shown in FIG. 3, except for the characteristics of the spacer 50 described later. That is, the superconducting circuit device 1 according to the second embodiment is formed of a quantum circuit chip 20 in which the quantum circuit 22 and the electrode 24 are formed, a substrate 40 in which the electrode 44 is formed, and titanium or a titanium alloy. It has a spacer 50 and. Further, the method for manufacturing the superconducting circuit device 1 according to the second embodiment may be the method shown in FIGS. 4 and 5.

Therefore, also in the second embodiment, it is possible to adjust the distance between the quantum circuit chip 20 and the substrate 40 with extremely high accuracy as described above. Therefore, the superconducting circuit device 1 according to the second embodiment can improve the performance of the device as a whole as in the first embodiment.

Here, the spacer 50B according to the second embodiment is made of a titanium material that is in a superconducting state at a temperature at which the quantum circuit 22 is operated, unlike the spacer 50A according to the first embodiment. That is, the spacer 50B according to the second embodiment is in a superconducting state at the temperature at which the quantum circuit 22 is operated. This is because the spacer 50B also functions as a magnetic shield. The details will be described below. As described above, titanium is superconducting at an extremely low temperature such that the quantum circuit 22 is operated, for example, an extremely low temperature such as 100 mK or less, when a sample having extremely high purity and high crystallinity can be prepared. It is in a state. Therefore, the spacer 50B according to the second embodiment can be formed of a titanium material (titanium and a titanium alloy) having high purity and good crystallinity.

In general, superconducting quantum circuits are very sensitive to magnetism, and even the presence of very weak magnetism, such as geomagnetism, may react sensitively and cause malfunctions. In addition to geomagnetism, various magnetic noises may exist in the environment in which the superconducting quantum circuit is operated. Therefore, it is desirable to shield the superconducting quantum circuit from such weak magnetic noise.

In the second embodiment, the function of this magnetic shield is realized by using a superconducting material for the spacer 50B. The superconducting material can function as a very high-performance magnetic shield due to the unique property of superconductivity, which is the complete antimagnetism due to the Meissner effect. Therefore, as shown in FIG. 12, the spacer 50B can shield the quantum circuit 22 from the very weak magnetic noise as shown by the arrow A. Therefore, the superconducting circuit device 1 according to the second embodiment can reduce the probability that the quantum circuit 22 will malfunction.

As the method of arranging the spacer 50B with respect to the substrate 40, those illustrated in FIGS. 6 to 11 can be adopted. In particular, as illustrated in FIGS. 6 to 8 and 10, by arranging the spacer 50B in the entire area near the outer circumference of the quantum circuit chip 20, the quantum circuit 22 can be shielded from magnetic noise invading from the outer circumference. it can. In other words, the spacer 50B can suppress the influence of magnetic noise on the quantum circuit 22.

Even with the arrangement method illustrated in FIG. 9, the spacer 50B may suppress the influence of geomagnetism (magnetic noise) on the quantum circuit 22. Geomagnetism works strongly in the north-south direction of the earth. Therefore, by arranging the spacers 50B at the positions of the two spacers 50A-4 in FIG. 9, and arranging the superconducting circuit device 1 so that the two spacers 50B are arranged on the north side and the south side of the quantum circuit 22, respectively. The influence of geomagnetism (magnetic noise) on the quantum circuit 22 can be suppressed. In other words, the superconducting circuit device 1 is placed so that the upper part of FIG. 9 is in the north direction or the south direction, and the longitudinal directions of the two spacers 50B are arranged along the east-west direction. The influence of geomagnetism (magnetic noise) on the ground can be suppressed. By keeping the distance from the vertical side of the quantum circuit chip 20 to the quantum circuit 22 (region 20cA) as much as possible, the influence of geomagnetism (magnetic noise) on the quantum circuit 22 can be further suppressed.

(Embodiment 3)
Next, the third embodiment will be described. In order to clarify the explanation, the following description and drawings have been omitted or simplified as appropriate. Further, in each drawing, the same elements are designated by the same reference numerals, and duplicate explanations are omitted as necessary. The third embodiment is different from other embodiments in that spacers 50 having different characteristics are arranged on the same substrate 40 (superconducting circuit device 1).

13 to 15 are views showing an example of a method of arranging the spacer 50 with respect to the substrate 40 in the superconducting circuit device 1 according to the third embodiment. 13 to 15 are plan views of the superconducting circuit device 1 as viewed from above (upward in FIG. 3). However, for the sake of explanation, the quantum circuit chip 20 is shown to be transparent in FIGS. 13 to 15. Further, in FIGS. 13 to 15, the positioning member 60 is not shown.

FIG. 13 is a diagram showing a first example of a method of arranging the spacer 50 with respect to the substrate 40 in the superconducting circuit device 1 according to the third embodiment. The arrangement method shown in FIG. 13 corresponds to the arrangement method shown in FIG. 7. Here, in the example shown in FIG. 13, the quantum circuit 22 is arranged in the region 20c near the center of the quantum circuit chip 20, and the spacer 50B is arranged around the region 20c. A region in which the quantum circuit 22 is not arranged is provided in the substantially center of the region 20c, and the spacer 50A is arranged in that region.

That is, in the example shown in FIG. 13, the spacer 50B, which is in a superconducting state at the temperature at which the quantum circuit 22 is operated, is arranged in a region (first region) around the region in which the quantum circuit 22 is arranged. There is. Further, the spacer 50A, which is in a normal conduction state at the temperature at which the quantum circuit 22 is operated, is arranged in a region (second region) sandwiched between the regions in which the quantum circuit 22 is arranged. In other words, the spacer 50A is arranged in a region (second region) surrounded by at least a part of the region in which the quantum circuit 22 is arranged.

FIG. 14 is a diagram showing a second example of a method of arranging the spacer 50 with respect to the substrate 40 in the superconducting circuit device 1 according to the third embodiment. The arrangement method shown in FIG. 14 corresponds to the arrangement method shown in FIG. Here, in the example shown in FIG. 14, the spacer 50B is arranged around the region where the quantum circuit 22 is arranged. Further, the quantum circuit 22 is divided into a region 20cA and a region 20cB in the vicinity of the center of the quantum circuit chip 20. A rod-shaped spacer 50A is arranged between the region 20cA and the region 20cB.

That is, in the example shown in FIG. 14, the spacer 50B, which is in a superconducting state at the temperature at which the quantum circuit 22 is operated, is arranged in a region (first region) around the region in which the quantum circuit 22 is arranged. There is. Further, the spacer 50A, which is in a normal conduction state at the temperature at which the quantum circuit 22 is operated, is arranged in a region (second region) sandwiched between the regions in which the quantum circuit 22 is arranged. In other words, the spacer 50A is arranged in a region (second region) surrounded by at least a part of the region in which the quantum circuit 22 is arranged.

FIG. 15 is a diagram showing a third example of a method of arranging the spacer 50 with respect to the substrate 40 in the superconducting circuit device 1 according to the third embodiment. The arrangement method shown in FIG. 15 corresponds to the arrangement method shown in FIG. Here, in the example shown in FIG. 15, the spacer 50B is arranged around the region where the quantum circuit 22 is arranged. Further, the quantum circuit 22 is divided into a region 20cC, a region 20cD, a region 20cE, and a region 20cF near the center of the quantum circuit chip 20. Then, between these four regions 20c, a spacer 50A having a shape in which two rods intersect is arranged.

That is, in the example shown in FIG. 15, the spacer 50B, which is in a superconducting state at the temperature at which the quantum circuit 22 is operated, is arranged in a region (first region) around the region in which the quantum circuit 22 is arranged. There is. Further, the spacer 50A, which is in a normal conduction state at the temperature at which the quantum circuit 22 is operated, is arranged in a region (second region) sandwiched between the regions in which the quantum circuit 22 is arranged. In other words, the spacer 50A is arranged in a region (second region) surrounded by at least a part of the region in which the quantum circuit 22 is arranged.

As described above, in the third embodiment, the spacer 50 has a region (first region) around the region where the quantum circuit 22 is arranged and a region (first region) sandwiched between the region where the quantum circuit 22 is arranged (the region). It is arranged in the second area). The portion (spacer 50B) arranged in the first region is in a superconducting state at the temperature at which the quantum circuit 22 is operated, and the portion (spacer 50A) arranged in the second region is the quantum circuit. It is in a normal conduction state at the temperature at which 22 is operated.

The spacer 50B, which is in a superconducting state at the temperature at which the quantum circuit 22 is operated, is arranged in a region (first region) around the region in which the quantum circuit 22 is arranged. As described above, the magnetic noise for the quantum circuit 22 can be blocked. Further, the spacer 50A, which is in a normal conduction state at the temperature at which the quantum circuit 22 is operated, is arranged in the region (second region) sandwiched between the regions in which the quantum circuit 22 is arranged. As in the first embodiment, the quantum circuit chip 20 can be efficiently cooled. Therefore, in the superconducting circuit device 1 according to the third embodiment, the spacer 50 can function as both a magnetic shield and a heat conduction path. In the examples of FIGS. 13 to 15, since the spacer 50 is arranged near the outer periphery and the center of the quantum circuit chip 20, the space between the quantum circuit chip 20 and the substrate 40 is similar to that of the first embodiment. The accuracy of the distance can be further improved.

In the third embodiment, the spacer 50A and the spacer 50B have different superconducting characteristics. Therefore, in FIGS. 14 and 15, the spacer 50A and the spacer 50B do not have to be integrated. That is, in the third embodiment, the spacer 50A and the spacer 50B can be manufactured separately. If it is possible to integrate the spacer 50A and the spacer 50B, which have different superconducting characteristics, they may be integrated. This makes it possible to easily arrange the spacer 50 on the substrate 40 as described above.

(Modification example)
The present invention is not limited to the above embodiment, and can be appropriately modified without departing from the spirit. For example, in the first embodiment, the method of arranging the spacer 50 is not limited to that illustrated in FIGS. 6 to 11.

For example, as illustrated in FIG. 6, the spacer 50 is arranged near the outer circumference of the quantum circuit chip 20, and further, inside the spacer 50 arranged near the outer circumference, the shape is similar to that of the spacer 50 arranged near the outer circumference. The spacer 50 may be arranged. That is, the spacer 50 in the shape of a hollow quadrangle (quadrilateral) may be doubly arranged. Further, the spacer 50 need not be arranged in a quadrilateral shape as illustrated in FIG. The spacer 50 may be appropriately arranged according to the outer peripheral shape of the quantum circuit chip 20. For example, when the outer peripheral shape of the quantum circuit chip 20 is circular, the spacer 50 may be arranged in a circular shape. These things are the same in other embodiments.

Some or all of the above embodiments may also be described, but not limited to:
(Appendix 1)
A quantum circuit chip in which a quantum circuit using a superconducting material and a first electrode are formed,
The substrate on which the second electrode was formed and
Has a spacer and
The first electrode and the second electrode are connected by bumps.
A superconducting circuit device in which the spacer is made of titanium or a titanium alloy and is arranged at a predetermined position between a quantum circuit chip and a substrate.
(Appendix 2)
A third electrode is formed on the substrate.
The superconducting circuit apparatus according to Appendix 1, wherein the third electrode and the quantum circuit are coupled by a capacity coupling, and the state of the quantum circuit is read out through the capacity coupling.
(Appendix 3)
The superconducting circuit device according to Appendix 1 or 2, wherein the spacer is in a normal conduction state at a temperature at which the quantum circuit is operated.
(Appendix 4)
The superconducting circuit device according to Appendix 1 or 2, wherein the spacer is in a superconducting state at a temperature at which the quantum circuit is operated.
(Appendix 5)
The superconducting circuit device according to any one of Supplementary note 1 to 4, wherein the spacer is arranged in a region around a region in which the quantum circuit is arranged.
(Appendix 6)
The superconducting circuit device according to any one of Appendix 1 to 5, wherein the spacer is arranged in a region sandwiched between regions in which the quantum circuit is arranged.
(Appendix 7)
The spacer is arranged in a first region around the region in which the quantum circuit is arranged and a second region sandwiched between the regions in which the quantum circuit is arranged.
The superconducting circuit device according to any one of Supplementary note 1 to 4, wherein the spacer arranged in the first region and the spacer arranged in the second region are formed to be integrated. ..
(Appendix 8)
The spacer is arranged in a first region around the region in which the quantum circuit is arranged and a second region sandwiched between the regions in which the quantum circuit is arranged.
The spacer arranged in the first region is in a superconducting state at a temperature at which the quantum circuit is operated.
The superconducting circuit device according to Appendix 1 or 2, wherein the spacer arranged in the second region is in a normal conduction state at a temperature at which the quantum circuit is operated.
(Appendix 9)
The superconducting circuit device according to any one of Appendix 1 to 8, wherein the spacer is arranged at a position corresponding to a positioning member formed on the substrate.
(Appendix 10)
Formed of titanium or titanium alloy,
A quantum circuit chip in which a quantum circuit using a superconducting material and a first electrode are formed, and a substrate on which a second electrode is formed are bumped by the first electrode and the second electrode. When connected, it is placed at a predetermined position between the quantum circuit chip and the substrate.
Spacer.
(Appendix 11)
The spacer according to Appendix 10, which is in a normal conduction state at a temperature at which the quantum circuit is operated.
(Appendix 12)
The spacer according to Appendix 10, which is in a superconducting state at a temperature at which the quantum circuit is operated.
(Appendix 13)
The spacer according to any one of Appendix 10 to 12, which is arranged in a region around the region in which the quantum circuit is arranged.
(Appendix 14)
The spacer according to any one of Appendix 10 to 13, which is arranged in a region sandwiched between regions in which the quantum circuit is arranged.
(Appendix 15)
It is arranged in a first region around the region where the quantum circuit is arranged and a second region sandwiched between the regions where the quantum circuit is arranged.
The spacer according to any one of Appendix 10 to 13, wherein the portion arranged in the first region and the portion arranged in the second region are formed to be integrated.
(Appendix 16)
It is arranged in a first region around the region in which the quantum circuit is arranged and a second region sandwiched between the regions in which the quantum circuit is arranged.
The portion arranged in the first region is in a superconducting state at the temperature at which the quantum circuit is operated.
The spacer according to Appendix 10 or 11, wherein the portion arranged in the second region is in a normal conduction state at a temperature at which the quantum circuit is operated.
(Appendix 17)
A quantum circuit chip in which a quantum circuit using a superconducting material and a first electrode are formed is opposed to a substrate on which a second electrode is formed.
A spacer made of titanium or a titanium alloy is placed at a predetermined position on the substrate.
A method for manufacturing a superconducting circuit device in which the first electrode and the second electrode are connected by bumps in a state where the spacer is arranged at a predetermined position on the substrate.
(Appendix 18)
The superconducting circuit apparatus according to Appendix 17, wherein the third electrode formed on the substrate and the quantum circuit are coupled by a capacity coupling, and the state of the quantum circuit is read out through the capacity coupling. Production method.
(Appendix 19)
The method for manufacturing a superconducting circuit device according to Appendix 17 or 18, wherein the spacer is in a normal conduction state at a temperature at which the quantum circuit is operated.
(Appendix 20)
The method for manufacturing a superconducting circuit device according to Appendix 17 or 18, wherein the spacer is in a superconducting state at a temperature at which the quantum circuit is operated.
(Appendix 21)
The method for manufacturing a superconducting circuit device according to any one of Supplementary note 17 to 20, wherein the spacer is arranged in a region around a region in which the quantum circuit is arranged.
(Appendix 22)
The method for manufacturing a superconducting circuit device according to any one of Supplementary note 17 to 21, wherein the spacer is arranged in a region sandwiched between regions in which the quantum circuit is arranged.
(Appendix 23)
The spacer is arranged in a first region around the region in which the quantum circuit is arranged and a second region sandwiched between the regions in which the quantum circuit is arranged.
The superconducting circuit device according to any one of Supplementary note 17 to 20, wherein the spacer arranged in the first region and the spacer arranged in the second region are formed to be integrated. Manufacturing method.
(Appendix 24)
The spacer is arranged in a first region around the region in which the quantum circuit is arranged and a second region sandwiched between the regions in which the quantum circuit is arranged.
The spacer arranged in the first region is in a superconducting state at a temperature at which the quantum circuit is operated.
The method for manufacturing a superconducting circuit device according to Appendix 17 or 18, wherein the spacer arranged in the second region is in a normal conduction state at a temperature at which the quantum circuit is operated.
(Appendix 25)
The method for manufacturing a superconducting circuit device according to any one of Appendix 17 to 24, wherein the spacer is arranged at a position corresponding to a positioning member formed on the substrate.

1 Superconducting circuit device 2 Superconducting circuit mounting structure 3 Reading unit 4 Control unit 10 Bump 12 Capable coupling 14 Inductive coupling 20 Quantum circuit chip 20a Surface 20c Region 22 Quantum circuit 24 Electrode 40 Substrate 42, 44, 46, 48 Electrode 45 Penetration Electrode 50 Spacer 60 Positioning member

Claims (10)

A quantum circuit chip in which a quantum circuit using a superconducting material and a first electrode are formed,
The substrate on which the second electrode was formed and
Has a spacer and
The first electrode and the second electrode are connected by bumps.
A superconducting circuit device in which the spacer is made of titanium or a titanium alloy and is arranged at a predetermined position between a quantum circuit chip and a substrate. A third electrode is formed on the substrate.
The superconducting circuit apparatus according to claim 1, wherein the third electrode and the quantum circuit are coupled by a capacity coupling, and the state of the quantum circuit is read out through the capacity coupling. The superconducting circuit device according to claim 1 or 2, wherein the spacer is in a normal conduction state at a temperature at which the quantum circuit is operated. The superconducting circuit apparatus according to claim 1 or 2, wherein the spacer is in a superconducting state at a temperature at which the quantum circuit is operated. The superconducting circuit device according to any one of claims 1 to 4, wherein the spacer is arranged in a region around a region in which the quantum circuit is arranged. The superconducting circuit device according to any one of claims 1 to 5, wherein the spacer is arranged in a region sandwiched between regions in which the quantum circuit is arranged. The spacer is arranged in a first region around the region in which the quantum circuit is arranged and a second region sandwiched between the regions in which the quantum circuit is arranged.
The superconducting circuit according to any one of claims 1 to 4, wherein the spacer arranged in the first region and the spacer arranged in the second region are integrally formed. apparatus. The spacer is arranged in a first region around the region in which the quantum circuit is arranged and a second region sandwiched between the regions in which the quantum circuit is arranged.
The spacer arranged in the first region is in a superconducting state at a temperature at which the quantum circuit is operated.
The superconducting circuit device according to claim 1 or 2, wherein the spacer arranged in the second region is in a normal conduction state at a temperature at which the quantum circuit is operated. A spacer made of titanium or a titanium alloy and used in superconducting circuit equipment. A quantum circuit chip in which a quantum circuit using a superconducting material and a first electrode are formed is opposed to a substrate on which a second electrode is formed.
A spacer made of titanium or a titanium alloy is placed at a predetermined position on the substrate.
A method for manufacturing a superconducting circuit device in which the first electrode and the second electrode are connected by bumps in a state where the spacer is arranged at a predetermined position on the substrate.

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