JPS61248471A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS61248471A
JPS61248471A JP8853485A JP8853485A JPS61248471A JP S61248471 A JPS61248471 A JP S61248471A JP 8853485 A JP8853485 A JP 8853485A JP 8853485 A JP8853485 A JP 8853485A JP S61248471 A JPS61248471 A JP S61248471A
Authority
JP
Japan
Prior art keywords
layer
single crystal
wiring
film
insulation film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8853485A
Other languages
Japanese (ja)
Other versions
JPH0744162B2 (en
Inventor
Yoichi Nishino
洋一 西野
Masao Kawamura
川村 雅雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP60088534A priority Critical patent/JPH0744162B2/en
Publication of JPS61248471A publication Critical patent/JPS61248471A/en
Publication of JPH0744162B2 publication Critical patent/JPH0744162B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To obtain a multi-layer wiring with an extremely high wiring density and a high reliability by a method wherein a conductive substance composed of a column shape single crystal is employed as a layer connector which is so provided as to penetrate through a layer insulation film. CONSTITUTION:An N-type impurity doped layer 12 and a surface protection film 13 are formed on a silicon wafer 11. Gold is implanted by a converged ion-beam method into the part of the impurity doped layer 12 where the layer connection is necessary. The wafer is transferred into a cylindrical reaction furnace and placed inside the reaction furnace where the temperature is kept at 375 deg.C and a mixture gas of SiCl4/H2 system is introduced and reaction is induced by a photoexcitation and supersaturated silicon is deposited from liquid alloy drop and a column shape silicon single crystal 14 with a diameter of about 1mum is made to grow by VLS. Then a layer insulation film 15 is formed for the thickness of 2mum and the whole surface of the layer insulation film 15 is etched to expose the top of the column shape single crystal 14 and aluminum or aluminum alloy is evaporated to form an upper wiring layer 16. With this constitution, as the wiring layer is evaporated on the insulation film surface without difference in level, a film with excellent uniformity can be formed.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は半導体装置に係り、詳しくは、高い信頼性を有
する微細多層配線を有する半導体装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having fine multilayer wiring having high reliability.

〔発明の背景〕[Background of the invention]

一般に、半導体装置においては、半導体基板表面および
表面上に不純物ドープ層、多結晶シリコン、金属シリサ
イド、もしくはアルミニウム合金等の導電層が絶縁膜と
ともに多層構造で配置される。これらの導電層を相互に
電気的に接続するために、導電層間に位置した絶縁膜の
一部を開孔し、(このような絶縁膜の開口部をコンタク
トホールと称する)。このコンタクトホール内に導°電
性物質を充填して、上下の導電層間の電気的接続を行な
う。ところで、前記絶縁膜は通常160〜2.5μm程
度の厚さを有しており、従って絶縁膜上部から下部導電
層に達するコンタクトホールが形成されると、1.0〜
2.5μmに達する段差が生ずる。このため、コンタク
トホールを開孔した後、絶縁膜上に、たとえばアルミニ
ウム配線層を形成した場合、配線層が段差部で非常に薄
くなり、コンタクトホールの形状によっては、完全に配
線が断線することもある。その結果、歩留が著しく低下
するばかりでなく、配線層が薄くなった部分で配線の寿
命が短くなり、信頼性も著しく低下してしまう。
Generally, in a semiconductor device, an impurity-doped layer, a conductive layer such as polycrystalline silicon, metal silicide, or an aluminum alloy is arranged on the surface of a semiconductor substrate together with an insulating film in a multilayer structure. In order to electrically connect these conductive layers to each other, a hole is formed in a part of the insulating film located between the conductive layers (such an opening in the insulating film is called a contact hole). This contact hole is filled with a conductive material to establish electrical connection between the upper and lower conductive layers. By the way, the insulating film usually has a thickness of about 160 to 2.5 μm, so when a contact hole is formed from the upper part of the insulating film to the lower conductive layer, the thickness is about 1.0 to 2.5 μm.
A step difference of up to 2.5 μm occurs. For this reason, if, for example, an aluminum wiring layer is formed on the insulating film after contact holes are opened, the wiring layer becomes extremely thin at the stepped portions, and depending on the shape of the contact hole, the wiring may be completely disconnected. There is also. As a result, not only the yield is significantly lowered, but also the life of the wiring is shortened in the portion where the wiring layer is thinner, and the reliability is also significantly lowered.

このような問題を解決するために、従来、たとえば特開
昭59−103355号に記載のように、コンタクトホ
ールの一部もしくは全部を多結晶シリコン等により充填
する方法が提案された。しかし、層間接続体として、結
晶粒界を有する多結晶シリコンを用いた場合、接続体の
導電性が非常に低くなってしまうという問題が生ずる。
In order to solve this problem, a method has been proposed in which a part or all of the contact hole is filled with polycrystalline silicon or the like, as described in, for example, Japanese Patent Laid-Open No. 59-103355. However, when polycrystalline silicon having grain boundaries is used as the interlayer connector, a problem arises in that the conductivity of the connector becomes extremely low.

さらに、多層配線におけるコンタクトホールがさらに微
細化されると、従来の技術によっては、コンタクトホー
ルを形成した後、このような微細なコンタクトホールを
用いて眉間接続を行なうことは著しく困難となることが
予想される。
Furthermore, as the contact holes in multilayer wiring become further miniaturized, it may become extremely difficult to make glabella connections using such fine contact holes after forming the contact holes using conventional techniques. is expected.

また、従来、たとえば特開昭58−225650号に記
載のように、リフトオフ法等により、多結晶のアルミニ
ウム合金などよりなる柱状の層間接続体を形成する方法
が提案されている。しかし、この方法を用いても、層間
接続体がさらに微細化すると、多結晶接続体中を横断し
て存在する結晶粒界のために断線が発生してしまい、信
頼性の高い微細な接続柱を形成することが困難であった
Furthermore, a method of forming a columnar interlayer connection body made of polycrystalline aluminum alloy or the like by a lift-off method or the like has been proposed, for example, as described in Japanese Patent Application Laid-Open No. 58-225650. However, even if this method is used, as the interlayer connections become finer, disconnections will occur due to the grain boundaries that exist across the polycrystalline connections, making it difficult to create highly reliable fine connection pillars. was difficult to form.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、上記従来技術の有する問題を解決し、
極めて高密度で、しかも信頼性の高い多層配線を有する
半導体装置を提供することにある。
The purpose of the present invention is to solve the problems of the above-mentioned prior art,
An object of the present invention is to provide a semiconductor device having extremely high density and highly reliable multilayer wiring.

〔発明の概要〕[Summary of the invention]

上記目的を達成するため、本発明は、層間絶縁膜を貫い
て設けられる層間接続体として、柱状単結晶よりなる導
電体を用いる。すなわち、眉間絶縁膜を形成する以前に
、たとえば、V L S (Vapor−Liquid
−5olid )成長法により、半導体基板上あるいは
配線基板上に柱状単結晶体を形成する。このVLS成長
については、ジャーナル・オブ・エレクトロケミカル・
ソサイテイ(J、 Electrocham、Soc、
) 113.1300 (1966年)における「シリ
コン結晶の制御された気相−液相−固相成長」(Con
trolled Vapor−Liquid−3oli
d Growth ofSilicon Crysta
ls)と題する論文に記載されている。この方法に従っ
て、所望の高さを有する導電性材料の柱状単結晶体を成
長させた後1層間絶縁膜を形成する。その後、たとえば
バイアススパッタ法でエツチングを行なって、柱状単結
晶体の頂部を露出させ、その上に第2の配線層を形成す
れば、導電性材料の柱状単結晶体からなる層間絶縁体を
有する、多層配線が形成される。
In order to achieve the above object, the present invention uses a conductor made of columnar single crystal as an interlayer connector provided through an interlayer insulating film. That is, before forming the glabellar insulating film, for example, VLS (Vapor-Liquid
-5olid) A columnar single crystal is formed on a semiconductor substrate or a wiring substrate by a growth method. This VLS growth is described in the Journal of Electrochemical
Society (J, Electrocham, Soc,
) 113.1300 (1966), “Controlled Vapor-Liquid-Solid Growth of Silicon Crystals” (Con
Trolled Vapor-Liquid-3oli
d Growth of Silicon Crysta
It is described in a paper entitled ls). According to this method, a single interlayer insulating film is formed after growing a columnar single crystal of a conductive material having a desired height. After that, etching is performed using, for example, a bias sputtering method to expose the tops of the columnar single crystals, and a second wiring layer is formed thereon, thereby forming an interlayer insulator made of the columnar single crystals of a conductive material. , multilayer wiring is formed.

この際、上記絶縁膜として平坦性のある材料からなる膜
を使用し、さらに、上記柱状単結晶体の頂部を、バイア
ススパッタ法などによって露出させるようにすれば、平
坦度および上部配線層との電気的接続が、いずれも極め
て良好になる。
At this time, if a film made of a material with flatness is used as the insulating film, and if the top of the columnar single crystal is exposed by bias sputtering or the like, the flatness and the upper wiring layer can be improved. The electrical connections are all very good.

〔発明の実施例〕[Embodiments of the invention]

以下、実施例により本発明の詳細な説明する6実施例1 第1図(a)〜(d)は、本発明の一実施例を示す工程
図である。
Hereinafter, the present invention will be explained in detail with reference to 6 Examples. Embodiment 1 FIGS. 1(a) to 1(d) are process diagrams showing one embodiment of the present invention.

第1図(a)に示すように、シリコンウェハ11(面方
位(111)、P型)上に、拡散法またはイオン注入法
によりN型不純物ドープ層12および表面保護膜13を
形成した。上記不純物ドープ層12の層間接続を必要と
する位置に、集束イオンビーム法により金を注入した。
As shown in FIG. 1(a), an N-type impurity doped layer 12 and a surface protection film 13 were formed on a silicon wafer 11 (plane orientation (111), P type) by a diffusion method or an ion implantation method. Gold was implanted into the impurity-doped layer 12 at positions where interlayer connections were required by a focused ion beam method.

このイオンビームの直経あるいは強度を調節することに
より、金−シリコン合金領域の大きさを直経0.5〜1
0μmの範囲内で制御することが可能である。
By adjusting the diameter or intensity of this ion beam, the size of the gold-silicon alloy region can be adjusted from 0.5 to 1
It is possible to control within a range of 0 μm.

上記ウェハをシリンダ型反応炉内に移し、金−シリコン
合金(31a t%Si)の共晶温度370℃以上に加
熱すると、金を注入した位置において金−シリコン共晶
合金の液滴が形成される。375℃に保った反応炉内に
設置し、S x CQ 4 / Hx系の混合ガスを導
入し、光励起法で反応させて、合金液滴から過飽和のシ
リコンを析出させて直経1μm程度の柱状シリコン単結
晶14をvLS成長させた(第1図(b))。
When the wafer is transferred to a cylinder-type reactor and heated to the eutectic temperature of 370°C or higher for gold-silicon alloy (31at%Si), droplets of gold-silicon eutectic alloy are formed at the positions where gold is injected. Ru. The reactor was placed in a reactor maintained at 375°C, a mixed gas of S x CQ 4 / Hx was introduced, and a reaction was carried out using a photoexcitation method to precipitate supersaturated silicon from the alloy droplets, forming a columnar shape with a diameter of approximately 1 μm. A silicon single crystal 14 was grown by vLS (FIG. 1(b)).

本実施例では上記柱状単結晶体14は、高さ1.5μm
まで成長させた。また、上記柱状単結晶体4の成長方向
は<111>であり、その柱面ば、(211)が6面、
(110)が6面の合計12面より構成されていること
がX線回折法により確認された。この柱状単結晶体14
の直経は、前記金−シリコン合金領域の大きさを調節し
ておくことにより、0.5〜10μm範囲内で制御可能
である。上記柱状単結晶体14にリンまたはボロンをド
ープして導電体にした。その結果、コンタクトホールの
層間接続体として多結晶シリコンを用いる従来方法と比
較して、層間接続体の導電性を約3倍向上することがで
きた。
In this embodiment, the columnar single crystal body 14 has a height of 1.5 μm.
grew up to. The growth direction of the columnar single crystal 4 is <111>, and the columnar faces are 6 (211) faces,
It was confirmed by X-ray diffraction that (110) was composed of 6 planes, a total of 12 planes. This columnar single crystal body 14
The direct diameter of the gold-silicon alloy region can be controlled within a range of 0.5 to 10 μm by adjusting the size of the gold-silicon alloy region. The columnar single crystal body 14 was doped with phosphorus or boron to make it a conductor. As a result, the conductivity of the interlayer connector could be improved approximately three times as compared to the conventional method using polycrystalline silicon as the interlayer connector of the contact hole.

次に、第1図(c)に示す如く、平面平担化効果を有す
る層間絶縁膜15を厚さ2μm形成した。
Next, as shown in FIG. 1(c), an interlayer insulating film 15 having a flattening effect was formed to a thickness of 2 μm.

本実施例では眉間絶縁膜15としてはバイアススパッタ
法によるSiO2膜を用いた糸、通常の化学気相成長法
による5in2やSi、N4膜等をスパッタエツチング
により平担化することによっても同様に用いることがで
きる。上記層間絶縁膜15の全表面をエツチングして柱
状単結晶体14の頂部を露出させた。引き続いて、上部
配線層16としてアルミニウムあるいはアルミニウム合
金を蒸着した。このようにすれば、段差のない絶縁膜表
面に蒸着することになるので、均一性の良い被膜を形成
することができる。
In this embodiment, as the glabellar insulating film 15, a thread using a SiO2 film formed by bias sputtering, a 5in2 film formed by ordinary chemical vapor deposition, Si, N4 film, etc., which is planarized by sputter etching, are also used. be able to. The entire surface of the interlayer insulating film 15 was etched to expose the tops of the columnar single crystals 14. Subsequently, aluminum or an aluminum alloy was deposited as the upper wiring layer 16. In this way, since the vapor is deposited on the surface of the insulating film with no steps, it is possible to form a film with good uniformity.

実施例2 第2図は、本発明の他の実施例としての配線の眉間接続
を示した断面図である6 半導体基板2″1の表面を酸化膜22で被覆した配線基
板上に、下部配線層23を形成した6該配線層23は厚
さが0.5〜1.2μm程度のアルミニウムやアルミニ
ウム合金等が用いられるが、あらかじめ単結晶化してお
くことが望ましい。本実施例では面方位(111)とし
た単結晶アルミニウム配線層を用いた。この配線層23
をフォトエツチング法により配線パターンニングを行な
った後、表面保護膜24を全面に被覆した。上記配線層
23上において、層間接続を必要とする位置を被覆して
いる酸化膜を局部的に除去した後、実施例1と同様にし
て、集束イオンビーム法によりゲルマニウムを注入した
。上記基板をシリンダ型反応炉内において、アルミニウ
ムーゲルマニウム合金(30,3at%Ge)の共晶温
度424℃以上に加熱すると、ゲルマニウムを注入した
位置においてアルミニウムーゲルマニウム共晶合金液滴
が形成される。そこで、430℃に保った反応炉内にト
リイソブチルアルミニウムのガスを導入して、合金液滴
から過飽和のアルミニウムを析出させ直径1μm程度の
柱状アルミニウム単結晶25がVLS成長させた。上記
柱状単結晶体25の直経は、0.5〜10μmの範囲内
で制御可能である。
Embodiment 2 FIG. 2 is a cross-sectional view showing a connection between the eyebrows of wiring as another embodiment of the present invention. The wiring layer 23 on which the layer 23 is formed is made of aluminum, aluminum alloy, etc. with a thickness of about 0.5 to 1.2 μm, but it is preferable to form it into a single crystal in advance.In this example, the plane orientation ( 111) was used.This wiring layer 23
After wiring patterning was performed by photoetching, the entire surface was covered with a surface protective film 24. After locally removing the oxide film covering the positions requiring interlayer connections on the wiring layer 23, germanium was implanted by the focused ion beam method in the same manner as in Example 1. When the above substrate is heated in a cylindrical reactor to the eutectic temperature of aluminum-germanium alloy (30,3 at% Ge) of 424°C or higher, aluminum-germanium eutectic alloy droplets are formed at the positions where germanium is injected. . Therefore, triisobutylaluminum gas was introduced into the reactor maintained at 430° C., supersaturated aluminum was precipitated from the alloy droplets, and columnar aluminum single crystals 25 with a diameter of about 1 μm were grown by VLS. The diameter of the columnar single crystal body 25 can be controlled within the range of 0.5 to 10 μm.

次に、実施例1と同様にして、平面平担化効果を有する
層間絶縁膜26を形成した後、酸膜の全表面をエツチン
グして柱状単結晶体25の頂部を露出させた。引き続い
て、上部配線層27としてアルミニウムまたはアルミニ
ウム合金を蒸着して2層配線を構成した。
Next, in the same manner as in Example 1, an interlayer insulating film 26 having a flattening effect was formed, and then the entire surface of the acid film was etched to expose the tops of the columnar single crystal bodies 25. Subsequently, aluminum or an aluminum alloy was deposited as the upper wiring layer 27 to form a two-layer wiring.

本実施例では、層間接続体としてアルミニウム単結晶を
用いているため、導電性、信頼性共に従来の配線よりも
著しく向上させることができた。
In this example, since aluminum single crystal was used as the interlayer connector, both conductivity and reliability were significantly improved compared to conventional wiring.

また、接続体を単結晶にしたため、従来の多結晶接続体
においてしばしば問題となるところの結晶粒界における
断線発生を完全に防止することができた。この効果は、
特に、接続体の直経を1μm程度に微細化した場合にg
著であり、従来の多結晶接続体を用いた場合より、3〜
S倍長寿命であることが認められた。
Furthermore, since the connecting body is made of a single crystal, it is possible to completely prevent disconnection at grain boundaries, which is often a problem in conventional polycrystalline connecting bodies. This effect is
In particular, when the direct diameter of the connecting body is reduced to about 1 μm, the g
3 to 3 compared to using conventional polycrystalline connectors.
It was found that the lifespan was S times longer.

上記実施例においては、VLS法における共晶を作るた
めにドープする金属として、金およびゲルマニウムを用
いたが、それ以外の物質を用いることもできる。また、
柱状単結晶を作る方法もVLS@’11ではなく、コン
タクトホール部における選択成長を用いてもよく、また
、単結晶膜を全面に形成した後、不要部をドライエツチ
ングによって選択的に除去してもよい。なお、上記実施
例では、共晶を作るためには打込金属としてAuとGo
を用いた例を示したが、その他にもSn。
In the above embodiment, gold and germanium were used as the metals to be doped to create the eutectic in the VLS method, but other materials may also be used. Also,
The method for producing columnar single crystals is not VLS@'11, but selective growth in contact hole areas may be used, or after forming a single crystal film on the entire surface, unnecessary parts are selectively removed by dry etching. Good too. In the above example, Au and Go are used as the implanted metals to make the eutectic.
Although an example using Sn was shown, there are also other examples using Sn.

Si、Beなどを用いても低融点の共晶が形成され、本
発明において使用できる。
Even if Si, Be, etc. are used, a low melting point eutectic is formed and can be used in the present invention.

〔発明の効果〕〔Effect of the invention〕

上記説明から明らかなように、本発明によれば、従来装
置のコンタクトホール部の段差に起因して発生する種々
な障害を効果的に除去することができる。また、単結晶
よりなる層間接続体を有するため、多結晶シリコンの場
合と比較して、その導電性を3倍程度向上することがで
きる。
As is clear from the above description, according to the present invention, it is possible to effectively eliminate various obstacles that occur due to the step difference in the contact hole portion of the conventional device. Furthermore, since the interlayer connector is made of single crystal, the conductivity can be improved by about three times compared to the case of polycrystalline silicon.

さらに、層間接続体としてアルミニウム単結晶のような
導電体を用いた場合、層間接続体の導電性をさらに向上
することができると同時に、接続体の微細化にともなっ
て発生する、接続体中の結晶粒界における断線も防止さ
れる。一方、本発明によれば、コンタクトホールをとく
に形成する必要がないため、層間接続体としての柱状単
結晶体の寸法を小さくすることにより半導体装置の微細
化が可能となり、集積度および信頼性を著しく向上させ
ることができる。
Furthermore, when a conductive material such as aluminum single crystal is used as an interlayer connector, the conductivity of the interlayer connector can be further improved, and at the same time, it is possible to further improve the conductivity of the interlayer connector. Disconnection at grain boundaries is also prevented. On the other hand, according to the present invention, since there is no need to specifically form contact holes, it is possible to miniaturize the semiconductor device by reducing the dimensions of the columnar single crystal as the interlayer connector, thereby improving the degree of integration and reliability. can be significantly improved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図および第2図は、それぞれ本発明の異なる実施例
を示す工程図および断面図である。 11.21・・・半導体基板、12・・・N型拡散層(
第1の導電層)、13.24・・・表面保護膜、14・
・・柱状シリコン単結晶体(層間接続体)、15゜26
・・・層間絶縁膜、16.27・・・上部配線層(第2
の導電層)、22・・・酸化膜、23・・・下部配線層
(第1の導電層)、25・・・柱状アルミニウム単結■
 1  図
FIG. 1 and FIG. 2 are a process diagram and a sectional view showing different embodiments of the present invention, respectively. 11.21... Semiconductor substrate, 12... N-type diffusion layer (
first conductive layer), 13.24... surface protective film, 14.
...Columnar silicon single crystal (interlayer connection), 15°26
...Interlayer insulating film, 16.27... Upper wiring layer (second
conductive layer), 22... oxide film, 23... lower wiring layer (first conductive layer), 25... columnar aluminum single crystal ■
1 figure

Claims (1)

【特許請求の範囲】[Claims] 1、所望の形状を有する第1の導電層と、該第1の導電
層上に絶縁膜を介して形成された第2の導電層を少なく
ともそなえ、上記第1および第2の導電層は柱状の単結
晶導電体によつて、互いに電気的に接続されているこを
特徴とする半導体装置。
1. At least a first conductive layer having a desired shape and a second conductive layer formed on the first conductive layer via an insulating film, the first and second conductive layers having a columnar shape. A semiconductor device characterized in that the semiconductor devices are electrically connected to each other by a single crystal conductor.
JP60088534A 1985-04-26 1985-04-26 Method for manufacturing semiconductor device Expired - Lifetime JPH0744162B2 (en)

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JP60088534A JPH0744162B2 (en) 1985-04-26 1985-04-26 Method for manufacturing semiconductor device

Publications (2)

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JPS61248471A true JPS61248471A (en) 1986-11-05
JPH0744162B2 JPH0744162B2 (en) 1995-05-15

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04159755A (en) * 1990-10-23 1992-06-02 Nec Kyushu Ltd Semiconductor device
JPH08293548A (en) * 1995-04-21 1996-11-05 Nec Corp Semiconductor device and manufacture thereof
JP2012033905A (en) * 2010-07-02 2012-02-16 Semiconductor Energy Lab Co Ltd Semiconductor device and manufacturing method of semiconductor device
WO2023195132A1 (en) * 2022-04-07 2023-10-12 富士通株式会社 Electronic device, electronic system and method for producing electronic device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5638838A (en) * 1979-09-06 1981-04-14 Pioneer Electronic Corp Manufacture of semiconductor device
JPS594015A (en) * 1982-06-30 1984-01-10 Fujitsu Ltd Semiconductor device and its manufacture

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5638838A (en) * 1979-09-06 1981-04-14 Pioneer Electronic Corp Manufacture of semiconductor device
JPS594015A (en) * 1982-06-30 1984-01-10 Fujitsu Ltd Semiconductor device and its manufacture

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04159755A (en) * 1990-10-23 1992-06-02 Nec Kyushu Ltd Semiconductor device
JPH08293548A (en) * 1995-04-21 1996-11-05 Nec Corp Semiconductor device and manufacture thereof
JP2012033905A (en) * 2010-07-02 2012-02-16 Semiconductor Energy Lab Co Ltd Semiconductor device and manufacturing method of semiconductor device
US8969866B2 (en) 2010-07-02 2015-03-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
WO2023195132A1 (en) * 2022-04-07 2023-10-12 富士通株式会社 Electronic device, electronic system and method for producing electronic device

Also Published As

Publication number Publication date
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