JPS60186038A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a wiring layer from disconnecting at the electrode contacting window and a resistance from increasing by providing a metal wiring layer of 2-layer structure that aluminum layers are laminated on a high melting point metal or its silicide layer which is chemically grown in vapor phase. CONSTITUTION:A layer 15W which forms a metal wiring layer 15 is formed by chemical vapor phase growing method. Accordingly, the layer is formed substantially in uniform thickness on the inner surface even in a deep electrode contacting window 14 having 1.5mum in opening size and 1mum of depth. An aluminum layer 15Al of the electrode contacting window 14 of the case that the aluminum layer 15Al after finishing the formation of a W layer 15W is formed in a sectional shape to form a region 16 formed in an extremely reduced thickness to cause a disconnection. However, since the W layer 15W having a resistance value lower by 2,000-3,000Angstrom of thickness is disposed on the lower layer, a current flows through the layer 15W and does not generate a heat in the thin region 16 of the Al layer 15Al at the wiring layer 15 at the operating time of the IC and hence the energizing time, the disconnection of the Al layer 15Al is prevented, and even if the Al layer 15Al is disconnected, the layer 15W has sufficiently low resistance. Thus, the wiring resistance is not largely increased.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a semiconductor device, and particularly to the structure of a metal wiring layer in a semiconductor device.

(b) Background of the technology Aiming for high integration in semiconductor integrated circuit devices (TC) is extremely important because it improves circuit function and speed of operation.
This is an important issue. For this reason, semiconductor components have been significantly miniaturized and their arrangement density has become extremely high.

In order to completely lead out the electrode wiring from the functional area of the semiconductor element under difficult circumstances, the size of the electrode contact window formed in the insulating film has become extremely fine. However, since the thickness of the insulating film is not formed very thin in order to obtain a predetermined dielectric strength voltage, the electrode contact window has a deep shape with a depth almost approaching the opening size.

(e) Prior art and problems In conventional semiconductor ICs, the metal wiring layer is generally made of aluminum A (At) or aluminum silicon (At-
8i) or the like. However, since the wiring layer made of At or At alloy is deposited by vapor deposition or sputtering, the step coverage is not good, so the wiring layer in the deeper electrode contact window is extremely thin. Due to this increase in resistance, the ff gracing effect, etc., disconnection at the electrode contact window is very likely to occur.
Figure 1 shows the conventional electrode J contact 1! In the figure, 1 is a semiconductor substrate, 2 is a functional area, and 3 is Il! 1 membrane, 4 electrode contact window, IJAt
The wiring layer 6 represents a portion where the At island is thin and disconnection is likely to occur.

In semiconductor ICs that are not highly integrated, the sides of the electrode contact windows are formed in a gently sloped manner to prevent wire breakage. In ICs, it is difficult to take the above-mentioned measure of making the opening sufficiently large, since this leads to a decrease in the degree of integration.

Therefore, under the At wiring layer, a polycrystalline silicon layer grown in a vapor phase with good coverage, that is, even in the electrode contact window part, is provided, so that even if the A4 layer is disconnected, A method of making the wiring layer conductive using a polycrystalline silicon layer has also been proposed, but in this method, the resistivity of the polycrystalline silicon layer is about two orders of magnitude higher than that of At, so when the At layer is disconnected, wiring resistance increases significantly,
Furthermore, due to thermal history, a large amount of 81 diffuses into the At layer, which increases the resistance of the At layer, resulting in a significant increase in wiring resistance and a problem in that the operating speed of the IC decreases. Ta.

(Middle Purpose of the Invention In view of the above-mentioned problems, the present invention provides a wiring structure that completely prevents disconnection of the wiring layer and increase in resistance in the miniaturized electrode contact window portion in semiconductor ICs that are becoming highly integrated. This object is achieved by a semiconductor device having an aluminum or aluminum alloy wiring 1-w having the structure shown below.

(e) Structure of the Invention That is, the present invention provides a semiconductor device in which a layer made of aluminum or an aluminum alloy is laminated on a layer of a high melting point metal or its silicide grown by chemical vapor deposition.
(f) Embodiments of the Invention Hereinafter, embodiments of the invention will be explained with reference to the drawings. 0 Figure 2 shows the structure of the interconnect layer in one embodiment. A top view of the electrode contact window schematically showing [), a sectional view taken along the line A-A (
c9 and BB cross-sectional views; FIGS. 3) to 3(e) are schematic cross-sectional views showing an embodiment of a manufacturing method for a semiconductor device having an uninvented structure; FIG.

FIG. 2 is a top view 1) schematically showing an example of the structure of the metal wiring layer, which is a feature of the semiconductor device of the present invention, with respect to the electrode contact window portion where the effect is most noticeable.
A sectional view (b) and B-B sectional view? −). In the figure, 11 is a semiconductor substrate, 12 is a functional region such as a base region, an emitter region, a collector contact region, etc. in a bipolar IC, and 13 is a silicon dioxide (
Slot), an insulating film made of pentasilicate glass (PSG), etc., with a thickness of about 1 [μm], 14 has a side of 1.5 [μm], for example.
μm) electrode contact window, 15 is a metal wiring layer, 1
5W is, for example, a chemical vapor deposition tungsten layer with a thickness of about 2000 to 300 (A), and 15A/ is, for example, a submerged layer.

Thickness 8000-7000 (A
) layer of aluminum (At), 16 is an At layer (15
At) indicates a thinly formed area.

In the above embodiment, the tungsten (W) layer 15W constituting the metal wiring layer 15 is formed by chemical vapor deposition;
As above, opening size is 1.5 [μm], depth is 1 [μm]
Even the electrode contact window 14, which is relatively deep, is formed to have a substantially uniform thickness on its inner surface. And the above w+*xs
After the formation of w, the electrode contact window 14 when forming the At layer 15AAt has an opening size of 1 [μm] and a depth of 1 [μm].
Therefore, the AL layer 15At is formed in a cross-sectional shape as shown in the figure, and a region 16t is formed in an extremely thin layer that may lead to disconnection. However, the underlying layer has a thickness of 2
Since the W layer 15W having a low resistance value of about 000 to 3000 [persons] is disposed, current flows through the W layer 15W when the IC 17) is in operation, that is, when it is energized.
does not generate heat in the thin region 16 of the At layer 15At, and therefore disconnection of the AI-WRx5ht is prevented.Also, even if the At layer 15At is disconnected, the resistance of the W layer 15W is sufficiently low. No significant increase in wiring resistance θHere, the specific resistance of the wiring layer material is shown for reference: At is 2.7X1σ' (Q-cm), W is 5.7X10' [:, Q-tan], tungsten silicide (WShJ is 8~9X10-' Cn, -c
m), polycrystalline silicon has a resistance of about 10-8 [Ω-Kushi]. From this value, it is clear that the same effect can be obtained even if a ws i layer is used instead of the W layer.

Next, a method for forming a metal wiring layer with the above structure will be explained with reference to the process cross-sectional diagrams shown in FIGS. explain.

The bipolar Q transistor of in-planar structure shown in FIG. 3U) is formed by conventional methods. That is, for example, selectively n
After forming the type collector region 22, a transistor formation region al and a collector contact formation region a in the transistor formation region are formed on the substrate by a normal selective oxidation method.
! A first silicon dioxide (Sin) insulating film 23'l having a thickness of about 1 μm separates the base forming region 83 from the base forming region 83.
i- is formed, and then an n-type impurity is selectively introduced at a high concentration into the collector contact formation region at in alignment with the first insulating film 23 to form an n+-type collector contact region 24. A p-type impurity is selectively introduced at a high concentration into the base formation region a8 in alignment with the insulating film 23, thereby forming the entire p-type base region 25.

Referring to FIG. 3, chemical vapor deposition (C) is then deposited on the substrate according to a conventional method.
For example, a second layer with a thickness of about 1 [μm] is formed by a method such as VD).
The insulating film 26 is entirely formed on the Si substrate, and then a collector contact window 27. having an opening size of, for example, about 1.5 [μm] square is formed on the second Si02 insulating film 26 by ordinary lithography. Emitter contact window 28 and base contact window 29f: are formed, and then the base contact window 29 is masked to align the collector contact window 27 and emitter contact window 28 of the second 8102 insulating film 26 to these contact windows. Selectively introduce n-type impurities at a high concentration. + Green substrate contact areas 3o and n+
The entire mold emitter region 31 is formed. The above steps follow the usual method of manufacturing an in-planar bipolar conductor device.

Referring to FIG. 3(C) Next, in forming the entire metal wiring layer of the two-layer structure of W and kt shown in the embodiment according to the present invention, first, the formation of the transistor is completely completed, and the contact window 27 is formed on the surface. ,2
2nd Sin with 8.29ffi.

For example, 0
5 to 1 (Tungsten hexabutide (WF) at around TorrJ
a), hydrogen (几), and fixed wood (N!) in a mixed gas at a temperature of about 300 to 400 (℃) and a thickness of 200C)
-3000 [: Contains] Hodada Tungsten (W) 7 cans 32
(Corresponding to FIG. 2 15W) Perform chemical vapor deposition. In addition, in this chemical vapor deposition technique, since tungsten N grows using the sloped Ifi of the substrate as a nucleus, the opening size is 1.5 [μm] and the depth is about 1 [μm] as described above. The tungsten layer 32 is also formed on the inner surfaces of the contact windows 27, 28, and 29 to have a uniform thickness. vertically (
7 hand song -e jh-2+aj%? 'Tame17Jζ
An A4 layer 33 (corresponding to FIG. 15AL in FIG. 2) having a thickness of 8,000 to 7,000 degrees is deposited on the substrate by the eleventh ring method or vapor deposition method. Here, as mentioned above, there is an At inside the deep contact window 27, 28, 29.
Region 34 (FIG. 2, 16 a e
16b) is formed.

(see Fig. 3) Next, the pAt layer 3 is etched by phosphorography technology using reactive ion etching method using ordinary chlorine-based gas.
3 and W layer 32 are patterned, and W layer 32 and A
Collector wiring layer 35 consisting of 211# structure of t layer. Emitter wiring layer 36. A base wiring layer 37 is formed.

Thereafter, although not shown, an insulating film for surface protection is formed as usual, and the in-planar bipolar semiconductor device according to the invention is completed.

In addition to W, tungsten silicide (W-8i) is also used as a lower wiring material in the wiring layer. In this case, the W-8i layer contains tungsten hexabutide (WF, ) and monosilane (Si-H&) of about 1 (Torr).
It is grown in a mixed gas at a temperature of about 300 to 400 C.degree.

As the upper layer wiring material in the wiring layer above, At
Not only K but also At alloys and all other metals having high conductivity are used.

Effects of the Invention As shown in the above embodiments, in the structure of the present invention, for example, 20 to 30% of the entire metal wiring layer is formed by chemical vapor deposition in the lower layer of the metal wiring layer. Thickness of about
! A layer made of a low-resistance, high-melting-point metal or its silicide is disposed, and as described above, the chemical vapor deposition layer has a substantially uniform thickness even on the circular surface of the contact window, which is deep due to its nature. Therefore, a highly conductive metal layer such as aluminum, which is the main wiring material, is normally deposited on the layer made of the high melting point metal or its silicide by sputtering or evaporation, and the step coverage is poor. Even when a very thin, high-resistance region is formed inside the contact window using As it flows through the area, heat is generated in the area! The disconnection of the wiring layer, which conventionally occurs, is prevented by the ignition.

Therefore, according to the present invention, the manufacturing yield and reliability of semiconductor integrated circuit devices that are highly integrated and highly dense are improved.

[Brief explanation of drawings]

FIG. 1 is a schematic cross-sectional view of an electrode contact window in a conventional semiconductor device, and FIG. 2 is a top view of an electrode contact window schematically showing the structure of a wiring layer in an embodiment of the invention. , A-A arrow Wlr sectional view (C') and B-B arrow sectional view ρ; This is a cross-sectional view of a schematic 1 showing an example. In the figure, 11 is a semiconductor substrate, 12 is a functional area, 13 is an expanded insulating film, 14 is an electrode contact window, and 15 is a metal wiring layer.
15W beam y Gesten layer, 15At aluminum layer,
16 is a region where a thin aluminum layer is formed, 21 is a p-type silicon substrate, 22 is an n-type collector region, and 23 is a first ? 3 is the edge film, 24 is the n++ collector contact region,
25 is a p-type base region, 26 is a second insulating film, 27 is a collector contact window, 28 is an emitter contact window, 2
9 is a base; contact window; 30 is an n+ type emitter contact region 31; 32 is a tungsten layer; 33 is an aluminum layer; 34 is a region where aluminum ore is thinly deposited; 35 is a collector. Wiring layer, 3
6 is an emitter wiring layer, 37 is a base wiring layer, aI is a transistor formation region, a! The ore collector contact formation area, a3 indicates the base formation area 〇1st g Figure 2

Claims (1)

[Claims] 1. A semiconductor device comprising a metal wiring layer having a two-layer structure in which a layer of aluminum or an alloy thereof is laminated on a layer of a high melting point metal or its silicide grown by chemical vapor deposition.