JPS594015A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To eliminate the need for forming the sloping of a stepped shape of an electrode window, and to prepar the device easily by forming a semiconductor region to an Si substrate, coating the whole surface containing said region with an insulating layer, forming the electrode window, setting up Si obtained by changing polycrystalline Si into a single crystal into the window, and coating Si with a metallic electrode in Al, etc. CONSTITUTION:Two thick field oxide films 4 are formed onto the P type Si substrate 1, the semiconductor regions 6, 7 are each diffused and formed positioned between said oxide films, and a gate electrode 9 is formed onto the substrate 1 exposed between these regions through a gate oxide film 8, and surrouned by an oxide film 10. The whole surface is coated with a PSG film 11, the electrode windows 12, 13 are each bored made corresponding to the regions 6, 7, and the polycrystalline Si layer 15 is grown on the whole surface containing the electrode windows. Laser beams 16 are irradiated to melt the layer 15, the layer 15 is pured into the windows 12, 13 while the regions 6, 7 exposed into the windows 12, 13 are used as crystalline seeds, and the layer 15 is changed into single crystals 17. The layer 15 except the single crystals is removed, and the upper ends of the single crystals 17 are coated with Al wiring 18.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly to improvements in contact between a metal electrode and a semiconductor region.

(2) Background of the technology In general, in semiconductor devices and their manufacturing methods, contacts between semiconductor regions formed on silicon substrates and metal electrodes (wirings) are made directly with aluminum (
Metal wiring such as A1) is vapor-deposited or spun.

Now, when forming an electrode window using PSG as an insulating layer and directly patterning Aβ into the electrode window, if the shape of the electrode window is not smooth, not only will the contact with the metal wiring be poor, but also the contact with the metal wiring will be poor. Because of the need to diffuse P into the substrate, a melt process was provided to solve the above two problems.

However, it is difficult to simultaneously control these two factors in one melt process due to problems such as the P concentration of PSG, and there has been a demand for a semiconductor device and a method for manufacturing the same that can easily control these two factors.

(3) Prior art and problems FIGS. 1 (Δ) to (1) show a conventional semiconductor device and its manufacturing method.

In FIG. 1 (Δ), ■ indicates, for example, a P-type silicon substrate, on which an initial silicon dioxide layer (SiO2) 2 is formed.

Next, as shown in (B), a silicon nitride (SiN) layer 3 is formed.
CV D (Chemical VaporDep)
The SiN layer 3 is selectively removed using photolithography according to a mask-like pattern, and as shown in (C), filled oxidation is performed to form the SiN layer 3.
A thick layer of silicon dioxide 1i (Si
02) is formed into about 7,000 eight genera.

Next, as shown in (D>), a gate oxide film 8 is formed leaving only the thick SiO2 layer, and a P-type dopant such as boron is ion-implanted (II) to pass through the top of the gate oxide film 8 and the boron is transferred to the silicon. introduced into the substrate.

Next, as shown in (E), the gate oxide film 8 in the source and drain semiconductor regions 6.7 is removed, and polycrystalline silicon 9 is deposited on the remaining gate oxide film 8 to diffuse N-type impurities. Deposit and pattern.

Next, as shown in (F), polycrystalline silicon 9 on gate oxide film 8 is oxidized to form silicon dioxide layer 1o.

Further, as shown in (G), P S G 11l is deposited on the entire surface to form electrode windows 12.13 above the source and drain semiconductor regions 6.7.

An enlarged side sectional view of this part is shown in (H), and the electrode window 12.
13, as shown in ('H), if the area from the PSG layer surface to the semiconductor regions 6 and 7 is formed steeply, the contact in the semiconductor area will be poor due to the sputtering of aluminum (Al) 14 formed in the next step (I). This results in poor compatibility between Al and metal wiring. Therefore, we added a melting process to the electrode window 12 of (H).
．． It is required to melt the PSG layer II to smooth the slope as shown by the dotted line at 13. However, in this melting process, when dissolving PSGii to smooth the slope, it is greatly influenced by the concentration of P contained in PSG, and it is difficult to obtain a smooth slope unless the concentration of P is increased, and if the concentration of P is increased, The wiring 14 of Δρ is corroded by P.

Furthermore, in order to have the function of diffusing P in the melting process, it is necessary to skillfully control the P concentration and melting time to determine the amount of P diffused into the diffusion layer and the shape of the melt, and the pH level must be strictly regulated. Since the melting time must be determined in accordance with the P concentration, it is difficult to specify these requirements.

(4) Purpose of the Invention In view of the above-mentioned conventional drawbacks, the present invention provides a method for controlling the depth of P in the diffusion layer without making the step shape of the electrode window slope-like, and without taking into account the step shape of the electrode window. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, which allow conditions to be set.

(5) Structure and object of the invention According to the present invention, a semiconductor region is formed on a silicon substrate, an electrode window is provided in an insulating layer formed on the semiconductor region, and polycrystalline silicon is formed in the electrode window. This is achieved by providing a semiconductor device characterized by providing crystallized silicon and providing a metal electrode such as aluminum through the single crystal silicon.

(6) Examples of the invention Examples of the present invention are shown in FIGS. 1A to 1G below.

(h), (i), and (j) will be explained.

(A) to (G) in FIG. 1 are the same as the conventional process, so redundant explanation will be omitted.
A polycrystalline silicon layer 15 (an enlarged view is shown in FIG. 1(h)) is deposited on the electrode window 12.13 formed in (i) by CVD or the like.
17) The thickness of the polycrystalline silicon layer 15 is approximately 4000-5000 people, and the polycrystalline silicon layer 15 is irradiated with a laser (continuous wave argon laser of 10 to 15 W) to melt the polycrystalline silicon layer, thereby forming the electrode window 12. At the same time as the polycrystalline silicon 15 melts and flows into the electrode window 13, single crystallization progresses from the surface in contact with the substrate 1, forming the electrode window 12 as shown in FIG. 1(j).
．． Single crystal silicon 17° 17 is formed within 13 .

Next, single crystal silicon 17. A7 through 17! Single crystal silicon 17. is formed by forming metal wiring 18 by sputtering or vapor deposition. 17 and Ajl! The metal wiring is alloyed and can make good contact.

In the above embodiment, the polycrystalline silicon 15 was explained as non-doped, but if doped crystalline silicon is used, the resistance can be selected to be low, and the single crystalline silicon 17 can be crystallized.
The resistance of the 17 part can be selected to be small, and the resistance value can be set to 15 to 1.
You can also choose around 7Ω.

Furthermore, if a melting process as in the prior art is performed before the metal wiring process, only the depth of P into the diffusion layer is controlled, and there is no need to take the step shape of the electrode window into consideration. Further, it is clear that the present invention can be applied not only to the MO3 type FET of the above-described embodiment but also to other semiconductor devices.

(7) Effects of the Invention As described above in detail, according to the present invention, the step shape of the electrode window is such that the single crystal silicon embedded in the electrode window formed in the insulating layer such as PSG is in direct contact with the An wiring. Since there is no need to set the slope to a slope, it is only necessary to control the depth of the P diffusion layer in the melting process, which makes the control extremely easy.

[Brief explanation of drawings]

(A) to (I) in FIG. 1 are side sectional views showing the manufacturing process of a conventional semiconductor device, (A) to (G) in FIG.
h) to (j) are side sectional views showing the manufacturing process of the semiconductor device of the present invention. DESCRIPTION OF SYMBOLS 1...Substrate, 2...Silicon dioxide layer, 4...
Filled oxide film, 62.7... Semiconductor region, 8.
...Gate oxide film, 11...PSG layer, 12.1
3... Electrode window, 15... Polycrystalline silicon layer, 1
7...Single crystal silicon. Patent Applicant: Fujitsu Limited 7 Procedural Amendment (Method) 1981, 10/λg Day 1, Case Description 1988 Patent Application No. 11314, 1, 2, Title of Invention: Semiconductor Device and Method for Manufacturing the Same 3, Amendment Relationship with the case of the patent applicant ” Ij Address 1015 Kamiodanaka, Nakahara-ku, Yozaki City, Kanagawa Prefecture Name Igo Co., Ltd. Representative Takuma Yamamoto 4, Agent 211 m <o44> 777-11
11 <extension 2630) Address: 1015 Kamiodanaka, Nakahara-ku, Yozaki-shi, Kanagawa Prefecture September 9, 1980 (Delivery date: September 28, 1980) M Book 1 Name of the invention Semiconductor device and its manufacturing method 2 , Claims (1) A semiconductor region is formed on a silicon substrate, an electrode window is provided in an insulating layer formed on the semiconductor region, silicon obtained by monocrystalizing polycrystalline silicon is provided in the electrode window, and the single crystal silicon is provided in the electrode window. A semiconductor device characterized in that a metal electrode made of aluminum or the like is provided through crystalline silicon. (2) forming a semiconductor region on a silicon substrate;
forming an insulating layer such as PSG on the semiconductor region;
A step of forming an electrode window in the insulating layer, a step of forming polycrystalline silicon in the electrode window, a step of irradiating the polycrystalline silicon with heat rays, and a step of forming a metal electrode on the monocrystalline silicon. 1. A method for manufacturing a semiconductor device, comprising the step of: 3. Detailed Description of the Invention (1) Technical Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly relates to improvements in metal electrodes and contacts on semiconductor regions. (2) Background of the technology In general, in semiconductor devices and their manufacturing methods, contacts between semiconductor regions formed on silicon substrates and metal electrodes (wirings) are made directly with aluminum (
A7! ＞ etc. are vapor-deposited or sputtered. Now, when forming an electrode window using PSG as an insulating layer and directly patterning Al in the electrode window, if the shape of the electrode window is not smooth, not only will the contact with the metal wiring be poor, but the contact with the metal wiring will be poor. Because of the need to diffuse P into the substrate, a melt process was provided to solve the above two problems. However, combining these two factors into one
Simultaneous control during the bolt process is PSG's P.
There has been a demand for a semiconductor device and a manufacturing method thereof that can easily control difficult problems such as concentration. (3) Prior art and problems FIGS. 1 (Δ) to (1) show a conventional semiconductor device and its manufacturing method. In FIG. 1(8), 2 indicates, for example, a P-type silicon substrate, on which an initial silicon dioxide layer (SiO2) 2 is formed. Next, as shown in (B), silicon nitride (SiN) [3
CV D (Chemical VaporDep)
The SiN layer 3 is selectively removed using photolithography according to a mask-like pattern, and as shown in (C), filled oxidation is performed to form the SiN layer 3.
A thick layer of silicon dioxide J* (Si
O2) is formed into about 7,000 eight genera. Next, as shown in (D), a gate oxide film 8 is formed leaving only the thick 5i02N, and a P-type dopant such as boron is ion-implanted (II) to pass through the gate oxide film 8 and the boron is transferred to the silicon substrate. will be introduced in Next, as shown in (E), the gate oxide film 8 in the source and drain semiconductor regions 6.7 is removed, and polycrystalline silicon 9 is placed on the remaining gate oxide film 8 to diffuse N-type impurities. is deposited to form a pattern. Next, as shown in (F), polycrystalline silicon 9 on gate oxide film 8 is oxidized to form silicon dioxide layer 10. Further, as shown in (G), a PSG layer 11 is deposited over the entire surface to form electrode windows 12 and 13 above the source and drain semiconductor regions 6 and 7. An enlarged side sectional view of this part is shown in (H), and the electrode window 12.
As shown in (H), if 13 is formed steeply from the PSG layer surface to the semiconductor regions 6 and 7, the contact in the semiconductor region will be poor due to sputtering of aluminum (A4) 14 formed in the next step (1). , impairs the compatibility between Aβ and metal wiring. Therefore, by adding a melting process, the electrode ° window 12 of (H) was added.
．． It is required to melt the PSG layer 11 and smooth the slope as shown by the dotted line at 13. However, this melting process is greatly influenced by the concentration of P contained in PSG when melting the PSG layer to create a smooth slope, and it is difficult to obtain a smooth slope unless the concentration of P is increased. The 8β wiring 14 is corroded by P. Furthermore, in order to have the function of diffusing P in the melting process, it is necessary to skillfully control the P1J1 degree and melt time to determine the amount of P diffused into the diffusion layer and the shape of the melt, and the P concentration must be strictly regulated. The melting time must be determined according to the degree of Pa, which has the disadvantage that it is difficult to specify these requirements. (4) Purpose of the Invention In view of the above-mentioned conventional drawbacks, the present invention provides a method for controlling the depth of P in the diffusion layer without making the step shape of the electrode window slope-like, and without taking into account the step shape of the electrode window. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, which allow conditions to be set. (5) Structure and object of the invention According to the present invention, a semiconductor region is formed on a silicon substrate, an electrode window is provided in an insulating layer formed on the semiconductor region, and polycrystalline silicon is formed in the electrode window. This is achieved by providing a semiconductor device characterized by providing crystallized silicon and providing a metal electrode such as aluminum through the single crystal silicon. (6) Embodiments of the Invention Examples of the invention are shown in (Δ) to (G) of FIG. 1 below. (J), (K), and (L) will be explained. (A) to (G) in Fig. 1 are the same as the conventional process, so redundant explanation will be omitted; however, as shown in (G), PSGJii
A polycrystalline silicon layer 15 (an enlarged view is shown in FIG. 1 (J)) is formed on the electrode window 12.
The electrode window 12 is formed by forming the polycrystalline silicon layer 15 to a thickness of 4,000 to 5,000 as described in K), and melting the polycrystalline silicon layer by irradiating a laser (10 to 15 W continuous wave argon laser) from above the polycrystalline silicon layer 15. ．． Polycrystalline silicon 1 in 13
5 melts and flows into the electrode window 12. At the same time, single crystallization progresses from the surface in contact with the substrate 1, and as shown in FIG. 1(L), the electrode window 12.
Single crystal silicon 17° 17 is formed within 13 . Next, 8L metal wiring 1 is passed through single crystal silicon 17.17.
By forming 8 by sputtering or vapor deposition, single crystal silicon 17. The metal wirings 17 and Aj2 are alloyed and can make good contact. In the above embodiment, the polycrystalline silicon 15 was explained as non-doped, but if doped crystalline silicon is used, the resistance can be selected to be low, and the single crystalline silicon 17 can be crystallized.
The resistance of the 17 part can also be selected to be small, with a resistance value of 15 to 17.
You can also choose around Ω. Furthermore, if a melting process as in the prior art is performed before the metal wiring process, only the depth of P into the diffusion layer is controlled, and there is no need to take the step shape of the electrode window into consideration. Further, the present invention also relates to M of the above-mentioned embodiment.
It is clear that the present invention can be applied not only to O3 type FETs but also to other semiconductor devices. (7) Effects of the Invention As described above in detail, according to the present invention, the step shape of the electrode window is such that the single crystal silicon embedded in the electrode window formed in the insulating layer such as PSG is in direct contact with the A1 wiring. Since there is no need to set the slope to a slope, it is only necessary to control the depth of the P diffusion layer in the melting process, thereby making the control extremely easy. 4. Brief description of the drawings (A) to (I) in FIG. 1 are side sectional views showing the manufacturing process of a conventional semiconductor device, (A) to (G) in FIG.
J) to (L) are side sectional views showing the manufacturing process of the semiconductor device of the present invention. ■...Substrate, 2...Silicon dioxide layer, 4...
Filled oxide film, 6, 7... semiconductor region, 8...
・Gate oxide film, 11...1) SG layer, 12
．． 13... Electrode window, I5... Polycrystalline silicon layer,
17...Single crystal silicon.

Claims (2)

[Claims] (1) A semiconductor region is formed on a silicon substrate, an electrode window is provided in the insulating layer formed on the semiconductor region, silicon obtained by converting polycrystalline silicon into a single crystal is provided within the electrode window, and the single crystal silicon is A semiconductor device characterized by having a metal electrode made of aluminum or the like interposed therebetween. (2) forming a semiconductor region on a silicon substrate;
forming an insulating layer such as PSG on the semiconductor region;
A step of forming an electrode window in the insulating layer, a step of forming polycrystalline silicon in the electrode window, a step of irradiating the polycrystalline silicon with heat rays, and a step of forming a metal electrode on the monocrystalline silicon. 1. A method for manufacturing a semiconductor device, comprising the step of: