JPS61174621A - Manufacture of semiconductor thin crystal - Google Patents
Manufacture of semiconductor thin crystalInfo
- Publication number
- JPS61174621A JPS61174621A JP60014051A JP1405185A JPS61174621A JP S61174621 A JPS61174621 A JP S61174621A JP 60014051 A JP60014051 A JP 60014051A JP 1405185 A JP1405185 A JP 1405185A JP S61174621 A JPS61174621 A JP S61174621A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- semiconductor
- protective layer
- semiconductor layer
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02488—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/02502—Layer structure consisting of two layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02672—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using crystallisation enhancing elements
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Materials Engineering (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、基板や誘電体層等の上に、半導体薄膜結晶を
製造する方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for producing semiconductor thin film crystals on substrates, dielectric layers, etc.
従来の技術
現在、例えば誘電体層上に形成されたゲルマニウム薄膜
結晶が、発光ダイオード、光複合素子、モノリシック複
合機能集積回路などの半導体素子の製造に利用され、ま
た、例えば誘電体層上に形成されたシリコン薄膜結晶が
、多層構造大規模集積回路などの半導体素子に利用され
ている。BACKGROUND OF THE INVENTION At present, thin film crystals of germanium, e.g. formed on a dielectric layer, are used in the production of semiconductor devices such as light emitting diodes, optical composite devices, monolithic multifunctional integrated circuits, etc. The resulting silicon thin film crystals are used in semiconductor devices such as multilayer large-scale integrated circuits.
そのような半導体薄膜結晶の１例を示すと第２図の如き
である。図示の半導体薄膜結晶は、ゲルマニウム薄膜結
晶であり、シリコンウェハ１０上に熱酸化ＳｉＯ２層１
２を形成したものを基板として、その熱酸化５ｉＯ７層
１２上にゲルマニウム層１４を形成し、更に、５ｉｎ２
のような上層保護層１６を形成して、膜構造を形成する
。An example of such a semiconductor thin film crystal is shown in FIG. The illustrated semiconductor thin film crystal is a germanium thin film crystal, and a thermally oxidized SiO2 layer 1 is formed on a silicon wafer 10.
2 was formed as a substrate, a germanium layer 14 was formed on the thermally oxidized 5iO7 layer 12, and then a 5in2
A film structure is formed by forming an upper protective layer 16 as shown in FIG.
この段階では、ゲルマニウム層１４は形成方法に依存し
て非晶質ないし小さい結晶粒（典型的な粒径は５０ｎｍ
）からなる微結晶状態になっている。そこで、その次
に、レーザビーム又は電子ビームもしくは線状ヒータを
用いた帯溶融法により、ゲルマニウム層１４の一部を溶
融し、溶融部分をゲルマニウム層面内で順次移動させ、
ゲルマニウムを大きい結晶粒もしくは単結晶でなる薄膜
層に結晶化させる。At this stage, the germanium layer 14 may be amorphous or have small crystal grains (typical grain size is 50 nm) depending on the formation method.
) is in a microcrystalline state. Therefore, next, a part of the germanium layer 14 is melted by a band melting method using a laser beam, an electron beam, or a linear heater, and the melted part is sequentially moved within the plane of the germanium layer.
Germanium is crystallized into a thin layer of large grains or single crystals.
しかし、このような方法でゲルマニウムを結晶□化する
場合、エネルギビームによる溶融法では、ビームパワー
、基板保持温度およびビームと基板間の相対速度（移動
速度）等を、また線状ヒータによる溶融法では、ヒータ
温度、基板温度、ヒータと基板間の相対速度等を、ゲル
マニウム層１４の上下の層１２．１６の材質に応じて一
定の狭い範囲に定めなければならない。However, when crystallizing germanium using such a method, the beam power, substrate holding temperature, relative speed (travel speed) between the beam and the substrate, etc. must be adjusted in the energy beam melting method, and in the melting method using a linear heater. In this case, the heater temperature, the substrate temperature, the relative speed between the heater and the substrate, etc. must be set within certain narrow ranges depending on the materials of the layers 12 and 16 above and below the germanium layer 14.
すなわち、上記方法によりゲルマニウム層の加熱のため
・に注がれるエネルギが上記範囲より小さいと、溶融お
よび充分な結晶成長が起こらない。That is, if the energy poured into the heating of the germanium layer by the above method is less than the above range, melting and sufficient crystal growth will not occur.
逆に、エネルギが大きすぎると、第３図に参照番号１８
を付して誇張して図示するように、溶融したゲルマニウ
ムが凝集を起こし、基板１２右よび上層保護層１６から
遊離し、薄膜結晶化が実現しない。On the other hand, if the energy is too large, reference numeral 18 is shown in FIG.
As shown in an exaggerated manner with , molten germanium aggregates and is separated from the right side of the substrate 12 and the upper protective layer 16, and thin film crystallization is not realized.
このような問題は、ゲルマニウム薄膜結晶の製造の場合
だけでな（、シリコン薄膜結晶などのほかの半導体薄膜
結晶の製造の場合にも発生する。Such problems occur not only in the production of germanium thin film crystals (but also in the production of other semiconductor thin film crystals, such as silicon thin film crystals).
そこで、従来、第４図のように、ゲルマニウム層１４の
上下に保護層となる層２０．２２を設けた構造によりゲ
ルマニウムの凝集を防止していた。その保護層２０およ
び２２の材料としては、タングステン等の高融点金属も
しくは窒化硼素、窒化アルミニウム等の絶縁物が使用さ
れていた。そして、広い範囲の結晶条件にわたって安定
に大面積薄膜結晶を得るためには、保護層２０．２２の
少なくとも一方にタングステン等の高融点金属を用いる
必要があった。Conventionally, as shown in FIG. 4, a structure in which protective layers 20 and 22 are provided above and below the germanium layer 14 was used to prevent germanium from agglomerating. As the material for the protective layers 20 and 22, a high melting point metal such as tungsten or an insulator such as boron nitride or aluminum nitride has been used. In order to stably obtain a large-area thin film crystal over a wide range of crystal conditions, it is necessary to use a high melting point metal such as tungsten for at least one of the protective layers 20 and 22.
発Ｈが解決しようとする問題点
しかしながら、保護層の一方に金属を用いると、素子間
の電気的結合には有利な反面、光結合素子等へ応用する
場合は、金属の高反射率のために光信号の透過が困難と
いう欠点があり、さらに電気的な素子間分離には不利と
いう欠点がある。Problems that H-emission attempts to solve However, it has the disadvantage that it is difficult to transmit optical signals, and it is also disadvantageous in terms of electrical isolation between elements.
また、タングステン等の高融点金属を保護層として使用
すると、半導体薄膜結晶化処理の際に表面荒れが生じて
凹凸ができるため、微細加工が困難になる。Furthermore, when a high melting point metal such as tungsten is used as a protective layer, surface roughness occurs during the semiconductor thin film crystallization process, resulting in unevenness, making microfabrication difficult.
そこで、本発明は、半導体薄膜結晶作成における上述の
欠点を除去して、保護層材料の選択の自由度が大きく、
微細加工上および素子応用上有利な構成とすることがで
きる半導体薄膜結晶を再現性良く製造できる方法を提供
せんとするものである。Therefore, the present invention eliminates the above-mentioned drawbacks in the production of semiconductor thin film crystals, and provides a greater degree of freedom in selecting the material for the protective layer.
It is an object of the present invention to provide a method for producing a semiconductor thin film crystal with good reproducibility, which can have a configuration advantageous in terms of microfabrication and device applications.
問題点を解′するための手段
そこで、本発明の発明者らは、上記した問題の原因を種
々研究した。その結果、その大きな原因は、半導体層と
保護層との層構造を形成する際に、保護層と半導体層と
の界面近傍に、酸素、炭素等の不純物が残留し、かかる
界面残留不純物が、半導体層と保護層との界面エネルギ
を増大させ、半導体溶融時にその溶融半導体の保護層に
対する濡れを減少させ、半導体の凝集を起こりやすくし
ているにあることが判明した。Means for Solving the Problems Therefore, the inventors of the present invention conducted various studies into the causes of the above-mentioned problems. As a result, the main reason for this is that impurities such as oxygen and carbon remain near the interface between the protective layer and the semiconductor layer when forming the layer structure of the semiconductor layer and the protective layer. It has been found that this method increases the interfacial energy between the semiconductor layer and the protective layer, reduces the wettability of the molten semiconductor to the protective layer when the semiconductor is melted, and makes it easier for the semiconductor to aggregate.
本発明は、かかる知見に基づいてなされたものであり、
半導体薄膜結晶の製造に右いて、半導体層の結晶化処理
に先立って、半導体層とそれに接する層との界面近傍に
イオン注入を行なうことにより、結晶化時の半導体の凝
集を防止することを特徴とするものである。The present invention was made based on this knowledge,
In the production of semiconductor thin film crystals, prior to crystallization of the semiconductor layer, ion implantation is performed near the interface between the semiconductor layer and the layer in contact with it to prevent agglomeration of the semiconductor during crystallization. That is.
五月
以上のような本発明による半導体薄膜結晶の製造方法に
おいて、保護層と半導体層との界面近傍にイオン注入を
行なうと、酸素、炭素等の界面残留不純物が、注入され
たイオンからエネルギを得て界面以外の場所に変位する
（ノックオン現象）。In the method of manufacturing a semiconductor thin film crystal according to the present invention as described above, when ions are implanted near the interface between the protective layer and the semiconductor layer, impurities remaining at the interface such as oxygen and carbon absorb energy from the implanted ions. and is displaced to a location other than the interface (knock-on phenomenon).
このように界面残留不純物を界面以外の場所に変位させ
、膜中に散乱させると、界面エネルギが減少し、濡れが
増大し、従って、半導体が溶融したときの半導体の凝集
が抑制される。Displacing residual interfacial impurities to locations other than the interface and scattering them throughout the film reduces interfacial energy, increases wetting, and thus suppresses agglomeration of the semiconductor when it is melted.
更に、イオン注入により界面近傍の組成は、注入イオン
の存在、保護層右よび半導体層のノックオン現象、注入
に伴ない導入された欠陥等の複合的な作用のため、注入
量に応じた変動を引起す。Furthermore, due to ion implantation, the composition near the interface changes depending on the implantation amount due to the combined effect of the presence of implanted ions, the knock-on phenomenon of the protective layer and semiconductor layer, and defects introduced with implantation. cause
そのため、半導体層と保護層を構成する原子は界面付近
で相互に混合する方向に組成変動が起こり、付着性を向
上させていると考えられる。Therefore, it is thought that the compositional changes occur in the direction that the atoms constituting the semiconductor layer and the protective layer are mixed with each other near the interface, improving adhesion.
以上のような作用があいまって上記イオン注入により、
結晶化処理の際の加熱温度や基板温度に厳しい条件を要
求されずに、単導体の凝集は効果的に防止され、再現性
良く薄膜結晶が実現される。Due to the combination of the above effects and the above ion implantation,
Agglomeration of single conductors is effectively prevented and thin film crystals can be realized with good reproducibility without requiring strict conditions for heating temperature or substrate temperature during crystallization treatment.
かくして、保護層として、タングステン等の高融点金属
を使用する必要はなくなり、保護層材料の選択の自由度
が大きくなる。従って、保護層として半導体の酸化物な
どの加工が容易な材料を使用することにより、微細加工
が容易になり、また、透明な材料を保護層として使用す
ることにより、光結合素子なども作ることだでき、半導
体薄膜結晶を利用して実現できる素子の範囲を広くする
ことごてきる。Thus, it is no longer necessary to use a high melting point metal such as tungsten for the protective layer, and the degree of freedom in selecting the material for the protective layer is increased. Therefore, by using a material that is easy to process, such as a semiconductor oxide, as a protective layer, microfabrication becomes easier, and by using a transparent material as a protective layer, it is possible to create optical coupling devices. This makes it possible to expand the range of devices that can be realized using semiconductor thin film crystals.
１１遭
以下、添付図面を参照して本発明による半導体薄膜結晶
の製造方法の実施例を説明する。Embodiments of the method for manufacturing a semiconductor thin film crystal according to the present invention will be described below with reference to the accompanying drawings.
第１図は、本発明の方法により製造されるゲルマニウム
薄膜結晶の１例を示すものであり、第１図（ａ）は、そ
の層構造を示す概略断面図であり、第。FIG. 1 shows an example of a germanium thin film crystal produced by the method of the present invention, and FIG. 1(a) is a schematic cross-sectional view showing its layer structure.
１図（ハ）は、深さ方向でのイオン注入濃度を示す濃度
分布図である。FIG. 1(C) is a concentration distribution diagram showing the ion implantation concentration in the depth direction.
図示の実施例は、シリコンウェハ１０上に厚さ。The illustrated embodiment is based on a silicon wafer 10.
３００ｎｍ熱酸化３１０２層１２を形成したものを基板
とし、その３ ｉ ０２層１２の上に、下層保護層３０
として窒化硼素を厚さ１１００ｎにプラズマ化学気相堆
積法により形成した。A substrate on which a 300 nm thermally oxidized 3102 layer 12 is formed is used, and a lower protective layer 30 is formed on the 3i02 layer 12.
As a substrate, boron nitride was formed to a thickness of 1100 nm by plasma chemical vapor deposition.
次に、ゲルマニウムを厚さ２００ｎｍに蒸着して半導体
層１４を形成し、更に、上層保護層３２として窒化硼素
を厚さ６０ｎｍにプラズマ化学気相堆積法により形成し
た。Next, germanium was deposited to a thickness of 200 nm to form the semiconductor layer 14, and boron nitride was further formed to a thickness of 60 nm as the upper protective layer 32 by plasma chemical vapor deposition.
その後、上層保護層３２側からシリコンイオンの注入を
行なった。そのイオン注入は、第１図（ハ）に参照番号
ａで示すように下層保護層３０と半導体層１４との界面
付近に、シリコン原子の分布のピークが来るようにエネ
ルギを調整して行なった（注入ａ）。次に、上層保護層
３２と半導体層１４との界面付近にピークが来るように
注入すを行なった。Thereafter, silicon ions were implanted from the upper protective layer 32 side. The ion implantation was performed by adjusting the energy so that the peak of the distribution of silicon atoms was located near the interface between the lower protective layer 30 and the semiconductor layer 14, as indicated by reference number a in FIG. 1(c). (Injection a). Next, implantation was performed so that the peak was located near the interface between the upper protective layer 32 and the semiconductor layer 14.
イオン加速エネルギ、注入量は、注入ａ七それぞれ３４
０Ｋｅ Ｖ、５ ＸＩＯ”ｃｍ−”、注入すでそれぞれ
１００Ｋｅ Ｖ、２ Ｘ１０１５ｃｍ−’であった。The ion acceleration energy and implantation amount were 34 for each implantation a7.
0 Ke V, 5 XIO"cm-", the injection was 100 Ke V, 2 X 1015 cm-', respectively.
そして、イオン注入後、線状ヒータを用いた帯溶融法に
よりゲルマニウムを結晶化した。After ion implantation, germanium was crystallized by a band melting method using a linear heater.
イオン注入を行わない場合、本実施例の膜構造では半導
体層１４の全面にわたって薄膜結晶を実現することは困
難であったが、上記イオン注入を行なうことにより結晶
化条件の精密な制御なしに容。Without ion implantation, it would be difficult to achieve a thin film crystal over the entire surface of the semiconductor layer 14 with the film structure of this example. .
易に薄膜結晶が得られた。Thin film crystals were easily obtained.
なお、保護層材料は、本実施例の窒化硼素に限定される
ものではなく、半導体層１４を構成する半導体材料の溶
融温度（例えば、ゲルマニウムでは約９５０℃）で溶融
も半導体との合金化もしない安定な物質であれば良い。The material for the protective layer is not limited to boron nitride in this embodiment, but can be melted or alloyed with the semiconductor at the melting temperature of the semiconductor material constituting the semiconductor layer 14 (for example, about 950° C. for germanium). It is fine as long as it is a stable substance that does not.
従って、基板がこの条件を満たすものであるならば、下
層保護層を省略して、基板上に直接半導体層を形成して
もよい。Therefore, if the substrate satisfies this condition, the lower protective layer may be omitted and the semiconductor layer may be formed directly on the substrate.
そこで、保護層としてＱ ｅ Ｏ２・Ｓ ｔ Ｏ２ガラ
スを用いたところ、同様のイオン注入効果が確認できた
。Therefore, when Q e O2·S t O2 glass was used as the protective layer, a similar ion implantation effect was confirmed.
また、凝集防止に必要な最小注入量は、保護層材料に依
存している。窒化硼素・Ｇ ｅ Ｏ２・３１０２ガラス
等では、１０′ｓａｍ−”オーダの比較的小さい注入量
で効果が認められるのに対し、半導体集積回路で一般的
に使用されている絶縁体材料である５１０２・窒化珪素
等では、１ｏ１６ｃｍ−２オ一ダ以上と、最小注入量が
比較的大きい。Also, the minimum dosage required to prevent agglomeration is dependent on the protective layer material. Boron nitride, G e O2, 3102 glass, etc. are effective with a relatively small implantation dose on the order of 10'sam-'', whereas 5102, an insulator material commonly used in semiconductor integrated circuits, is effective. - For silicon nitride, etc., the minimum implantation amount is relatively large, being more than 1016 cm-2 orders of magnitude.
いずれにしても、多種類の保護層材料にわたって、本発
明のイオン注入の効果は認められた。In any case, the effects of the ion implantation of the present invention were observed across a wide variety of protective layer materials.
更に、イオン注入は、第１図ら）で説明した本実施例の
方法に限定されるのではなく、例えば、保護層３０及び
３２の材料をそれぞれ適宜選択することにより、注入ａ
のみを行なえば注入すを行なわなくても凝集防止を達成
できる。その理由の第１は、上層保護層自体が半導体層
と付着力が大きい場合は、注入すを行わなくても、結晶
化処理の際に半導体層の凝集は発生しない。理由の第２
は、注入すを行うと、その注入イオンは、上層保護層と
半導体層との間の界面も通過し、その通過の際、界面残
留不純物をほかに変位させ、注入イオンの到達点ぼどで
はないが、界面エネルギを減少させ、また、界面付近の
組成変動などにより付着力を向上させることができる。Furthermore, the ion implantation is not limited to the method of this embodiment described in FIG.
Agglomeration prevention can be achieved by only performing injection without injection. The first reason is that if the upper protective layer itself has strong adhesion to the semiconductor layer, no agglomeration of the semiconductor layer will occur during the crystallization process even if implantation is not performed. Second reason
When implantation is performed, the implanted ions also pass through the interface between the upper protective layer and the semiconductor layer, and as they pass through, they displace the remaining impurities at the interface, causing the implanted ions to reach However, it is possible to reduce the interfacial energy and improve adhesion by changing the composition near the interface.
また、半導体層１４が薄い場合には、単一の注入工程で
半導体層１４と保護層３０．３２との上下の両方の界面
にイオン注入することができ、上記効果が同様に得られ
る。Further, when the semiconductor layer 14 is thin, ions can be implanted into both the upper and lower interfaces between the semiconductor layer 14 and the protective layer 30, 32 in a single implantation step, and the above effect can be obtained similarly.
注入イオン種も本実施例のシリコンに限定されるもので
はなく、上記説明した界面効果をもたらすに充分な量で
あればすべてのイオン種で有効である。その理由は、本
発明はイオン注入の物理的効果を利用しているためであ
る。例えば、硼素イオンを注入イオン種として使用した
ところ、同様の効果が確認された。従って、半導体薄膜
結晶中へのドーピングと連結させて、本発明の凝集防止
用イオン注入を同時に行なうことも可能である。The implanted ion species is not limited to the silicon used in this embodiment, but any ion species is effective as long as the amount is sufficient to bring about the interface effect described above. This is because the present invention utilizes the physical effects of ion implantation. For example, similar effects were confirmed when boron ions were used as the implanted ion species. Therefore, it is possible to perform the aggregation prevention ion implantation of the present invention simultaneously in conjunction with doping into the semiconductor thin film crystal.
ただし、注入イオン種の選択は、注入イオンが半導体層
に悪影響をもたらすかどうか、そして、所期の深さまで
注入するに必要な加速電圧はどうかにより、行うことが
好ましい。However, it is preferable to select the implanted ion type depending on whether the implanted ions have an adverse effect on the semiconductor layer and the accelerating voltage required for implantation to a desired depth.
また、半導体層１４も、ゲルマニウムに限定されるもの
ではなく、例えばシリコンなどのほかの第■族単体半導
体や、ヒ化ガリウム、燐化インジウムなどの第■−■族
化合物半導体でも同様な効果が得れる。Further, the semiconductor layer 14 is not limited to germanium, and similar effects can be obtained by using other Group Ⅰ elemental semiconductors such as silicon, or Group Ⅰ-■ compound semiconductors such as gallium arsenide and indium phosphide. You can get it.
更に、基板も、シリコンウェハに限らず、他の半導体基
板でも、金属基板でも、絶縁基板でもよい。そして、そ
の基板上に絶縁層を設けていてもいなくてもよく、また
、基板上に金属層を設けていてもいなくてもよい。Further, the substrate is not limited to a silicon wafer, but may be another semiconductor substrate, a metal substrate, or an insulating substrate. Then, an insulating layer may or may not be provided on the substrate, and a metal layer may or may not be provided on the substrate.
本発明は、化合物半導体薄膜結晶成長への応用展開も期
待できる。例えば、上層保護層を除去したゲルマニウム
層上にヒ化ガリウムを成長させることにより安価な太陽
電池製造が可能である。また、ヒ化ガリウム発光素子と
シリコンウェハ内に形成した受光素子を組合わせたモノ
リシック・フィトカップラ素子が実現できる。更に、光
や電子による能動機能を混成した多層構造集積回路の作
成等に利用できる。The present invention can also be expected to be applied to compound semiconductor thin film crystal growth. For example, inexpensive solar cells can be manufactured by growing gallium arsenide on a germanium layer from which the upper protective layer has been removed. Furthermore, a monolithic phytocoupler element that combines a gallium arsenide light-emitting element and a light-receiving element formed within a silicon wafer can be realized. Furthermore, it can be used to create multilayer integrated circuits that combine optical and electronic active functions.
発明の詳細
な説明したように、本発明による半導体薄膜結晶の製造
方法によれば、半導体薄膜結晶に対する保護層として種
々の材料を使用しても、半導体薄膜結晶化時に凝集を防
止することができる。例えば、ＳｉＯ□のように微細加
工技術上開発の進んでいる材料を介して、半導体薄膜結
晶を作成することにより、高集積度の半導体素子を製造
することできる。また、素子応用上の必要に応じて絶縁
体上あるいは金属上に薄膜結晶を同時に再現性良く作成
することもでき、更に、透明材料を使用することにより
光素子も製造することができる。As described in detail of the invention, according to the method of manufacturing a semiconductor thin film crystal according to the present invention, even if various materials are used as a protective layer for the semiconductor thin film crystal, agglomeration can be prevented during semiconductor thin film crystallization. . For example, by creating a semiconductor thin film crystal using a material such as SiO□, which is well-developed in terms of microfabrication technology, a highly integrated semiconductor element can be manufactured. Furthermore, thin film crystals can be simultaneously created on insulators or metals with good reproducibility as required for device applications, and optical devices can also be manufactured by using transparent materials.
第１図は、本発明の詳細な説明図であり、第１図（ａ）
は膜の積層構造を示す概略断面図であり、第１図（ハ）
は注入された原子濃度の分布を示す説明図である。
第２図は、従来のゲルマニウム薄膜結晶の製造方法にお
ける膜積層構造を示す概略断面図である。
第３図は、第１図の構成で溶融加熱した結果、ゲルマニ
ウムが凝集を引起した状態を示す誇張断面図である。
第４図は、ゲルマニウムの凝集防止のためゲルマニウム
層の上下に保護層を配した従来の構成を示す概略断面図
である。
〔主な参照番号〕
１０・・シリコンウェハ、
１２・・熱酸化５ｉｎ２層、
１４・・ゲルマニウム層、
１６・・上層保護層
１８・・凝集したゲルマニウム、
２０・・下層保護層、
２２・・上層保護層、
３０・・下層保護層、
３２・・上層保護層FIG. 1 is a detailed explanatory diagram of the present invention, and FIG. 1(a)
is a schematic cross-sectional view showing the laminated structure of the membrane, and FIG.
FIG. 2 is an explanatory diagram showing the distribution of the concentration of implanted atoms. FIG. 2 is a schematic cross-sectional view showing a film stack structure in a conventional germanium thin film crystal manufacturing method. FIG. 3 is an exaggerated cross-sectional view showing a state in which germanium has agglomerated as a result of melting and heating with the configuration shown in FIG. FIG. 4 is a schematic cross-sectional view showing a conventional structure in which protective layers are provided above and below a germanium layer to prevent agglomeration of germanium. [Main reference numbers] 10...Silicon wafer, 12...Thermal oxidation 5in2 layer, 14...Germanium layer, 16...Upper layer protective layer 18...Agglomerated germanium, 20...Lower layer protective layer, 22...Upper layer Protective layer, 30...lower protective layer, 32...upper protective layer
Claims (4)
の溶融温度で安定な材料からなる第１の保護層を前記半
導体層上に形成する工程と、前記基板と前記半導体層の
界面近傍と、前記半導体層と第１の保護層の界面近傍と
の両方もしくは一方にイオン注入を行なう工程と、 前記半導体層を加熱処理して該半導体層を結晶化せしめ
る工程と、 を具備することを特徴とする半導体薄膜結晶の製造方法
。(1) A step of forming a semiconductor layer on a substrate, a step of forming a first protective layer made of a material stable at the melting temperature of the semiconductor layer on the semiconductor layer, and an interface between the substrate and the semiconductor layer. and a step of performing ion implantation into both or one of the vicinity and the vicinity of the interface between the semiconductor layer and the first protective layer, and the step of heat-treating the semiconductor layer to crystallize the semiconductor layer. A method for manufacturing a semiconductor thin film crystal characterized by:
体基板、絶縁性基板、または、金属基板であることを特
徴とする特許請求の範囲第（１）項記載の半導体薄膜結
晶の製造方法。(2) Manufacturing a semiconductor thin film crystal according to claim (1), wherein the substrate is a semiconductor substrate, an insulating substrate, or a metal substrate that is stable at the melting temperature of the semiconductor layer. Method.
の溶融温度で安定な第２の保護層を予め設けることを特
徴とする特許請求の範囲第（１）項または第（２）項記
載の半導体薄膜結晶の製造方法。(3) Claims (1) or (2) characterized in that a second protective layer that is stable at the melting temperature of the semiconductor substrate is provided in advance between the substrate and the semiconductor layer. A method for producing a semiconductor thin film crystal as described in 1.
−Ｖ族化合物半導体で形成することを特徴とする特許請
求の範囲第（１）項から第（３）項までのいずれかに記
載の半導体薄膜結晶の製造方法。(4) The semiconductor layer is a group IV single semiconductor or a group III semiconductor.
-The method for manufacturing a semiconductor thin film crystal according to any one of claims (1) to (3), characterized in that it is formed from a group V compound semiconductor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60014051A JPS61174621A (en) | 1985-01-28 | 1985-01-28 | Manufacture of semiconductor thin crystal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60014051A JPS61174621A (en) | 1985-01-28 | 1985-01-28 | Manufacture of semiconductor thin crystal |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61174621A true JPS61174621A (en) | 1986-08-06 |
Family
ID=11850290
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60014051A Pending JPS61174621A (en) | 1985-01-28 | 1985-01-28 | Manufacture of semiconductor thin crystal |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61174621A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0308166A2 (en) * | 1987-09-18 | 1989-03-22 | Xerox Corporation | Polycrystalline film formation |
| JPH02101735A (en) * | 1988-10-11 | 1990-04-13 | Agency Of Ind Science & Technol | Manufacture of semiconductor single crystal layer |
| GB2244284A (en) * | 1990-05-02 | 1991-11-27 | Nippon Sheet Glass Co Ltd | A method of manufacturing a polycrystalline semiconductor film by ion implantation |
| KR100448714B1 (en) * | 2002-04-24 | 2004-09-13 | 삼성전자주식회사 | Insulating layer in Semiconductor Device with Multi-nanolaminate Structure of SiNx and BN and Method for Forming the Same |
| JP2011171548A (en) * | 2010-02-19 | 2011-09-01 | Nippon Telegr & Teleph Corp <Ntt> | Method of manufacturing semiconductor device |
| CN109791876A (en) * | 2016-05-12 | 2019-05-21 | 环球晶圆股份有限公司 | Hexagonal boron nitride is directly formed on silicon substrate dielectric |
-
1985
- 1985-01-28 JP JP60014051A patent/JPS61174621A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0308166A2 (en) * | 1987-09-18 | 1989-03-22 | Xerox Corporation | Polycrystalline film formation |
| JPH02101735A (en) * | 1988-10-11 | 1990-04-13 | Agency Of Ind Science & Technol | Manufacture of semiconductor single crystal layer |
| GB2244284A (en) * | 1990-05-02 | 1991-11-27 | Nippon Sheet Glass Co Ltd | A method of manufacturing a polycrystalline semiconductor film by ion implantation |
| GB2244284B (en) * | 1990-05-02 | 1993-11-03 | Nippon Sheet Glass Co Ltd | A method of manufacturing a polycrystalline semiconductor film |
| KR100448714B1 (en) * | 2002-04-24 | 2004-09-13 | 삼성전자주식회사 | Insulating layer in Semiconductor Device with Multi-nanolaminate Structure of SiNx and BN and Method for Forming the Same |
| JP2011171548A (en) * | 2010-02-19 | 2011-09-01 | Nippon Telegr & Teleph Corp <Ntt> | Method of manufacturing semiconductor device |
| CN109791876A (en) * | 2016-05-12 | 2019-05-21 | 环球晶圆股份有限公司 | Hexagonal boron nitride is directly formed on silicon substrate dielectric |
| CN109791876B (en) * | 2016-05-12 | 2023-08-15 | 环球晶圆股份有限公司 | Direct formation of hexagonal boron nitride on silicon-based dielectrics |
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