JPS59155951A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a three-dimensional LSI with a positive connection by interposing an inter-layer insulating film between an upper layer and a lower layer with circuit elements, boring a through-hole to the upper layer and the inter-layer insulating film, inserting a vertical type wiring into the through-hole and connecting the elements of the upper layer and the lower layer by the wiring while surrounding the wiring of an upper-layer penetrating section by an insulating film when ICs are formed in laminated structure. CONSTITUTION:When an Si substrate 1 as a lower layer to which source-drain regions 3 are formed and an Si substrate with the same structure as said substrate 1 are superposed, an inter-layer insulating film 5 is interposed between both substrates. A bored section 6 penetrating an upper layer and the insulating film 5 is bored, a vertical wiring 9 is inserted into the bored section, and the lower end section of the wiring 9 is brought into contact with the surface of the regions 3. An insulating film 10 surrounding the wiring 9 is shaped to the penetrating section of the upper layer of the upper section of the wiring 9 to previously interrupt a contact with the upper layer, and the upper end of the wiring 9 and a region formed to the upper layer are connected by a wiring 11 in Al, etc. Accordingly, the wiring of the upper and lower layers is connected positively.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical field of the invention The present invention is 5th! The present invention relates to a method of forming a semiconductor integrated circuit having an RIG structure.・ (b) Background of the technology Currently, the integration of integrated circuits (ICs and LSIs) is increasing rapidly and moving towards three-dimensional structures. For example, 'd?N is also widely used. Relico / (hereinafter referred to as S)
i) Semiconductor (for that matter, the current two-dimensional structure is made up of silicon dioxide (hereinafter referred to as 5iOz) layer, silicon nitride (hereinafter referred to as 5iOz) layer)
N+) layer, phosphosilicate glass (PSG) layer, or other heat-resistant insulating layer, and then a non-single-crystal St layer such as polycrystalline St or amorphous Sl is formed on top of this, and this is fused with a single layer such as by laser irradiation. After crystallization, an LSI is formed on the crystal. Here, the circuits in the upper and lower layers are connected through vertical wiring, but problems such as disconnection and impurity contamination are likely to occur during this formation. The present invention relates to a three-dimensional LSI structure that does not cause such failures.

(c) Traditional technology and problems The conventional method for forming three-dimensional LSIs, for example when forming a MOS-IC on a St semiconductor substrate, is based on the hole conductivity type (hereinafter referred to as P) as shown in Figure 1. The source (S) 2 and drain (to) 3 regions of electron conduction type (hereinafter referred to as N type) formed by impurity diffusion on the Sl substrate 1 of type
G) A large number of transistors are arranged in a matrix, sandwiching MOS transistors 4 and 4, which are made of impurity-doped polycrystalline S1 or molybdenum silicide
A normal LSI has a three-dimensional structure in which p-circuits are connected by conductor lines such as the following. Conversely, a P-type diffusion region is provided on the N-type Si substrate 1 to provide a source (s).
)2 and drain )3 may be formed in some cases.

Next, to make these LSIs into a three-dimensional structure, add 5
An interlayer insulating layer 5 is formed by applying an insulating material such as i02 by chemical vapor reaction (CVD), and then photolithography is used to form a part 6 at the position where vertical wiring is to be formed. form.

Next, polycrystalline Sl or amorphous Si is deposited alternately over the entire surface by sputtering or vacuum evaporation, and the upper Si is melted and recrystallized by irradiation with an argon ion (Ar'') laser. A crystal substrate °7 is produced.By this heat treatment by laser irradiation, the polycrystalline or amorphous St deposited in the part 6 is also turned into a single crystal, but at this time, as shown in FIG. 6, the upper Si crystal substrate 7 may cave in and the upper St crystal layer 7 and the vertical wiring section may become insulated. Also, crystallization progresses ideally and the upper St crystal layer 7 is relatively Even if it could be formed flat, the M formed on the Si substrate 1 as shown in FIG.
The drain region 8 of the MOS) transistor formed on the drain region 3 of the OS) transistor and the upper Sl crystal layer 7
When the conductivity types of the drain regions are different, that is, when the lower drain region 3 is N type and the drain region 8 to be formed in the upper layer 7 is P type. , the impurity element in the lower drain region 3 diffuses to the upper part through the vertical wiring 9, and even if the upper and lower elements are of the same type, the lower impurity diffuses into the channel region of the upper MOS transistor. There was a problem in that it diffused and caused poor characteristics.

(d) Object of the Invention An object of the present invention is to provide a method for forming vertical wiring for a three-dimensional LSI that does not involve step-cutting of an upper crystal layer or diffusion of impurities from a lower substrate.

(e) Structure of the Invention The purpose of the present invention is to form a vertical hole at the connection position of the upper and lower circuits when further forming an integrated circuit on the integrated circuit via an insulating layer, and to seal the vertical hole with a conductive material. After forming the vertical wiring, a non-single-crystal layer is deposited on the upper layer, and only the periphery of this vertical bale is selectively oxidized and insulated.Next, the non-single-crystal layer is made into a single crystal, and then the upper layer is This can be achieved by forming an integrated circuit.

(f) Embodiments of the Invention The present invention solves the conventional problems by performing the formation of vertical wiring for a three-dimensional LSI separately from the formation of the upper Si crystal layer.

In the present invention, the holes provided to connect the conductive circuits of the upper and lower LSIs are completely filled with a conductive material such as polycrystalline St or silicide doped with impurities, and the method for this is CVD, sputtering or Either deposit a conductive material on the surface of the substrate using vacuum evaporation, seal the surface, and then polish the substrate surface, or perform controlled etching to remove the conductive material on the surface of the substrate. Any method may be used, such as leaving only a small portion, performing laser irradiation and pouring a conductive material, or selectively epitaxially growing Sl on the exposed portion. That is, in the case of the last method, the first
As is clear from the figures and FIG. 2, since the bottom of the Komei region is an SL substrate, if epitaxial growth is performed, Si crystal can be grown only on the Komei region. In this way, after forming the vertical wiring 9 on the part, Koumei deposits polycrystalline Si or amorphous Si on the surface by CVD or sputtering, and then forms the vertical wiring 9 as shown in FIG. If the slight periphery 10 of the upper part of the wiring part 10 is selectively oxidized and converted into a SiO□ film and insulated, the gold surface is irradiated with a laser beam to form a single crystal, thereby preventing depression in the vertical wiring part 9 and diffusing impurity elements. can also be suppressed. In this case, since the vertical wiring section 9 is insulated from the upper S1 crystal layer 7, it is necessary to connect the wiring using an aluminum vapor deposited film or the like. In the embodiments so far, the formation of the vertical wiring 9 and the formation of the upper S1 crystal layer 7 are performed separately, but they can be performed simultaneously.

That is, as shown in FIG. 4, when a vertical wiring 9 is to be formed on a diffusion region of a semiconductor element formed on a Si crystal substrate 1, for example, an N-type drain 3, a 5.
A hole is made in the glabellar insulating layer 5 made of i02, and then polycrystalline Si or amorphous St is formed on the entire surface of the hole including the portion 6. After that, the St layer 10 around the hole is selectively oxidized. Then, by changing to S i O 2 and performing laser irradiation, the entire surface including the portion 6 is made into a single crystal. In this case, Kongming is part 6
Although there is a possibility that depression or impurity contamination may occur in the vertical wiring 9 formed in the cylindrical S i O++ made by selective oxidation,
Since it is confined, there is no influence on the outside.

Next, the vertical wiring 9 thus formed and the semiconductor element formed on the upper Si crystal substrate are formed into conductor wiring 11 using an aluminum vapor deposition film, etc., thereby forming a semiconductor device free from impurity contamination. .

(g) Effects of the Invention In the present invention, when forming a three-dimensional LSI, the formation of a contact hole that connects the upper and lower layers is performed separately from the formation of the upper Si crystal layer. This eliminates problems caused by impurity diffusion and improves the yield during production.

[Brief explanation of the drawing]

3 is a sectional view showing a state in which the periphery of the upper vertical wiring according to the present invention is insulated, and FIG. 4 is a sectional view showing an embodiment of the present invention. In the figure, 1 is a silicon crystal substrate, 5 is an interlayer insulating layer, and 6 is a silicon crystal substrate.
7 is the upper silicon crystal layer, and 9 is the vertical wiring. 'F-January~≦ Hirosu last year 7 1\-j -X/J

Claims (1)

[Claims] In a three-dimensional circuit consisting of a plurality of semiconductor layers having circuit elements stacked below and connected by vertical wiring, the circuit element region of the upper semiconductor layer and the upper part of the vertical wiring are insulated through an absolute R layer. 1. A semiconductor device characterized in that the circuit element is separated by a layer, and the circuit element and the upper part of the vertical wiring are connected by a conductor provided on the surface.