JPH0626244B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device, and more particularly to the structure of a MIS type semiconductor device.

(Prior Art and its Problems) A MIS type semiconductor device formed on a semiconductor film provided on an insulator, a MIS type semiconductor device having a so-called SOI (Semiconductor on Insalator) structure, has a junction capacitance higher than that of a conventional MIS type semiconductor device. In addition, since the wiring capacitance is small and element isolation is complete and simple, high-speed large-scale integrated circuits (LSI)
It is said that the semiconductor device is suitable for. For example, Electronic Materials, pages 54-104, January 1982, published by Motoo Nakano and Nobuo Sasaki, "SOS / CMOS".
In the "device", the SOS (Sil
A structure such as a CMOS type semiconductor device having an icon on Sapphire structure is shown. The SOS structure is an example of the SOI structure, and a plan view of a CMOS inverter circuit element corresponding to this is shown in FIG. 3 (b).

Here, 1 is a sapphire substrate, 2 is an oxide film, 3 is an N type region, 4 is a P type region, 5 is a P ^{+ type} source / drain region,
Reference ^numeral 6 is an N ⁺ source / drain region, 7 is P ^{+ type} polycrystalline silicon, 8 is N ^{+ type} polycrystalline silicon, and 9 is an Al wiring.

However, in recent years, M formed on a conventional semiconductor substrate
Even in the IS type semiconductor device, a fine element isolation technique has been developed, and it has become possible to achieve the same degree of integration as the MIS type semiconductor device having the SOI structure. On the other hand, recently MI with SOI structure
A structure has been proposed for further improving the degree of integration in an S-type semiconductor device. Figures 4 (a) and (b) show the improved SO.
It is a top view corresponding to a schematic sectional view of a CMOS inverter circuit element of S structure. Here, 1 to 9 are the same as 1 to 9 in FIG. In this structure, the drains of the NMOS transistor and the PMOS transistor are joined to each other, and an Al wiring is performed after forming an opening so that at least the junction boundary is included in the drain region of either the N ^{+ type} or the P ^{+ type.} The feature is that an ohmic connection can be obtained. According to this structure, it is possible to further integrate the inverter circuit element using the MIS type semiconductor device having the SOI structure in the related art.

However, as the size of the transistor is reduced in order to achieve a higher-speed LSI, the degree of integration will be limited even in the case of the semiconductor device having the improved SOI structure. That is, if the area of the contact hole is reduced as the transistor size is reduced, the resistance of the contact hole is increased, which becomes a factor that hinders the speedup of the LSI. Therefore, there is no choice but to limit the reduction ratio of the area of the contact hole. Therefore, in the case of the semiconductor device having the improved SOI structure, the degree of integration is limited by the area of the contact hole and further integration is impossible. Becomes

As described above, the conventional semiconductor device has a high-speed and highly integrated LS.
There is a clear limit to the formation of I and there will be serious problems in the future.

(Object of the Invention) An object of the present invention is to provide a structure of an MIS type semiconductor device having an SOI structure in which the above problems are eliminated.

(Structure of the Invention) According to the present invention, in a complementary MIS type semiconductor device formed on a semiconductor film provided on an insulator, metal or metal is added so as to include the drain regions of the opposite conductive type MIS type transistors. A semiconductor compound layer is formed, and a semiconductor gate of the next stage is connected to the upper portion of the layer, so that the drain region of the opposite conductivity type MIS transistor and the gate are ohmic-connected. A semiconductor device that can be obtained is obtained.

(Example) First, an example of an MIS type semiconductor device having an SOI structure according to the present invention will be described.

1 (a) and 1 (b) are a schematic cross-sectional view and a plan view of an inverter circuit element formed by this structure as one example of the MIS type semiconductor device according to the present invention. In the figure, 3 to 6 are the same as 3 to 6 in FIG. 3, 10 is an insulating substrate, 11 is an insulating film, 12 is a P ^{+ type} semiconductor film, 13 is an N ^{+ type} semiconductor film,
14 is a film made of metal or a compound of metal and semiconductor, 15
Is wiring. According to this structure, the source and drain diffusion layers of the opposite conductivity type MIS transistor corresponding to the output of the inverter circuit element become the gate of the inverter circuit element of the next stage through the film made of metal or a compound of metal and semiconductor. An ohmic connection is established with the P ^{+ type} or N ^{+ type} semiconductor film. Therefore, in the structure of the present invention, it is not necessary to form a contact hole in the gate as compared with the inverter circuit element of the conventional structure, so that the degree of integration is improved, and since the contact hole is reduced, the resistance of the contact can be reduced. In addition, since the wiring layer formed by the gate and the wiring layer connected to the source and drain layers are formed in different layers, they have excellent characteristics such as increased freedom of wiring, and high speed,
This structure is suitable for highly integrated LSI.

Next, a manufacturing process for realizing the structure according to the present invention will be described based on Examples.

2 (a) to 2 (d) are schematic cross-sectional views showing the main steps of manufacturing a CMOS inverter circuit element having N ⁺ and P ⁺ polycrystalline silicon gates having an SOS structure according to this structure. 1,
3 to 9 are the same as 1 and 3 to 9 in FIG. 1, 16 is a gate oxide film, 17 is a titanium silicide film, and 18 is an interlayer oxide film. First, 0.5 μm thick on the sapphire substrate 1.
Forming a silicon island and then thermally oxidizing it to form a gate oxide film 1
6 thickness 400 Å, and further, N type region 3 and P type region 4 are formed by ion implantation of impurities. [Fig. 2
(a)] Next, the gate oxide film 4 at the boundary between the N-type region 3 and the P-type region 4 of the silicon island is patterned to form an opening so that the underlying silicon film is exposed, and the exposed upper portion of the silicon film is exposed. Is converted to titanium silicide. (FIG. 2 (b)) Here, titanium silicide is formed by the following steps. First, a titanium film having a thickness of 400 Å is formed on the entire surface of the sample having an opening formed in the gate oxide film 4 by a sputtering method and then annealed at 600 ° C. for 20 minutes in a hydrogen atmosphere. At this time, only the portion of the opening where the silicon is exposed becomes titanium silicide. Next, this sample is treated by boiling and washing with a mixed solution of HCl: H ₂ O ₂ : H ₂ O = 1: 1: 4 for 10 minutes, and pure washing for 10 minutes, and then annealed in a nitrogen atmosphere at 800 ° C. for 30 minutes. By performing acid cleaning here, the titanium film is peeled off, and titanium silicide remains only in the openings as shown in FIG.

Next, 0.5 μmC of polycrystalline silicon is added to the sample in the state of (b).
After forming by VD method and patterning the gate and wiring regions, P ^{+ is} self-aligned by ion implantation of impurities.
Type source / drain region 5, N ^{+ type} source / drain region 6, P ^{+ type} polycrystalline silicon 7, N ^{+ type} polycrystalline silicon 8
Are formed (FIG. 2 (c)). Where N at the top of the opening
^{The + type} and P type polycrystalline silicon must be formed smaller than the size of the opening. By doing so, the titanium silicide 14 in the opening and the P ^{+ type} source / drain region 5 are formed.
A connection can be established between the N ^{+ type} source / drain region 6.
As a result, P ^{+ type} and N ^{+ type} source / drain regions 5, 6 are formed.
And the N ^{+ type} and P ^{+ type} polycrystalline silicon layers 7 and 8 can be ohmic-connected via the titanium silicide 14.

Next, an interlayer insulating film is formed on the sample in the state of (c) by 0.5 μm CVD.
After patterning the contact holes by
The Al wiring 9 is formed. (FIG. 2 (d)) The above is an embodiment of the manufacturing process for realizing the structure of the present invention. In this embodiment, a titanium silicide film is used as a method for establishing ohmic connection between semiconductors of opposite conductivity types.
This is also possible with other metal silicides or metals.

Although the manufacturing process has been described above by taking the CMOS inverter circuit element having the SOS structure as an example, it is apparent that the present invention can be applied to the inverter circuit element having the general MIS structure. Further, the structure of the present invention can be applied to a complementary MIS type semiconductor device having a single conductive type semiconductor gate, and can be applied not only to the inverter circuit element but also to other circuit elements.

(Effect of the Invention) According to the present invention, as compared with the structure of the conventional MIS type semiconductor device, the number of contact holes is small, so that the degree of integration is high, the resistance can be reduced, and the degree of freedom of wiring is increased. A semiconductor device having excellent characteristics can be obtained.

[Brief description of drawings]

1 (a) and 1 (b) are schematic sectional views and plan views of an inverter circuit element formed by this structure as a basic embodiment of a semiconductor device according to the present invention, and FIGS. 2 (a) to 2 (d). ) Is a schematic cross-sectional view showing an example of a manufacturing process for realizing the semiconductor device of the present invention, and FIGS. 3A and 3B are schematic cross-sectional views of a conventional MIS type semiconductor device having an SOI structure. FIGS. 4A and 4B are a schematic cross-sectional view and a plan view of an improved conventional MIS semiconductor device having an SOI structure, respectively. 1 ... Sapphire substrate, 2 ... Oxide film, 3 ... N-type region, 4 ... P-type region, 5 ... P ^{+ type} source / drain region, 6 ... N ^{+ type} source / drain region, ⁷⁺ ...... P ^{+ type} polycrystalline silicon, 8 …… N ^{+ type} polycrystalline silicon, 9 …… Al
Wiring, 10 ... Insulating substrate, 11 ... Insulating film, 12 ... P
⁺ Type semiconductor film, 13 ... N ^{+ type} semiconductor film, 14 ... Film of metal or compound of metal and semiconductor, 15 ... Wiring, 16 ...
... Gate oxide film, 17 ... Titanium silicide film, 18 ...
… Interlayer oxide film.

Claims (1)

[Claims] 1. In a complementary MIS type semiconductor device formed on a semiconductor film provided on an insulator, a layer of a metal or a compound of a metal and a semiconductor so as to include a drain region of a MIS type transistor of an opposite conductivity type. Is formed, and the semiconductor region of the next stage is connected to the upper part of the region to form the ohmic contact between the drain region and the gate of the MIS transistor of the opposite conductivity type.