JPS6362893B2 - - Google Patents
Info
- Publication number
- JPS6362893B2 JPS6362893B2 JP18062383A JP18062383A JPS6362893B2 JP S6362893 B2 JPS6362893 B2 JP S6362893B2 JP 18062383 A JP18062383 A JP 18062383A JP 18062383 A JP18062383 A JP 18062383A JP S6362893 B2 JPS6362893 B2 JP S6362893B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- single crystal
- semiconductor
- forming
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 30
- 239000013078 crystal Substances 0.000 claims description 29
- 238000000034 method Methods 0.000 claims description 23
- 238000002844 melting Methods 0.000 claims description 18
- 230000008018 melting Effects 0.000 claims description 17
- 229910052751 metal Inorganic materials 0.000 claims description 16
- 239000002184 metal Substances 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 238000000137 annealing Methods 0.000 claims description 8
- 229910052594 sapphire Inorganic materials 0.000 claims description 8
- 239000010980 sapphire Substances 0.000 claims description 8
- 238000010894 electron beam technology Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 239000012212 insulator Substances 0.000 claims description 5
- 239000011810 insulating material Substances 0.000 claims 1
- 239000005300 metallic glass Substances 0.000 claims 1
- 239000003870 refractory metal Substances 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 18
- 229910052710 silicon Inorganic materials 0.000 description 18
- 239000010703 silicon Substances 0.000 description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 229910052814 silicon oxide Inorganic materials 0.000 description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 6
- 238000001259 photo etching Methods 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- LNDHQUDDOUZKQV-UHFFFAOYSA-J molybdenum tetrafluoride Chemical compound F[Mo](F)(F)F LNDHQUDDOUZKQV-UHFFFAOYSA-J 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
- NXHILIPIEUBEPD-UHFFFAOYSA-H tungsten hexafluoride Chemical compound F[W](F)(F)(F)(F)F NXHILIPIEUBEPD-UHFFFAOYSA-H 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/0242—Crystalline insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02488—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Materials Engineering (AREA)
- Recrystallisation Techniques (AREA)
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、半導体装置の製造方法に係わり、特
に絶縁膜上に方位の制御された良好な半導体単結
晶層を得る方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of obtaining a good semiconductor single crystal layer with controlled orientation on an insulating film.
半導体集積回路の分野では、従来の２次元的に
活性領域を配置する手法にかわつて、最近３次元
的に積層する手法が検討され始めている。ここで
の基幹技術は、レーザビームや電子ビーム等によ
るビームアニールで絶縁膜上に良好な単結晶層を
得ることにある。また、方位制御も一つの重要な
事項である。これは、絶縁膜上の単結晶層の面内
方位をそろえておかないと、移動度の違い等によ
つて、素子の特性のばらつきが現われるためであ
る。
In the field of semiconductor integrated circuits, instead of the conventional method of arranging active regions two-dimensionally, a method of stacking them three-dimensionally has recently begun to be considered. The key technology here is to obtain a good single crystal layer on the insulating film by beam annealing using a laser beam, an electron beam, or the like. Direction control is also an important issue. This is because unless the in-plane orientations of the single crystal layer on the insulating film are aligned, variations in device characteristics will occur due to differences in mobility and the like.
従来のビームアニール法を第１図に示す。図中
１はシリコン基板、２はシリコン酸化膜、３はシ
リコン酸化膜２に形成した開孔、４は多結晶シリ
コン膜、５はレーザビーム或いは電子ビーム、６
は単結晶化したシリコン層である。ここで、開孔
３を通して多結晶シリコン膜４は、シリコン基板
１と接している。この方法では、レーザビームや
電子ビーム等をシリコン膜４を一部分づつ溶融し
ながら走査する。このようにして開孔部３からの
結晶方位情報を上部の多結晶シリコン膜４に伝え
てシリコン酸化膜２上に方位制御された単結晶シ
リコン層６が形成されることになる。 A conventional beam annealing method is shown in FIG. In the figure, 1 is a silicon substrate, 2 is a silicon oxide film, 3 is an opening formed in the silicon oxide film 2, 4 is a polycrystalline silicon film, 5 is a laser beam or electron beam, and 6
is a single crystal silicon layer. Here, polycrystalline silicon film 4 is in contact with silicon substrate 1 through opening 3 . In this method, a laser beam, an electron beam, or the like is scanned while melting the silicon film 4 one part at a time. In this way, the crystal orientation information from the opening 3 is transmitted to the upper polycrystalline silicon film 4, and a single crystal silicon layer 6 whose orientation is controlled is formed on the silicon oxide film 2.
しかしながら、この種の方法にあつては次のよ
うな問題があつた。すなわち、シリコン酸化膜の
熱伝導度は3.4×10-3〔calcm-1・sec-1・deg-1〕で
あり、一方シリコンのそれは0.2〔calcm-1・
sec-1・deg-1〕となつているため、開孔部３では
他の部分よりも熱の逃げが大きい。従つて、開孔
部３が丁度とける程度（Si：15w／cm℃、SiO2：
0.014w／cm℃）のパワーでアニールすると、シ
リコン酸化膜２上のシリコンに対してはパワーが
大きすぎてシリコンが蒸発してしまうことが起
る。また、シリコン酸化膜上のシリコンに対し丁
度良くパワーを設定すると、開孔部３のシリコン
が溶融しない場合がある。従つて、この両者を満
足させなければならないためパワーの許容幅は非
常に小さくなり、結晶成長の温度制御が極めて困
難であつた。 However, this type of method has the following problems. In other words, the thermal conductivity of silicon oxide film is 3.4×10 -3 [calcm -1・sec -1・deg -1 ], while that of silicon is 0.2 [calcm -1・
sec -1 ·deg -1 ], so heat escapes from the opening 3 more than from other parts. Therefore, the opening 3 is just melted (Si: 15w/cm℃, SiO 2 :
When annealing is performed with a power of 0.014 w/cm (°C), the power is too high for the silicon on the silicon oxide film 2, and the silicon may evaporate. Furthermore, if the power is set just right for the silicon on the silicon oxide film, the silicon in the opening 3 may not melt. Therefore, since both of these conditions must be satisfied, the allowable range of power becomes extremely small, making it extremely difficult to control the temperature during crystal growth.
本発明の目的は、ビームアニールにおけるパワ
ーの許容幅を大きくすることができ、結晶成長の
温度制御を比較的緩やかにし、成長結晶の良好な
方位制御が可能となり、３次元IC等の製造に好
適する半導体装置の製造方法を提供することにあ
る。
The purpose of the present invention is to make it possible to widen the allowable range of power in beam annealing, to make the temperature control of crystal growth relatively gentle, to enable good orientation control of the grown crystal, and to be suitable for manufacturing three-dimensional ICs, etc. An object of the present invention is to provide a method for manufacturing a semiconductor device.
本発明の骨子は、絶縁膜上単結晶層を形成する
ための基板として、結晶質絶縁体例えばサフアイ
ア基板上に形成したシリコン単結晶膜を用いるこ
とにある。
The gist of the present invention is to use a silicon single crystal film formed on a crystalline insulator, such as a sapphire substrate, as a substrate for forming a single crystal layer on an insulating film.
サフアイア基板等の結晶性絶縁体は、通常シリ
コンに比して熱伝導度が小さいので、熱の逃げを
小さく抑えることができる。一方、３次元ICを
形成する場合、下地基板には通常能動素子が形成
されている。そして、この能動素子に熱的影響を
大きく与えることは好ましくない。従つて、開孔
部分から順次溶融固化した後の熱はす早く分散し
てしまうことが望ましく、そのためには熱伝導率
の高い高融点金属膜を層内に配置すればよい。 A crystalline insulator such as a sapphire substrate usually has lower thermal conductivity than silicon, so it is possible to suppress heat escape. On the other hand, when forming a three-dimensional IC, active elements are usually formed on the base substrate. Further, it is not preferable to have a large thermal influence on this active element. Therefore, it is desirable that the heat that has been melted and solidified from the open pores is quickly dispersed, and for this purpose, a high melting point metal film with high thermal conductivity may be disposed in the layer.
本発明はこのような点に着目し、非晶質絶縁膜
上に半導体単結晶層を形成し半導体素子を多層に
形成する半導体装置の製造方法において、結晶性
絶縁物上に半導体単結晶膜を形成する工程と、こ
の半導体単結晶膜上に非晶質絶縁膜を形成し、か
つチツプのスクライブライン上に位置する半導体
単結晶膜上に高融点金属膜を形成する工程と、次
いで上記非晶質絶縁膜の一部をエツチングして上
記半導体単結晶膜の一部を露出せしめる工程と、
次いで全面に多結晶半導体膜を形成する工程と、
しかるのち電子ビーム或いはレーザビームを用い
て上記多結晶半導体膜をアニールして単結晶化す
るようにした方法である。 The present invention focuses on these points, and includes a method for manufacturing a semiconductor device in which a semiconductor single crystal layer is formed on an amorphous insulating film and semiconductor elements are formed in multiple layers. forming an amorphous insulating film on the semiconductor single crystal film, and forming a high melting point metal film on the semiconductor single crystal film located on the scribe line of the chip; etching a part of the quality insulating film to expose a part of the semiconductor single crystal film;
Next, a step of forming a polycrystalline semiconductor film on the entire surface,
In this method, the polycrystalline semiconductor film is then annealed using an electron beam or a laser beam to form a single crystal.
本発明によれば、サフアイア基板等の結晶性絶
縁基板を高融点金属という組合せを用いることに
よつて、局所的には熱伝導度がシリコン基板に比
して小さいにも拘わらず、大きくみると熱の蓄積
が極めて小さいような構造を得ることが出来る。
従つて、前記第１図に示した開孔部のシリコンを
とかすビームパワーと絶縁膜上のシリコンをとか
すビームパワーとが接近してくるため、良好な方
位制御が可能となる。また、サフアイア上のシリ
コン単結晶層に形成された素子に対しては、高融
点金属膜による放熱効果のために、ビームアニー
ルによる熱の影響を著しく少なくすることができ
る。このため、３次元ICの製造に極めて有効で
ある。
According to the present invention, by using a combination of a crystalline insulating substrate such as a sapphire substrate and a high-melting point metal, although the thermal conductivity is locally lower than that of a silicon substrate, it can be A structure with extremely low heat accumulation can be obtained.
Therefore, since the beam power for melting the silicon in the opening shown in FIG. 1 approaches the beam power for melting the silicon on the insulating film, good azimuth control is possible. Further, for elements formed on a silicon single crystal layer on sapphire, the effect of heat due to beam annealing can be significantly reduced due to the heat dissipation effect of the high melting point metal film. Therefore, it is extremely effective in manufacturing three-dimensional ICs.
以下、本発明の詳細を図示の実施例によつて説
明する。
Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.
第２図ａ〜ｆは本発明の一実施例方法を説明す
るための工程断面図である。まず、第２図ａに示
す如くサフアイア基板（結晶性絶縁物）１１上に
通常のSOS形成工程に従つてシラン及び水素によ
つて単結晶シリコン膜１２を形成する。続いて、
第２図ｂに示す如く全面にシリコン酸化膜（非晶
質絶縁膜）１３を形成したのち、チツプスクライ
ブライン上に該ラインと同程度の間隔及び幅の溝
１４を通常のフオトエツチング法を用いて形成す
る。次いで、フツ化モリブデン若しくはフツ化タ
ングステンと不活性ガスとによつて第２図ｃに示
す如く上記溝部１４内にモリブデン若しくはタン
グステン膜（高融点金属膜）１５を約2000〔Å〕
厚さに選択形成する。その後、第２図ｄに示す如
くシリコン酸化膜１３を一部エツチング除去して
単結晶シリコン膜１２の一部を露出させる開孔１
６を形成する。この開孔１６は、次の絶縁膜上単
結晶層を形成する時のシードになる部分である。 FIGS. 2a to 2f are process sectional views for explaining a method according to an embodiment of the present invention. First, as shown in FIG. 2a, a single crystal silicon film 12 is formed on a sapphire substrate (crystalline insulator) 11 using silane and hydrogen according to a normal SOS forming process. continue,
After forming a silicon oxide film (amorphous insulating film) 13 on the entire surface as shown in FIG. 2b, grooves 14 with the same spacing and width as the lines are formed on the chip scribe lines using a normal photoetching method. to form. Next, a molybdenum or tungsten film (high melting point metal film) 15 is formed in the groove 14 to a thickness of about 2000 Å using molybdenum fluoride or tungsten fluoride and an inert gas, as shown in FIG. 2c.
Form to select thickness. Thereafter, as shown in FIG. 2d, a portion of the silicon oxide film 13 is etched away to expose a portion of the single crystal silicon film 12 through an opening 1.
form 6. This opening 16 serves as a seed when forming the next single crystal layer on the insulating film.
次に、全面にシランの熱分解によつて、第２図
ｅに示す如く全面に多結晶シリコン膜１７を形成
する。その後、第２図ｆに示す如くレーザビーム
或いは電子ビームによるビームアニール法で、多
結晶シリコン膜１７の単結晶化処理を行う。かく
して、シリコン酸化膜１３上にシリコン単結晶層
１８が形成されることになる。 Next, a polycrystalline silicon film 17 is formed on the entire surface by thermal decomposition of silane, as shown in FIG. 2e. Thereafter, as shown in FIG. 2f, the polycrystalline silicon film 17 is made into a single crystal by beam annealing using a laser beam or an electron beam. In this way, a silicon single crystal layer 18 is formed on the silicon oxide film 13.
このようにすることにより、開孔部１６と平坦
部とでの許容ビームパワーが近づくため、結晶成
長の制御が容易となる。 By doing so, the permissible beam powers at the aperture 16 and the flat portion become close to each other, making it easier to control crystal growth.
第３図ａ〜ｄは他の実施例を説明するための工
程断面図である。この実施例が先に説明した実施
例と異なる点は、高融点金属膜１５の形成方法と
して選択CVD法の代りに通常のフオトエツチン
グ法を用いることにある。 FIGS. 3a to 3d are process sectional views for explaining another embodiment. This embodiment differs from the previously described embodiments in that the high melting point metal film 15 is formed using a normal photoetching method instead of the selective CVD method.
まず、第３図ａに示す如くサフアイア基板１１
上に通常のSOS形成工程に従つて、単結晶シリコ
ン膜１２を形成する。続いて、蒸着法を用い全面
にタングステン若しくはモリブデン膜（高融点金
属膜）１５を形成する。次いで、通常のフオトエ
ツチング法を用い、第３図ｂに示す如くスクライ
ブラインに相当する部分を除いて高融点金属膜１
５をエツチング除去する。続いて、プラズマ
CVD法を用い、第３図ｃに示す如く全面にシリ
コン酸化膜を形成したのち、シード部をエツチン
グ除去して開孔１６を形成する。次いでLPCVD
法を用い、第３図ｄに示す如く全面に多結晶シリ
コン膜１７を形成する。この最終形態は、先の実
施例と高融点金属膜１５上にシリコン酸化膜１３
が存在する以外は同一形態になる。 First, as shown in FIG. 3a, the sapphire substrate 11
A single crystal silicon film 12 is formed thereon according to a normal SOS formation process. Subsequently, a tungsten or molybdenum film (high melting point metal film) 15 is formed on the entire surface using a vapor deposition method. Next, using a normal photoetching method, the high melting point metal film 1 is removed except for the portion corresponding to the scribe line, as shown in FIG. 3b.
5 is removed by etching. Next, plasma
After forming a silicon oxide film on the entire surface using the CVD method as shown in FIG. 3c, the seed portion is etched away to form an opening 16. Then LPCVD
Using a method, a polycrystalline silicon film 17 is formed on the entire surface as shown in FIG. 3d. This final form is similar to the previous embodiment and has a silicon oxide film 13 on the high melting point metal film 15.
They have the same form except for the presence of .
このような方法であつても先の実施例と同様の
効果が得られるのは勿論のことである。また、単
結晶シリコン層を更に積み上げる場合には２層或
いは３層毎にこのような金属膜メツシユを形成す
ることにより、膜厚が厚い時の熱の逃げが悪くな
る問題も緩和することが出来る。 Of course, even with such a method, the same effects as in the previous embodiment can be obtained. In addition, when further stacking single crystal silicon layers, by forming such a metal film mesh every second or third layer, it is possible to alleviate the problem of poor heat escape when the film is thick. .
なお、本発明は上述した各実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々
変形して実施することができる。例えば、前記高
融点金属膜を形成する領域として、スクライブラ
インに加え素子領域の一部を用いることも可能で
ある。この場合、高集積化の点で若干不利となる
が放熱効果はより大きなものとなる。また、シリ
コン以外の他の半導体の単結晶化に適用できるの
も勿論のことである。 Note that the present invention is not limited to the embodiments described above, and can be implemented with various modifications without departing from the gist thereof. For example, it is also possible to use a part of the element region in addition to the scribe line as the region where the high melting point metal film is formed. In this case, there is a slight disadvantage in terms of high integration, but the heat dissipation effect becomes greater. It goes without saying that the present invention can also be applied to single crystallization of semiconductors other than silicon.
第１図は従来のビームアニール法の問題点を説
明するための断面図、第２図は本発明の一実施例
を説明するための工程断面図、第３図は他の実施
例を説明するための工程断面図である。
１１…サフアイア基板（結晶性絶縁物）、１２
…シリコン単結晶膜、１３…シリコン酸化膜、１
４，１６…開孔、１５…高融点金属膜、１７…多
結晶シリコン膜、１８…シリコン単結晶層。
Fig. 1 is a cross-sectional view for explaining the problems of the conventional beam annealing method, Fig. 2 is a process cross-sectional view for explaining one embodiment of the present invention, and Fig. 3 is for explaining another embodiment. FIG. 11...Sapphire substrate (crystalline insulator), 12
...Silicon single crystal film, 13...Silicon oxide film, 1
4, 16...Open hole, 15...High melting point metal film, 17...Polycrystalline silicon film, 18...Silicon single crystal layer.
Claims (1)
導体素子を多層に形成する半導体装置の製造方法
において、結晶性絶縁物上に半導体単結晶膜を形
成する工程と、この半導体単結晶膜上に非晶質絶
縁膜を形成し、かつチツプのスクライブライン上
に位置する半導体単結晶膜上に高融点金属膜を形
成する工程と、次いで上記非晶質絶縁膜の一部を
エツチングして上記半導体単結晶膜の一部を露出
せしめる工程と、次いで全面に多結晶半導体膜を
形成する工程と、しかるのち電子ビーム或いはレ
ーザビームを用いて上記多結晶半導体膜をアニー
ルして単結晶化する工程とを具備したことを特徴
とする半導体装置の製造方法。 ２ 前記結晶性絶縁物として、サフアイア基板を
用いたことを特徴とする特許請求の範囲第１項記
載の半導体装置の製造方法。 ３ 前記非晶質絶縁膜及び高融点金属膜を形成す
る工程として、前記半導体単結晶膜上に上記非晶
質絶縁膜を形成したのち、チツプのスクライブラ
イン上に位置する非晶質絶縁膜をエツチングし、
次いでこのエツチングにより露出した半導体単結
晶膜上に上記高融点金属膜を形成するようにした
ことを特徴とする特許請求の範囲第１項記載の半
導体装置の製造方法。 ４ 前記非晶質絶縁膜及び高融点金属膜を形成す
る工程として、前記半導体単結晶膜の前記スクラ
イブライン上に位置する部分に高融点金属膜を選
択的に形成し、次いで全面に上記非晶質絶縁膜を
形成するようにしたことを特徴とする特許請求の
範囲第１項記載の半導体装置の製造方法。[Scope of Claims] 1. A method for manufacturing a semiconductor device in which a semiconductor single crystal layer is formed on an amorphous insulating film and semiconductor elements are formed in multiple layers, including the step of forming a semiconductor single crystal film on a crystalline insulating material; , forming an amorphous insulating film on this semiconductor single crystal film, and forming a high melting point metal film on the semiconductor single crystal film located on the scribe line of the chip; A step of etching a part to expose a part of the semiconductor single crystal film, then a step of forming a polycrystalline semiconductor film on the entire surface, and then annealing the polycrystalline semiconductor film using an electron beam or a laser beam. 1. A method for manufacturing a semiconductor device, comprising a step of crystallizing the semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein a sapphire substrate is used as the crystalline insulator. 3. In the step of forming the amorphous insulating film and the high melting point metal film, after forming the amorphous insulating film on the semiconductor single crystal film, the amorphous insulating film located on the scribe line of the chip is etching,
2. The method of manufacturing a semiconductor device according to claim 1, wherein the refractory metal film is then formed on the semiconductor single crystal film exposed by this etching. 4. In the step of forming the amorphous insulating film and the high melting point metal film, a high melting point metal film is selectively formed on a portion of the semiconductor single crystal film located on the scribe line, and then the amorphous metal film is formed on the entire surface. 2. The method of manufacturing a semiconductor device according to claim 1, wherein a high quality insulating film is formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18062383A JPS6074507A (en) | 1983-09-30 | 1983-09-30 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18062383A JPS6074507A (en) | 1983-09-30 | 1983-09-30 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6074507A JPS6074507A (en) | 1985-04-26 |
| JPS6362893B2 true JPS6362893B2 (en) | 1988-12-05 |
Family
ID=16086445
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18062383A Granted JPS6074507A (en) | 1983-09-30 | 1983-09-30 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6074507A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020096099A1 (en) * | 2018-11-09 | 2020-05-14 | 주식회사 루닛 | Machine learning method and device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0590857U (en) * | 1991-05-29 | 1993-12-10 | 株式会社小桜建装 | Plug |
-
1983
- 1983-09-30 JP JP18062383A patent/JPS6074507A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020096099A1 (en) * | 2018-11-09 | 2020-05-14 | 주식회사 루닛 | Machine learning method and device |
| US10922628B2 (en) | 2018-11-09 | 2021-02-16 | Lunit Inc. | Method and apparatus for machine learning |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6074507A (en) | 1985-04-26 |
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