JPS5825222A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5825222A
JPS5825222A JP57087879A JP8787982A JPS5825222A JP S5825222 A JPS5825222 A JP S5825222A JP 57087879 A JP57087879 A JP 57087879A JP 8787982 A JP8787982 A JP 8787982A JP S5825222 A JPS5825222 A JP S5825222A
Authority
JP
Japan
Prior art keywords
film
single crystal
substrate
polycrystalline
laser beam
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57087879A
Other languages
Japanese (ja)
Other versions
JPS643047B2 (en
Inventor
Hiroyuki Tango
丹呉　浩侑
Yoshihisa Mizutani
水谷　嘉久
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP57087879A priority Critical patent/JPS5825222A/en
Publication of JPS5825222A publication Critical patent/JPS5825222A/en
Publication of JPS643047B2 publication Critical patent/JPS643047B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02598—Microstructure monocrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02691—Scanning of a beam

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To monocrystallize the entire amorphous semiconductor film on an insulating film by a method wherein an insulating film is attached to a single crystal substrate to be provided with some openings, the entire surface is then covered with an amorphous semiconductor film, a laser beam is used to monocrystallize the amorphous semiconductor exposed in an opening, and then the laser beam changes its position for the monocrystallization of all the amorphous semiconductor film on the insulating film. CONSTITUTION:A single crystal Si substrate 1 is coated with an SiO2 film 2, wherein a plurality of openings 3 are provided, and then is further coated with a thin polycrystalline Si film 5 except a part to remain without the film 5. Next, the entire surface is deposited with a polycrystalline Si film 5, whereinto Si ions 6 are implanted for the creation of defects within the film 5 for a effective absorption of energy in a later process. After this, an opening 3 not covered by the film 4 is subjected to a laser beam 7, whereby the polycrystalline Si film 5 in the opening 3 is converted into a single crystal 5a with the substrate 1 acting as seed. The laser beam 7 changes its position for a continued monocrystallization of the neighboring portions of the film 5 with the single crystal 5a now acting as a seed, which process is repeated until the entire film is converted into a monocrystalline film 5b. This results in the production of a substrate suitable for use in a high speed device.

Description

【発明の詳細な説明】 く発明の技術分針〉 本発明は改喪された半導体装置の製造方法に関する。[Detailed description of the invention] Inventive technology minute hand The present invention relates to a method of manufacturing a refurbished semiconductor device.

〈発明の技術的背景とその問題点〉 従来，シリコン（引）基板なる単結晶基板表面を熱酸化
してＳｉｏｚ膜を形成し、さらにＣＶＤ法によりＳｉ膜
を被着する工程がＩＣの分野で広く用いられている、然
しながら８ｉ０ｓ膜上に被着したＳ１膜は単結晶とはな
らず多結晶４膜となる。多結晶ＳＫ膜の抵抗値はかなり
高く、　　　　　　　　　　　　　従ってゲート電極或
いは配線材料としてこのような多結晶８ｉ膜を用いた半
導体装置における動作速度を制限する大きな要因となっ
ていた。<Technical background of the invention and its problems> Conventionally, in the IC field, the process of thermally oxidizing the surface of a single crystal substrate, such as a silicon substrate, to form a Sioz film, and then depositing a Si film using the CVD method. However, the S1 film deposited on the 8i0s film, which is widely used, is not a single crystal but a polycrystalline 4 film. The resistance value of the polycrystalline SK film is quite high, and has therefore been a major factor limiting the operating speed of semiconductor devices using such a polycrystalline 8i film as a gate electrode or wiring material.

〈発明の目的〉 本発明κよればζの様な絶縁体膜上の非単結晶半導体膜
を単結晶化せしめ、より速い動作速度が請求される半導
体装置の製造方法を提供することが出来る。<Object of the Invention> According to the present invention κ, it is possible to provide a method for manufacturing a semiconductor device that requires a higher operating speed by monocrystallizing a non-single crystal semiconductor film on an insulating film such as ζ.

〈発明の概要〉 単結晶基板上に皺基板の露出部を有する絶縁体膜を設け
る工程と、前記絶縁体膜上および前記露出基板上に非単
結晶半導体膜を形成する工程と、前記非単結晶半導体膜
のうち選択された領域のみ単結晶化する王権とを具備し
てなることを特徴とする。<Summary of the Invention> A step of providing an insulating film having an exposed portion of a wrinkled substrate on a single crystal substrate, a step of forming a non-single crystal semiconductor film on the insulating film and the exposed substrate, and a step of forming the non-single crystal semiconductor film on the insulating film and on the exposed substrate. The present invention is characterized in that it has the power to single-crystallize only a selected region of the crystalline semiconductor film.

〈発明の実施例〉 以下本発明の実施例を図面を参照して詳述する。<Embodiments of the invention> Embodiments of the present invention will be described in detail below with reference to the drawings.

先ず単結晶基板なる８ｉ基板（１）の主面Ｋ　１０００
℃のウェット０２中で熱酸化し絶縁体膜として５ｏｏｏ
ｉ厚の８　ｉ０２膜（２）を成長させる（第１図ａ）ｏ
こζで公知の耐熱酸化膜を用いたる選択酸化法により８
１基板（１）の主面に酸化膜のない開孔部（３）を設け
ている。これは耐熱酸化膜下に薄いバッファ酸化膜を挾
んで選択酸化を行ない、その後耐熱酸化膜、バッファ酸
化膜除去によシ開孔部（３）を形成出来る。First, the main surface K of the 8i substrate (1), which is a single crystal substrate, is 1000.
Thermal oxidation in wet 02°C to form an insulator film of 5ooo
Grow an 8 i02 film (2) of i thickness (Figure 1a) o
With this ζ, 8
An opening (3) without an oxide film is provided on the main surface of one substrate (1). In this method, selective oxidation is performed by sandwiching a thin buffer oxide film under the heat-resistant oxide film, and then the heat-resistant oxide film and the buffer oxide film are removed to form the openings (3).

バッツァ酸化膜を残した部分は薄いＲ４ｏｚ膜（４）と
して示した。このように選択酸化によるコプラナ技術を
用いることによシ表面の平担化が為されている０ 次に全面に４０００Ｘ厚の多結晶８１膜（５）をＣＶＤ
＊成しく第１！！！！ｂ　）、さらＫ　２００ＫｅＶの
加速電圧で３×１０”　／ａｌの引イオンをイオン打込
み（６）する（Ｊｌｌ１図Ｃ）ｏこのイオン打込み杜多
結晶別膜（５）の内部に欠陥を生じせしめ、その後のエ
ネルギービーム照射に際してエネルギー吸収を効果的に
行なわせる丸めのものである。The portion where the Bazza oxide film remained is shown as a thin R4oz film (4). In this way, the surface is planarized by using coplanar technology using selective oxidation.Next, a polycrystalline 81 film (5) with a thickness of 4000X is deposited on the entire surface by CVD.
*Succeed first! ! ! ! b) Further, ion implantation (6) of 3×10"/al is carried out at an accelerating voltage of 200 KeV (Figure C). This ion implantation causes defects inside the polycrystalline film (5). , which is rounded to effectively absorb energy during subsequent energy beam irradiation.

この状態でエネルギービーム例えばレーザー光を照射（
７）することにより多結晶８４膜（５）を開孔部（３）
からＳｉ山１１（２）上に区り、開孔部を介して隣接す
るＢｔＨ板（１）を成長種として単結晶化せしめる。多
結晶Ｓｔ膜（５）の領域（５ｍ）そして領域（５ｂ）と
いう具合に順次レーず一光を走査しながら照射して行く
ととくより（第１図ｄ、ｅ）単結晶化された低照射部分
の結晶方位にならって順次単結晶化され、遂に・は全面
の多結晶８１膜（５）を単結晶化することが出来るＯ ８ｉ基板（１）Ｋ　ＩＩＩ　Ｉ！する多結晶シリコンへ
のレーザー照射により、多結晶Ｓ１は極めて短時間で溶
融、再固化を行なうが、このとき開孔部（３）を介して
隣接すゐ８ｉ基ＩＮ　（１）を成長種としてエピタキシ
ャル成長し、基板Ｓｉと同一の結晶方位を有する単結晶
が成長する。エネルギービーム照射ＫＩＩしては、その
ビーム径、エネルギー密度を設定することによ９実質的
に多結晶８電属（５）にのみエネルギーを与え、ｓｓＯ
＊Ｉ［（２）及びその下に対しては熱的影響を与えない
ようにすることも可能である。In this state, an energy beam such as a laser beam is irradiated (
7) By opening the polycrystalline 84 film (5) in the opening (3)
The BtH plate (1) adjacent to the Si plate 11 (2) through the opening is used as a growth seed to form a single crystal. When the area (5m) and area (5b) of the polycrystalline St film (5) are sequentially irradiated with a single laser beam while scanning, it is especially noticeable (Fig. 1d, e) that the monocrystalline low The O 8i substrate (1) is sequentially made into a single crystal according to the crystal orientation of the irradiated area, and finally the entire polycrystalline 81 film (5) can be made into a single crystal. When the polycrystalline silicon is irradiated with a laser, the polycrystalline S1 melts and re-solidifies in an extremely short time, but at this time, the adjacent sui-8i group IN (1) is used as a growth seed through the opening (3). Epitaxial growth is performed to grow a single crystal having the same crystal orientation as the Si substrate. Energy beam irradiation KII gives energy only to the polycrystalline 8 metal (5) by setting the beam diameter and energy density, and ssO
*I[(2) and the area below it may be prevented from having any thermal influence.

第２図は全面にビーム照射が為され単結晶化が行なわれ
たＳｉ層を用いて第１のＭＩ８）ランジスタのゲート電
極（８）、配線（９）及びアクティブ領域として能動素
子なる第２のＭＩ８）ランジスタＱＧを形成したもので
ある。ここにｏｎｔｔａはソース、６Ｓｆ１４はドレイ
ン、ａＨｅは夫々第２のトランジスタのゲート酸化膜及
びゲート電極である０ ゲート電極（８）、配線（９）は単結晶化により数０７
口以下の抵抗値となり多結晶シリコンを用いた場合のｌ
Ａθ程度の値となった。ゲート電極（８）、配線（９）
へはエネルギービーム照射前文は後適当な時期ＫＰ　、
　Ｂ　、　Ａ、等の不純物を導入し低抵抗化を図る。Figure 2 shows the gate electrode (8) of the first MI8) transistor, the wiring (9), and the second active element as the active region, using a Si layer whose entire surface has been irradiated with a beam and made into a single crystal. MI8) A transistor QG is formed. Here, ontta is the source, 6Sf14 is the drain, and aHe is the gate oxide film and gate electrode of the second transistor, respectively.
When polycrystalline silicon is used, the resistance value becomes less than
The value was approximately Aθ. Gate electrode (8), wiring (9)
The preamble to the energy beam irradiation will be at an appropriate time after KP,
Impurities such as B and A are introduced to lower the resistance.

又、アクティブ領域顛は高速化が為され、又島状に形成
され、バルク素子に比べて所＠　ＳＯＳ構造のトランジ
スタと同様な効果を享受することが出来るＯ 又、予めエネルギービーム照射する半導体層をパターニ
ングしておくととくよりエネルギー吸収能が高まり単結
晶化を促進することが出来る０上記実施例に於いては基
板、半導体膜材料としてＳｔを例としたが、その他伽ヤ
ＧａＡｓの様な材料にも適用で自ることはもちろんであ
るａｔたイオン打込皐も先述Ｓｉに限らず、Ｇｅ等の半
導体元素。In addition, the active region is faster and is formed in an island shape, allowing it to enjoy the same effect as an SOS structure transistor compared to a bulk device. In the above embodiments, St was used as the substrate and semiconductor film material, but other materials such as GaAs, etc. Of course, ion implantation can also be applied to materials, and is not limited to the aforementioned Si, but can also be applied to semiconductor elements such as Ge.

Ａｒ等の不活性元素、Ａｓ、ｐ、Ｂ等のＮ又はＰ導電型
を与える元素のイオンを用いてもよいＯさらに、エネル
ギービームとしてレーザービームを用いているが、その
他覚子線、Ｘ線等の照射によっても同様の効果をあげる
ことが出来る。又、多結晶シリコンの代わりに一晶質シ
リコン膜を用いても良い０ また、上記実施例では、多結晶シリコン層（５）全面に
エネルギービーム照射を行なっているが高抵抗素子を製
作する場合の様に、照射を選択的に行ない所定領域を多
結晶シリコンのま１ｍこすことも可能である０ 會た、本実施例では単結晶化の種として半導体基板を用
いているが、サファイア、スピネルの様な絶縁性基板を
用いることも出来る第３図に本発明をこの８０８に応用
した例を示す。Ions of inert elements such as Ar, and elements giving N or P conductivity type such as As, p, and B may be used.Furthermore, although a laser beam is used as the energy beam, other sources such as rays, X-rays, etc. A similar effect can also be achieved by irradiation. Furthermore, a monocrystalline silicon film may be used instead of polycrystalline silicon.Also, in the above embodiment, the entire surface of the polycrystalline silicon layer (5) is irradiated with an energy beam, but when manufacturing a high resistance element, It is also possible to selectively perform irradiation and scrub polycrystalline silicon over a predetermined area by 1 m.Also, in this example, a semiconductor substrate is used as a seed for single crystallization, but sapphire, spinel An example in which the present invention is applied to this 808 is shown in FIG. 3, in which an insulating substrate such as 808 can also be used.

〈発明の効果〉 以上、説明したように本発明の方法は、トランジスタ、
ゲート電極、配線、高抵抗素子、容量素子等に利用する
ことが出来るが、例えばアクティブ領域−として示した
ようにフィールド領域上に能動素子を設けるなど、文理
を重ねてさらに絶縁体層と単結晶層を幾重にも重ねるこ
とが出来、従来横方向に広がった面積に配置されていた
デバイスを縦方向につみ重ねた構造に出来るととになり
デバイスの集積度を遠端に高めろことが出来る０以上説
明したように本発明は単結晶基板上に誼基板の露出部を
有する絶縁体膜を設ける工種と。<Effects of the Invention> As explained above, the method of the present invention can be applied to transistors,
It can be used for gate electrodes, wiring, high-resistance elements, capacitive elements, etc., but for example, as shown in the active region, an active element is provided on a field region, and by combining science and technology, it can be further applied to an insulating layer and a single crystal. It is possible to stack many layers, and it is possible to create a structure in which devices, which were conventionally arranged in a horizontally spread area, are stacked vertically, and the degree of integration of devices can be increased at the far end. As explained above, the present invention is a method of forming an insulating film having an exposed portion of the substrate on a single crystal substrate.

前記絶縁体膜上および前記露出基板上に非単結晶半導体
膜を形成する工種と、前記非単結晶半導体膜のうち選択
された領域のみ単結晶化する工種とを具備してなる半導
体装置の製造方法であり本発明の主旨を逸脱しない限り
種々変更を加え得ることは勿論である。Manufacturing a semiconductor device comprising a process for forming a non-single crystal semiconductor film on the insulator film and the exposed substrate, and a process for monocrystallizing only a selected region of the non-single crystal semiconductor film. It goes without saying that this is a method and that various changes can be made without departing from the spirit of the invention.

【図面の簡単な説明】[Brief explanation of drawings]

第１図（→〜（６）は本発明を説明する為の断面図。 第２図は本発明の詳細な説明する断面図、第３図はサフ
ァイア基板を用いた実施例を説明する新面図である。 図に於いて。 ｌ・・・別基板、　　２・・・８１の膜、　３・・・開
孔部。 ５・・・多結晶Ｓｔ膜、　　７・・・エネルギービーム
照射。 ８．１６・・・ゲート電極、　　９・・・配線。 １０・・・第２のトランジスタ、１１　、１２・・・ソ
ース領域。 １３　、１４・・・ドレイン領域、ｊ・・・ゲート８１
０！Ｊ［。 加・・・単結晶サファイア基板、２１・・・エピタキシ
ャル別層。 ρ・・・８ｉ０ｚ膜、田・・・開孔部、ム・・・単結晶
化されたＳ１膜。 代理人　弁理士　　則　近　憲　佑 （ほか１名） １１図 ７１区 第２図 １　　　／ｌ。 輩３図Figure 1 (→-(6) is a sectional view for explaining the present invention. Figure 2 is a sectional view for explaining the present invention in detail. Figure 3 is a new surface for explaining an embodiment using a sapphire substrate. In the figure. 1... Another substrate, 2... 81 film, 3... Opening part. 5... Polycrystalline St film, 7... Energy beam irradiation. 8 .16... Gate electrode, 9... Wiring. 10... Second transistor, 11, 12... Source region. 13, 14... Drain region, j... Gate 81
0! J [. Ka... Single crystal sapphire substrate, 21... Epitaxial separate layer. ρ...8i0z film, T...opening area, M...single crystallized S1 film. Agent Patent Attorney Noriyuki Chika (and 1 other person) 11 Figure 71 Ward 2 Figure 1 /l. 3rd figure

Claims (2)

【特許請求の範囲】[Claims] （１）単結晶基板上に＃基板の露出部を有する絶縁体膜
を設ける工程と、前記絶縁体膜上および前記露出基板上
に非単結晶半導体膜を形成する工程と、前記非単結晶半
導体膜のうち選択された領域のみ単結晶化する工程とを
具備してなることを特徴とする半導体装置の製造方法０(1) A step of providing an insulating film having an exposed portion of the # substrate on a single crystal substrate, a step of forming a non-single crystal semiconductor film on the insulating film and the exposed substrate, and a step of forming the non-single crystal semiconductor film on the insulating film and on the exposed substrate. A method for manufacturing a semiconductor device 0, characterized in that it comprises a step of monocrystallizing only a selected region of a film. （２）前記非単結晶半導体膜のうち選択され九領域のみ
単結晶化するに先だって前記非単結晶中導体＠にイオン
打込みを行なうことを特徴とする特許法０(2) Patent method 0 characterized in that ion implantation is performed into the non-single crystal medium conductor @ before monocrystallizing only selected nine regions of the non-single crystal semiconductor film.
JP57087879A 1982-05-26 1982-05-26 Manufacture of semiconductor device Granted JPS5825222A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57087879A JPS5825222A (en) 1982-05-26 1982-05-26 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57087879A JPS5825222A (en) 1982-05-26 1982-05-26 Manufacture of semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP14327079A Division JPS5667923A (en) 1979-11-07 1979-11-07 Preparation method of semiconductor system

Publications (2)

Publication Number Publication Date
JPS5825222A true JPS5825222A (en) 1983-02-15
JPS643047B2 JPS643047B2 (en) 1989-01-19

Family

ID=13927146

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57087879A Granted JPS5825222A (en) 1982-05-26 1982-05-26 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5825222A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6336515A (en) * 1986-07-30 1988-02-17 Sony Corp Manufacture of thin single-crystal semiconductor film
JPS6445975A (en) * 1987-08-12 1989-02-20 Nippon Kokan Kk Cavitation detecting device for pump

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6336515A (en) * 1986-07-30 1988-02-17 Sony Corp Manufacture of thin single-crystal semiconductor film
JPS6445975A (en) * 1987-08-12 1989-02-20 Nippon Kokan Kk Cavitation detecting device for pump

Also Published As

Publication number Publication date
JPS643047B2 (en) 1989-01-19

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