JPS6364892B2 - - Google Patents
Info
- Publication number
- JPS6364892B2 JPS6364892B2 JP6170981A JP6170981A JPS6364892B2 JP S6364892 B2 JPS6364892 B2 JP S6364892B2 JP 6170981 A JP6170981 A JP 6170981A JP 6170981 A JP6170981 A JP 6170981A JP S6364892 B2 JPS6364892 B2 JP S6364892B2
- Authority
- JP
- Japan
- Prior art keywords
- laser
- silicon
- diffusion layer
- reflection coefficient
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 238000010438 heat treatment Methods 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims description 3
- 230000001678 irradiating effect Effects 0.000 claims description 3
- 239000000463 material Substances 0.000 claims 1
- 238000009792 diffusion process Methods 0.000 description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 10
- 229920005591 polysilicon Polymers 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 238000000034 method Methods 0.000 description 8
- 229910004298 SiO 2 Inorganic materials 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 3
- 238000005224 laser annealing Methods 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Health & Medical Sciences (AREA)
- High Energy & Nuclear Physics (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
Description
【発明の詳細な説明】
本発明は、半導体装置の製造方法、特に半導体
デバイスの製造におけるエネルギー線を用いる熱
処理の方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of heat treatment using energy rays in manufacturing a semiconductor device.
この分野の一般的な背景技術を略述すると、レ
ーザアニールの如きエネルギー線を用いる熱処理
は半導体デバイスの製造工程においてよく用いら
れる。例えば半導体基板にヒ素（As）をイオン
注入した後に十分に強いエネルギーのレーザ照射
を行つてイオン注入で打込まれたAsを活性化す
ることがなされる。 To briefly explain the general background technology in this field, heat treatment using energy beams such as laser annealing is often used in the manufacturing process of semiconductor devices. For example, after ion-implanting arsenic (As) into a semiconductor substrate, laser irradiation with sufficiently strong energy is performed to activate the As implanted by ion implantation.
ところで、半導体デバイスの製造において、半
導体ウエハ上に酸化膜または窒化膜の如き絶縁膜
を被着せしめることは通常よく行われる。第１図
を参照すると、１はシリコン基板、２は二酸化シ
リコン（SiO2）絶縁膜であり、SiO2膜２はソー
ス、ドレイン領域形成のためパターニングされ、
Asのイオン注入によつてｎ形拡散層３が形成さ
れ終つた状態が示される。拡散層３において下地
のシリコンは露出されている。 Incidentally, in the manufacture of semiconductor devices, it is common practice to deposit an insulating film such as an oxide film or a nitride film on a semiconductor wafer. Referring to FIG. 1, 1 is a silicon substrate, 2 is a silicon dioxide (SiO 2 ) insulating film, and the SiO 2 film 2 is patterned to form source and drain regions.
A state in which an n-type diffusion layer 3 has been formed by As ion implantation is shown. The underlying silicon in the diffusion layer 3 is exposed.
特にかかる構造のウエハに光ビーム例えばレー
ザ照射をなすについて、イオン注入したAsの活
性化に必要なレーザエネルギーは、絶縁膜の下の
シリコンと関係して問題がある。第１図に戻り、
SiO2膜２が6000〔Å〕の膜厚のものであるとし
て、そのレーザ反射係数は約13％であるのに対
し、シリコンが露出された拡散層３の表面のレー
ザ反射係数は約38％である。レーザ反射係数が小
であることはそれだけレーザの吸収率が高いとい
うことであるから、Asの活性化のためウエハに
矢印で示す如くレーザ照射したとき、拡散層３に
とつては最適のレーザ照射であつても、SiO2膜
２の下のシリコンにとつてはエネルギーが大に過
ぎて、シリコンが溶融し、絶縁膜の下でリツプル
（ripple）現象（波打ち現象）が第１図に４で示
す如く発生し、更に第１図に５で示す部分に反射
係数の違いによるミスマツチが認められその部分
が損傷する原因となる。 In particular, when irradiating a wafer with such a structure with a light beam, such as a laser, the laser energy required to activate the ion-implanted As is problematic in relation to the silicon under the insulating film. Returning to Figure 1,
Assuming that the SiO 2 film 2 has a thickness of 6000 Å, its laser reflection coefficient is approximately 13%, whereas the laser reflection coefficient of the surface of the diffusion layer 3 where silicon is exposed is approximately 38%. It is. A small laser reflection coefficient means a high laser absorption rate, so when the wafer is irradiated with laser as shown by the arrow to activate As, the laser irradiation is optimal for the diffusion layer 3. Even so, the energy is too great for the silicon under the SiO 2 film 2, and the silicon melts, causing a ripple phenomenon (waving phenomenon) under the insulating film, as shown in Figure 1 (4). Further, a mismatch due to a difference in reflection coefficient is observed in the portion indicated by 5 in FIG. 1, which causes damage to that portion.
本発明の目的は、従来技術におけるレーザアニ
ール工程で経験される上記の特定の課題を解決す
るにある。かかる目的を達成するために、本発明
の方法においては、ポリシリコンと単結晶シリコ
ンのレーザ反射係数がほぼ等しいことに注目し、
第１図に示す例において絶縁膜上にポリシリコン
層を被着せしめた後にイオン注入で打込んだ不純
物の活性化のためのレーザ照射を行なうものであ
る。 It is an object of the present invention to solve the above-mentioned particular problems experienced in laser annealing processes in the prior art. In order to achieve this objective, in the method of the present invention, it is noted that the laser reflection coefficients of polysilicon and single crystal silicon are almost equal,
In the example shown in FIG. 1, after a polysilicon layer is deposited on an insulating film, laser irradiation is performed to activate impurities implanted by ion implantation.
以下、本発明の方法の実施例を添付図面を参照
して説明する。 Embodiments of the method of the present invention will be described below with reference to the accompanying drawings.
第２図の断面図において、第１図と同じ部分は
同じ符号で示すが、シリコン基板１上に厚さ6000
〜7000〔Å〕のSiO2絶縁膜２を形成し、それをパ
ターニングし、Asのイオン注入によつてｎ形拡
散層３が形成されている。 In the cross-sectional view of FIG. 2, the same parts as in FIG. 1 are designated by the same reference numerals.
A SiO 2 insulating film 2 of ~7000 Å is formed, patterned, and an n-type diffusion layer 3 is formed by implanting As ions.
上記の工程が終つた後に、全面に化学気相成長
法（CVD法）で厚さ5000〔Å〕から１〔μm〕のポ
リシリコン層を成長させ、通常のホトリソグラフ
イ技術を用いてパターニングして、図示される如
き拡散層３の表面を露出するポリシリコン層６を
形成する。かかるポリシリコン層６を形成する理
由は、ポリシリコンのレーザ反射係数は30数パー
セント程度で単結晶シリコンの反射係数にほぼ等
しいことに着目し、SiO2膜２の下のシリコンを
溶融することなく、拡散層３の適正なレーザ照射
を行うためである。 After the above steps are completed, a polysilicon layer with a thickness of 5000 [Å] to 1 [μm] is grown on the entire surface by chemical vapor deposition (CVD) and patterned using normal photolithography. Then, a polysilicon layer 6 is formed which exposes the surface of the diffusion layer 3 as shown in the figure. The reason for forming such a polysilicon layer 6 is that the laser reflection coefficient of polysilicon is about 30%, which is almost equal to the reflection coefficient of single crystal silicon. This is to properly irradiate the diffusion layer 3 with the laser.
続いて図に矢印で示す如くレーザ照射を行な
う。レーザ照射は、図示の実施例においては、
CWArを用い約８〔Ｗ〕のパワーで実施した。 Subsequently, laser irradiation is performed as indicated by the arrow in the figure. In the illustrated embodiment, the laser irradiation is
It was carried out using CWAr with a power of about 8 [W].
最後に、拡散層３をマスクで覆い、例えばドラ
イエツチングでポリシリコン層６を除去する。 Finally, the diffusion layer 3 is covered with a mask, and the polysilicon layer 6 is removed, for example, by dry etching.
以上に説明した如く、本発明の方法において
は、レーザ反射係数がシリコンのそれとは異なる
絶縁膜上にポリシリコン層を形成し、ポリシリコ
ンと単結晶シリコンとはほぼ同程度のレーザ反射
係数のものであることを利用して拡散層における
打込み不純物活性化のためのレーザ照射を行なう
ことにより、従来技術におけるシリコン溶融によ
る波打ち現象および拡散層と絶縁膜の境界におけ
るレーザ反射係数の違いによるミスマツチを阻止
することが可能となり、製造される半導体装置の
信頼性が高められるものである。 As explained above, in the method of the present invention, a polysilicon layer is formed on an insulating film whose laser reflection coefficient is different from that of silicon, and polysilicon and single crystal silicon have approximately the same laser reflection coefficient. By using this fact to perform laser irradiation to activate implanted impurities in the diffusion layer, we can prevent the waving phenomenon caused by silicon melting and the mismatch caused by the difference in laser reflection coefficient at the boundary between the diffusion layer and the insulating film in conventional technology. This makes it possible to improve the reliability of the manufactured semiconductor device.
第１図は従来技術によるレーザアニール工程を
示す断面図、第２図は本発明の方法を実施する工
程を示す断面図である。
１……シリコン基板、２……SiO2、３……ｎ
形拡散層、４……リツプル、５……ミスマツチ部
分、６……ポリシリコン層。
FIG. 1 is a sectional view showing a laser annealing process according to the prior art, and FIG. 2 is a sectional view showing a process of carrying out the method of the present invention. 1... Silicon substrate, 2... SiO 2 , 3... n
shaped diffusion layer, 4... ripple, 5... mismatched portion, 6... polysilicon layer.
Claims (1)
めの光ビームを照射することから成る熱処理にお
いて、不純物拡散層形成のため半導体基板を露出
する如くにパターニングされた絶縁膜上に、該半
導体基板とほぼ等しい光ビーム反射係数をもつた
材料の層を形成し、しかる後に光ビーム照射を行
うことを特徴とする半導体装置の製造方法。1. In a heat treatment consisting of irradiating a light beam to activate impurities implanted into a semiconductor substrate, the semiconductor substrate and 1. A method of manufacturing a semiconductor device, comprising forming layers of materials having substantially equal light beam reflection coefficients, and then irradiating with a light beam.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6170981A JPS57176719A (en) | 1981-04-23 | 1981-04-23 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6170981A JPS57176719A (en) | 1981-04-23 | 1981-04-23 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57176719A JPS57176719A (en) | 1982-10-30 |
| JPS6364892B2 true JPS6364892B2 (en) | 1988-12-14 |
Family
ID=13179023
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6170981A Granted JPS57176719A (en) | 1981-04-23 | 1981-04-23 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57176719A (en) |
-
1981
- 1981-04-23 JP JP6170981A patent/JPS57176719A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57176719A (en) | 1982-10-30 |
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