JPS62199067A - Manufacture of semiconductor memory device - Google Patents

Abstract

PURPOSE:To improve the withstanding voltage of a second gate oxide film without decreasing a yield rate, by growing a second non-single crystal silicon film, in which impurities are not doped, on a second oxide insulating film forming an EPROM, and performing the thermal oxidation of said silicon film. CONSTITUTION:On a second oxide insulating film 30 of a second gate oxide film of an EPROM, which is formed on a silicon substrate 1, a second non-single crystal silicon film, in which impurities are not doped, is provided. The thermal oxidation of said film is performed, and a third oxide insulating film 31 is grown. When the films 30 and 31 are made to be second gate oxide films, the withstanding voltage of the second gate oxide films is improved without decreasing the yield rate. Thus the EPROM having high memory keeping performance can be formed.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to an improvement in a method of manufacturing a semiconductor memory device.

[Prior art and its problems] Conventionally, E PROM (E rasab) as shown in FIG.
leProgrammable Read 0nly
Memory) is manufactured as follows.

First, a first insulating film is formed on the surface of an island-shaped element region surrounded by a field oxide film (not shown) of a P-type silicon substrate 1, and then a first polycrystalline silicon film that will become a floating gate is deposited on the entire surface. do. Next, this first polycrystalline silicon film is doped with phosphorus using, for example, POCI 3 as a diffusion source, and then a portion of it is selectively etched. Subsequently, a second thermal oxide film is formed on the surface of the first polycrystalline silicon film by performing low-temperature oxidation at a temperature of 1000°C or less using, for example, oxygen or water vapor as an oxidizing gas.
A second polycrystalline silicon film to serve as a control gate is deposited over the entire surface and doped with impurities.

Next, the second polycrystalline silicon film, the second thermal oxide film, the first polycrystalline silicon film, and the first insulating film are sequentially etched by photolithography to form a first gate insulating film with a thickness of 2.7 mm.
- forming gate 3, second gate oxide film 4 and control gate 5. Subsequently, using these as a mask, N-type impurities such as AS are ion-implanted. Subsequently, thermal oxidation is performed to form a post-oxide film 6 on the surface and side surfaces of the control gate 5, the side surfaces of the 70-ting gate 3, and the exposed surface of the substrate 1, and to activate the As ion-implanted layer. Form N++ source and drain regions 7.8. Next, after depositing a PSG film 9 as a passivation film on the entire surface, this PSG II 9 and a part of the post-oxidation film 6 were selectively etched to open a contact hole 10, and then an A hs i film was deposited on the entire surface. After that, patterning is performed to form a source electrode 11 and a drain forming electrode 12, and the EPRO
Manufacture M cell.

The above-mentioned EPROM cell is a device that performs writing by applying a high positive voltage to the N+ type drain region 8 and control gate 5 of the cell transistor to inject electrons into the floating gate 3.

However, if a high positive voltage is applied to the control gate 5 after writing, there is a drawback that the electrons injected into the 70-ting gate 3 can be handled by the control gate 5, and the memory may not be retained.

This is due to the breakdown voltage deterioration of the second gate oxide film 4.
The reason for this is thought to be as follows.

In other words, since the first polycrystalline silicon film that becomes the floating gate is composed of grains having various plane orientations, the surface has irregularities (5 urfaseasperi).
ty). When this is oxidized by low-temperature oxidation at 1000°C or less to form a second gate oxide 1114, 7
Irregularities occur at the boundary between the 0-ting gate 3 and the second gate oxide film 4. This is the second gate oxidation g! This causes deterioration of the breakdown voltage of No. 4.

This phenomenon can be alleviated by high-temperature processes of 1,100°C or higher, but high-temperature processes change the position of pre-formed bonds and cause wafer warping, which deteriorates device performance and reduces yield. This cannot be an effective countermeasure. Furthermore, as the degree of integration increases, the area of the gate also increases, increasing the probability that defects will occur in the oxide film due to contamination from the manufacturing environment, and leakage current will occur through these defects, deteriorating device performance.

[Object of the Invention] The present invention has been made in view of the above circumstances, and provides a semiconductor memory device that improves the withstand voltage of the second gate oxide film and has good memory retention characteristics without reducing the yield of the device. The aim is to provide a method for manufacturing.

[Summary of the Invention] A method for manufacturing a semiconductor memory device of the present invention includes forming a first insulating film on the surface of an element region of a semiconductor substrate of a first conductivity type, and manufacturing a first non-single crystal silicon film doped with impurities over the entire surface. After forming the film, a second oxide insulating film is formed thereon, a second non-single crystal silicon film is formed without doping with impurities, and this second non-single crystal silicon film is thermally oxidized. The main idea is to convert the silicon into a third oxide insulating film, then form a third non-single-crystal silicon film, and then form a second conductivity type source and drain by buttering and impurity ion implantation. It is.

As described above, by forming the third oxide insulating film which is obtained by thermally oxidizing and converting the second non-single crystal silicon film, the second oxide insulating film on the first non-single crystal silicon film is Since the third oxide insulating film covers the defects, the overall defect density is reduced. Further, since phosphorus or the like is not doped into the second non-single crystal silicon film, phosphorus or the like is not incorporated into the third oxide insulating film, so that an oxide film with fewer defects is formed.

This effect makes it possible to reduce the leakage current of the second gate oxide between the 70-ring gate and the control gate.

[Examples of the Invention] Examples of the manufacturing method of the present invention are shown below in Figures 2 <a) to (h).
). FIG. 1 shows the structure of a semiconductor device obtained by the manufacturing method of the present invention.

First, a normal selective oxidation technique is applied to the surface of a P-type silicon substrate 21 having a specific resistance of 10 to 20 Ω-Cm and a plane orientation of (911). A field oxide film 22 with a thickness of 1.2 μm was formed (as shown in FIG. 2(a)).

Next, thermal oxidation was performed to form a first insulating film 23 with a thickness of 500 μm on the surface of the island-shaped element region surrounded by the field oxide film 22. Subsequently, a first polycrystalline silicon film 24 having a thickness of 3500 mm was deposited over the entire surface by CVD. Continuing, P
First polycrystalline silicon g! using OCI 3 as a diffusion source! 2
4 was doped with phosphorus to set ρ to −15Ω/mouth. Next, thermal oxidation was performed for 10 minutes in an A gas at 1000° C. and 50% 02rIA to form a second oxide insulating film 25 of 200 μm (as shown in FIG. 2(b)).

Next, a second polycrystalline silicon film 1 with a thickness of 100 was applied to the entire surface.
11326 was deposited. This polycrystalline silicon film has
No impurity is doped (as shown in FIG. 2(C)).

Next, this second polycrystalline silicon r! 26 to 100
Thermal oxidation was performed in Ar gas at 0° C. and 0.211° C. to change all of the second polycrystalline silicon film 26 into a third oxide insulator 11A27 (as shown in FIG. 2(d)).

Next, a third polycrystalline silicon Ml which becomes a control gate with a film thickness of 3500×, ρ, = 20 Ω/hole is deposited on the entire surface.
28 were deposited. Subsequently, a photoresist pattern 29 was partially formed on the third polycrystalline silicon film 28 by photolithography (as shown in FIG. 2(e)).

Next, using this photoresist pattern 29 as a mask, the third polycrystalline silicon film 28 and the third oxide insulating film 2 are formed.
7. Sequentially pattern the second oxide insulator 125, first polycrystalline silicon 1124, and first insulator 1123 to form the first gate insulator 2 and floating gate 3.
, a control gate 5, and a second gate oxide film 30, 31 between the floating gate and the control gate (as shown in FIG. 2(f)).

Next, use these as masks and apply energy to AS4' 6
Ion implantation was performed under the conditions of 0 keV and a dose of 2.5X 10" 0N-2. Subsequently, after removing the photoresist pattern 29, thermal oxidation was performed at 1000°C to form a post-oxide film 32 with a thickness of 500X. At this time, the As ion-implanted layer was activated and N+ type source and drain regions 7.8 with ρ5-30 to 40Ω/gate and X5 = 0.4 μm were formed.Subsequently, the thickness of the passivation film was 0.8 μm of PSGII!J33 was deposited (as shown in the same figure (g)).

Next, a contact hole 10 is formed by selectively etching a part of the PSGg 133 and post-oxidation 11132, and after depositing Al-8ill with a thickness of 1.0 μm on the entire surface, the source electrode 11 is formed by buttering. , the drain electrode 12 is formed and an EPROM cell is manufactured (as shown in FIG. 3(h)).

According to the manufacturing method of the present invention, FIG.
After depositing the second polycrystalline silicon film 26 in step As seen in the resulting semiconductor memory device of FIG. 1, the second gate oxide film 30,31 between the floating gate 3 and the control gate 5 has a second oxide insulation layer 1m1125 and a third oxide insulation layer g! It consists of 27,
The second gate oxidation process can significantly reduce defect density as a whole.

For example, as shown in FIG.
The breakdown voltage of the second gate oxide film when it is composed of only
FIG. 1B also shows the second gate oxide film in the case where the second gate oxide film is composed of the second oxide insulating film 30 and the 3M insulator 131 according to the above embodiment (see FIG. 1). The breakdown voltage is shown respectively. As is clear from these figures, the breakdown voltage of the second gate oxide film formed by the method of the above embodiment is significantly improved, and the variation in breakdown voltage is also extremely small. As a result, even if a high positive voltage is applied to the control gate 5 after writing to the EPROM cell shown in FIG. 1, the memory can be maintained well. Further, since a low-temperature process is employed, there is no problem that the yield of semiconductor memory devices decreases due to wafer warping or the like.

In the above embodiment, polycrystalline silicon is used as the material for the floating gate 3 and the control gate 5, but the material is not limited to this, and amorphous silicon may also be used.

[Effects of the Invention] As detailed above, according to the method of manufacturing a semiconductor memory device of the present invention, there is no need to significantly change the conventional process.
A semiconductor memory device with improved memory retention characteristics and improved breakdown voltage of the second gate oxide film can be manufactured without increasing costs or decreasing device yield.

[Brief explanation of drawings]

FIG. 1 is a sectional view of an EPROM cell of the present invention, and FIG. 2 (
3(a) to 3(h) are cross-sectional views showing the manufacturing method of the EPROM cell in the embodiment of the present invention, FIG. b) is a histogram of breakdown voltage of the second gate oxide film formed by the method of the embodiment of the present invention, and FIG. 4 is a cross-sectional view of a conventional EPROM. 1.21... Silicon substrate, 2... First gate insulating film, 3... Floating gate, 4... Second gate oxide film, 5... Control gate, 6
...Post-oxidation film, 7.8...N+ type source, drain electrode, 9.33... Passivation film, 1
0... Contact hole, 11... Source electrode,
12... Drain electrode, 22... Field oxide film, 23... First insulating film, 24... First amorphous silicon film, 25... Second oxide insulating film, 26
... second amorphous silicon film, 27 ... third oxide insulating film, 28 ... third non-single crystal silicon film,
29... Photoresist pattern, 30.31...
second gate oxide film, 32...post oxide film; Patent applicant Toshiba Corporation Figure 1 Figure 2 Figure 2

Claims (1)

[Claims] 1. After forming a first insulating film on the surface of an element region of a semiconductor substrate of a first conductivity type, forming a first non-single crystal silicon film doped with impurities over the entire surface; forming a second oxide insulating film on the silicon film;
forming a second non-single crystal silicon film not doped with impurities on the second oxide insulating film, and thermally oxidizing the second non-single crystal silicon film to convert it into a third oxide insulating film. a step of forming a third non-single-crystal silicon film on the entire surface of the third oxide insulating film; and a step of sequentially patterning these films and using this pattern as a mask to inject impurities of a second conductivity type into the semiconductor substrate. 1. A method of manufacturing a semiconductor memory device, comprising the step of forming source and drain regions of a second conductivity type by ion implantation.