JPS61256621A - 接着型半導体基板の製造方法 - Google Patents

接着型半導体基板の製造方法

Info

Publication number
JPS61256621A
JPS61256621A JP9750985A JP9750985A JPS61256621A JP S61256621 A JPS61256621 A JP S61256621A JP 9750985 A JP9750985 A JP 9750985A JP 9750985 A JP9750985 A JP 9750985A JP S61256621 A JPS61256621 A JP S61256621A
Authority
JP
Japan
Prior art keywords
bound
wafer
section
semiconductor substrate
bonded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9750985A
Other languages
English (en)
Japanese (ja)
Other versions
JPH044742B2 (enrdf_load_stackoverflow
Inventor
Yoshinori Natsume
嘉徳 夏目
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP9750985A priority Critical patent/JPS61256621A/ja
Publication of JPS61256621A publication Critical patent/JPS61256621A/ja
Publication of JPH044742B2 publication Critical patent/JPH044742B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
JP9750985A 1985-05-08 1985-05-08 接着型半導体基板の製造方法 Granted JPS61256621A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9750985A JPS61256621A (ja) 1985-05-08 1985-05-08 接着型半導体基板の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9750985A JPS61256621A (ja) 1985-05-08 1985-05-08 接着型半導体基板の製造方法

Publications (2)

Publication Number Publication Date
JPS61256621A true JPS61256621A (ja) 1986-11-14
JPH044742B2 JPH044742B2 (enrdf_load_stackoverflow) 1992-01-29

Family

ID=14194225

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9750985A Granted JPS61256621A (ja) 1985-05-08 1985-05-08 接着型半導体基板の製造方法

Country Status (1)

Country Link
JP (1) JPS61256621A (enrdf_load_stackoverflow)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6489346A (en) * 1987-09-29 1989-04-03 Sony Corp Semiconductor substrate
JPH0387012A (ja) * 1989-06-21 1991-04-11 Fujitsu Ltd 接合ウエハおよびその製造方法
US6583029B2 (en) 2000-03-29 2003-06-24 Shin-Etsu Handotai Co., Ltd. Production method for silicon wafer and SOI wafer, and SOI wafer
JP2010105141A (ja) * 2008-10-31 2010-05-13 Naoetsu Electronics Co Ltd 半導体接合ウエーハの製造方法
WO2012014136A1 (en) 2010-07-30 2012-02-02 Memc Electronic Materials, Inc. Semiconductor and solar wafers and method for processing same
WO2012014137A2 (en) 2010-07-30 2012-02-02 Memc Electronic Materials, Inc. Grinding tool for trapezoid grinding of a wafer
WO2012014138A1 (en) 2010-07-30 2012-02-02 Memc Electronic Materials, Inc. Semiconductor and solar wafers
JP2013115307A (ja) * 2011-11-30 2013-06-10 Sumitomo Electric Ind Ltd Ｉｉｉ族窒化物複合基板の製造方法

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6489346A (en) * 1987-09-29 1989-04-03 Sony Corp Semiconductor substrate
JPH0387012A (ja) * 1989-06-21 1991-04-11 Fujitsu Ltd 接合ウエハおよびその製造方法
US6583029B2 (en) 2000-03-29 2003-06-24 Shin-Etsu Handotai Co., Ltd. Production method for silicon wafer and SOI wafer, and SOI wafer
JP2010105141A (ja) * 2008-10-31 2010-05-13 Naoetsu Electronics Co Ltd 半導体接合ウエーハの製造方法
WO2012014136A1 (en) 2010-07-30 2012-02-02 Memc Electronic Materials, Inc. Semiconductor and solar wafers and method for processing same
WO2012014137A2 (en) 2010-07-30 2012-02-02 Memc Electronic Materials, Inc. Grinding tool for trapezoid grinding of a wafer
WO2012014138A1 (en) 2010-07-30 2012-02-02 Memc Electronic Materials, Inc. Semiconductor and solar wafers
US8310031B2 (en) 2010-07-30 2012-11-13 Memc Electronic Materials, Inc. Semiconductor and solar wafers
JP2013115307A (ja) * 2011-11-30 2013-06-10 Sumitomo Electric Ind Ltd Ｉｉｉ族窒化物複合基板の製造方法

Also Published As

Publication number Publication date
JPH044742B2 (enrdf_load_stackoverflow) 1992-01-29

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