JPS61256621A - Production of bound-type semiconductor substrate - Google Patents
Production of bound-type semiconductor substrateInfo
- Publication number
- JPS61256621A JPS61256621A JP9750985A JP9750985A JPS61256621A JP S61256621 A JPS61256621 A JP S61256621A JP 9750985 A JP9750985 A JP 9750985A JP 9750985 A JP9750985 A JP 9750985A JP S61256621 A JPS61256621 A JP S61256621A
- Authority
- JP
- Japan
- Prior art keywords
- bound
- wafer
- section
- semiconductor substrate
- bonded
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 239000000758 substrate Substances 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 238000000034 method Methods 0.000 claims abstract description 16
- 238000005498 polishing Methods 0.000 claims description 6
- 230000002093 peripheral effect Effects 0.000 claims description 5
- 238000003825 pressing Methods 0.000 claims description 4
- 239000000853 adhesive Substances 0.000 claims description 3
- 230000001070 adhesive effect Effects 0.000 claims description 3
- 235000012431 wafers Nutrition 0.000 abstract description 39
- 230000007547 defect Effects 0.000 abstract description 2
- 239000004575 stone Substances 0.000 abstract 2
- 238000009792 diffusion process Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 238000007665 sagging Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 231100000989 no adverse effect Toxicity 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は接着型半導体基板の製造方法に関するもので、
特に大容昆のパワートランジスタの製造に使用されるも
のである。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for manufacturing an adhesive semiconductor substrate,
In particular, it is used in the production of Dayongkun's power transistors.
(発明の技術的背景とその問題点)
半導体装置を製造するにはシリコンウェーハを用い拡散
、酸化、エツチング等をくり返すウェーハプロセスによ
りトランジスタの所定の能動領域を形成している。特に
バイポーラ型のトランジスタのうち耐圧および飽和電流
容量の大きいものについては能動領域における動作を確
実にするために、濃度の高い不純物拡散領域である埋込
拡散領域をまず形成し、その上に能動領域となる拡散領
域を形成するようにしている。しかしながらこの方法で
は長時間の拡散及び堆積の工程を必要とし、また製造の
安定性に欠ける。(Technical background of the invention and its problems) In manufacturing semiconductor devices, silicon wafers are used and predetermined active regions of transistors are formed through a wafer process that repeats diffusion, oxidation, etching, etc. In particular, for bipolar transistors with high breakdown voltage and saturation current capacity, in order to ensure operation in the active region, a buried diffusion region, which is a high concentration impurity diffusion region, is first formed, and then the active region A diffusion region is formed such that However, this method requires lengthy diffusion and deposition steps and lacks manufacturing stability.
このため、拡散濃度の異なる2枚のウェーハを用い、こ
れを貼り合せて1枚のウェーハとする技術が提案されて
いる。すなわち400〜600μmの厚さを有する2枚
のウェーハを例えば第4図(a)に示すように一方のウ
ェーハ1には高濃度のリン拡散を行ってn+とじ、他方
のウェーハ2には濃度の低いリン拡散を行ってn−とじ
、これら双方の少なくとも片面にラッピングおよびポリ
ッシングをほどこして鏡面とし、この鏡面同士を圧力を
かけて接触させることによって両者の原子間引力で強固
な接着を実現している。この接着後に高m(1100℃
)で2Hの熱処理を行なうことにより境界面での接着強
度はさらに増加する。For this reason, a technique has been proposed in which two wafers having different diffusion concentrations are used and bonded together to form one wafer. In other words, two wafers having a thickness of 400 to 600 μm are processed, for example, as shown in FIG. N-binding is performed with low phosphorus diffusion, lapping and polishing are applied to at least one side of both to create a mirror surface, and by applying pressure and bringing these mirror surfaces into contact, strong adhesion is achieved by the atomic attraction between the two. There is. After this adhesion, high m (1100℃)
) The adhesion strength at the interface is further increased by 2H heat treatment.
次に、能動領域として使用されるn−ウェーハ2の基板
厚を80〜100μmの厚さになるように研削、ラッピ
ング、ポリッシングを行って減少させ、これを用いてウ
ェーハプロセスを行ない半導体装置を製造する。Next, the substrate thickness of the n-wafer 2 used as an active region is reduced by grinding, lapping, and polishing to a thickness of 80 to 100 μm, and a wafer process is performed using this to manufacture semiconductor devices. do.
しかしながらこのような貼り合せ加工ではウェーへの破
損が多いという問題がある。すなわち、第4図(a)(
b)に示すように、貼り合せ前の各ウェーハは鏡面仕上
げの際のポリッシング等で平坦度が低下し、特に貼り合
わせ面の周縁部3にダレ4を生じているため接着時に接
着が行なわれていない。このため貼り合わせ強度が弱く
なり厚さ減少のためのラッピングの際第5図(a)の正
面図および第5図(1))の斜視図に示されるように割
れ5、欠け6、はがれ等が生じて歩留りが低下すること
となる。従って半導体装置を製造するための有効部分が
減少し、あるいは正常な接着が行われた部分にも影響を
及ぼして特性および信頼性を低下させることとなる。However, this type of bonding process has a problem in that the wafers are often damaged. That is, Fig. 4(a) (
As shown in b), the flatness of each wafer before bonding has decreased due to polishing during mirror finishing, and sagging 4 has occurred particularly at the peripheral edge 3 of the bonding surface, so the bonding is not performed at the time of bonding. Not yet. For this reason, the bonding strength becomes weaker, and when wrapping to reduce the thickness, cracks 5, chips 6, peeling, etc. occur as shown in the front view of Figure 5 (a) and the perspective view of Figure 5 (1)). occurs, resulting in a decrease in yield. Therefore, the effective area for manufacturing the semiconductor device is reduced, or the area where normal adhesion is performed is affected, resulting in deterioration of characteristics and reliability.
本発明はこのような問題を解決するためになされたもの
で歩留りが良く、かつ信頼性の高い接着型半導体基板を
提供することを目的とする。The present invention was made to solve these problems, and an object of the present invention is to provide a bonded semiconductor substrate with a high yield and high reliability.
〔発明の概要)
上記目的達成のため本発明においては2枚の半導体基板
の少なくとも片面をそれぞれ鏡面研磨する工程と、この
鏡面研磨面を接触させて圧力をかけることにより2枚の
半導体基板を接着させる工程と、この接着された半導体
基板の周縁部を研削し未接着部を除去する工程と、を備
えるようにしており、強固に接着された部分のみが残る
ことにより、その後の厚さ調整のための加工において欠
陥の発生がなく、歩留りおよび信頼性が向上する。[Summary of the Invention] In order to achieve the above object, the present invention includes a process of mirror-polishing at least one side of two semiconductor substrates, and bonding the two semiconductor substrates by bringing the mirror-polished surfaces into contact and applying pressure. This process includes a step of grinding the periphery of the bonded semiconductor substrate to remove the unbonded portion, and by leaving only the strongly bonded portion, it is easier to adjust the thickness later. No defects occur during processing, improving yield and reliability.
以下本発明の一実施例を図面を参照して詳細に説明する
。An embodiment of the present invention will be described in detail below with reference to the drawings.
従来例と同様に、片面が鏡面仕上げされた2枚のウェー
ハ1,2.が圧力と湿度を加えられて鏡面同士を接着さ
れる。この時接着面の最外周部ではそれぞれの基板のダ
レにより未接着部3が生じている。As in the conventional example, two wafers 1, 2 . The mirror surfaces are glued together by applying pressure and humidity. At this time, an unbonded portion 3 is generated at the outermost periphery of the bonded surface due to sagging of each substrate.
このような接着ウェーハ10は円筒研削盤に取り付けら
れ第1図の正面図に示されるようにその端面を回転砥石
11の端面と当接さU、この砥石11を接着ウェーへの
中心方向に移動させることにより研削が行われる。この
砥石11は平坦な円筒面11aの両側に角度をもって外
周方向に立ち上る傾斜部11b、11Cを備えている。Such a bonded wafer 10 is mounted on a cylindrical grinder, and as shown in the front view of FIG. Grinding is performed by This grindstone 11 has inclined portions 11b and 11C that rise at an angle toward the outer circumference on both sides of a flat cylindrical surface 11a.
平坦部11bの幅は接着ウェーへの厚さよりわずかに小
さくなっており、接着ウェーへの両面周縁端部は傾斜部
11b、11cにそれぞれ当接することになり、直径の
減少と共に面取り部7が形成されることになる。The width of the flat portion 11b is slightly smaller than the thickness of the bonded wafer, and the peripheral edges of both sides of the bonded wafer come into contact with the sloped portions 11b and 11c, respectively, and as the diameter decreases, a chamfered portion 7 is formed. will be done.
この研削の際、砥石11は例えば350 rpmで回転
をしており、研削される接着ウェーハ10にはこれと逆
の回転が与えられる。接着ウェーハの周辺部にある非接
着部3が除去された位置で研削は終了する。なお実際の
製造時に量産工程にのるウェーハの大きさはあらかじめ
定められているため直径はそのような大きさに調節され
ることが多く、例えば4インチ(101,6m)ウェー
ハを接着してなる接着ウェーハにおいては周囲の非接着
部を除去して3インチ(76,2a+s+)ウェーハに
仕上げられる。During this grinding, the grindstone 11 is rotating at, for example, 350 rpm, and the bonded wafer 10 being ground is given a rotation opposite to this. Grinding ends at a position where the non-bonded portion 3 at the periphery of the bonded wafer is removed. Note that during actual manufacturing, the size of the wafers used in the mass production process is determined in advance, so the diameter is often adjusted to that size.For example, 4-inch (101,6 m) wafers are bonded together. The bonded wafer is finished into a 3-inch (76,2a+s+) wafer by removing the surrounding non-bonded portion.
また研削装置には、研削されるウェーハに研削砥石が追
従するように油圧並びに空気圧を併用した砥石追従アー
ムが備えられている。The grinding device is also equipped with a grindstone following arm that uses both hydraulic pressure and air pressure so that the grindstone follows the wafer being ground.
このようにして未接着部が除去された接着つ工−ハ10
′は第2図の正面図に示されるようにウェーハ1′およ
び2′の全面で完全な接着が行われ、次の工程で第3図
の正面図に示されるようにウェーハ2′表面のラッピン
グおよびポリッシングが行なわれて厚さが減少したウェ
ーハ2″となり、その要この完成接着ウェーハ10”を
用いてウェーハプロセスが行なわれる。Glued joint with unbonded parts removed in this way - C10
As shown in the front view of FIG. 2, complete adhesion is performed on the entire surface of wafers 1' and 2', and in the next step, the surface of wafer 2' is lapped as shown in the front view of FIG. Then, polishing is performed to obtain a wafer 2'' whose thickness has been reduced, and a wafer process is performed using this completed bonded wafer 10''.
以上の実施例では接着される2枚のウェーハの厚さをほ
ぼ同じ厚さとしたが、接着型ウェーへの完成俊に行なわ
れる厚さ減少のための加工を容易にするために厚さを変
え、例えば一方を500μm、他方を300μmの厚さ
にして接着を行なうことができる。In the above embodiments, the two wafers to be bonded were made to have approximately the same thickness, but the thicknesses were changed to facilitate processing for reducing the thickness as soon as the bonded wafer was completed. For example, bonding can be performed with one side having a thickness of 500 μm and the other side having a thickness of 300 μm.
また、実施例では面取り加工を未接着部の除去加工とと
もに行なっているが、これらの加工を分離することがで
きる。Further, in the embodiment, the chamfering process is performed together with the process of removing the unbonded portion, but these processes can be separated.
以上のように本発明によれば接着された2枚のウェーハ
よりなる接着型ウェーハの周辺部を研削して未接着部を
除去するようにしているので、その後に行なわれるラッ
ピング等において欠(プ、割れ、はがれ等が生じず、歩
留りが向上Jるほか正常な接着部への悪影響がなくなり
その後に形成された半導体装置の信頼性の向上を図るこ
とができる。As described above, according to the present invention, the periphery of a bonded wafer made up of two bonded wafers is ground to remove the unbonded area, so that there are no gaps in the wafers that are left unbonded during subsequent lapping, etc. , cracking, peeling, etc. do not occur, the yield is improved, and there is no adverse effect on normal bonded parts, making it possible to improve the reliability of semiconductor devices formed thereafter.
第1図は本発明による接着ウェーへの製造方法を示す説
明図、第2図は未接着部を除去した様子を示す正面図、
第3図は本発明により得られた接着型ウェーハの正面図
、第4図は従来の接着型「ウェーハの接着後の様子を示
す説明図、第5図は従来の接着型ウェーハにおいて厚さ
調整加工を行なったときの問題点を示す説明図である。
1.1’ 、2.2’ 、2″・・・ウェーハ、3・・
・未接着部、4・・・ダレ、7・・・面取り部、10.
10’10”・・・接着型ウェーハ、11・・・研削砥
石。FIG. 1 is an explanatory diagram showing the method of manufacturing a bonded wafer according to the present invention, and FIG. 2 is a front view showing the state where the unbonded part is removed.
Fig. 3 is a front view of a bonded wafer obtained by the present invention, Fig. 4 is an explanatory diagram showing the state of a conventional bonded wafer after bonding, and Fig. 5 is a thickness adjustment in a conventional bonded wafer. It is an explanatory diagram showing problems when processing. 1.1', 2.2', 2''... wafer, 3...
- Unbonded part, 4... Sag, 7... Chamfered part, 10.
10'10"...adhesive wafer, 11...grinding wheel.
Claims (1)
研磨する工程と、 この鏡面研磨面を接触させて圧力をかけることにより前
記2枚の半導体基板を接着させる工程と、この接着され
た半導体基板の周縁部を研削し未接着部を除去する工程
と、 必要に応じ全体の厚さを調整する工程と、 を備えた接着型半導体基板の製造方法。 2、半導体基板が円形の半導体ウェーハである特許請求
の範囲第1項記載の接着型半導体基板の製造方法。 3、研削が周縁部の未接着部の除去とともに周縁端部の
鋭部を除去するように行われる特許請求の範囲第1項記
載の接着型半導体基板の製造方法。[Claims] A step of mirror-polishing at least one side of one or two semiconductor substrates, a step of bonding the two semiconductor substrates by bringing the mirror-polished surfaces into contact and applying pressure; A method for manufacturing a bonded semiconductor substrate, comprising: grinding the peripheral edge of the bonded semiconductor substrate and removing the unbonded portion; and adjusting the overall thickness as necessary. 2. The method for manufacturing an adhesive semiconductor substrate according to claim 1, wherein the semiconductor substrate is a circular semiconductor wafer. 3. The method of manufacturing a bonded semiconductor substrate according to claim 1, wherein the grinding is performed to remove the unbonded portion of the peripheral edge and also the sharp portion of the peripheral edge.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9750985A JPS61256621A (en) | 1985-05-08 | 1985-05-08 | Production of bound-type semiconductor substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9750985A JPS61256621A (en) | 1985-05-08 | 1985-05-08 | Production of bound-type semiconductor substrate |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS61256621A true JPS61256621A (en) | 1986-11-14 |
JPH044742B2 JPH044742B2 (en) | 1992-01-29 |
Family
ID=14194225
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9750985A Granted JPS61256621A (en) | 1985-05-08 | 1985-05-08 | Production of bound-type semiconductor substrate |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61256621A (en) |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6489346A (en) * | 1987-09-29 | 1989-04-03 | Sony Corp | Semiconductor substrate |
EP0413547A2 (en) * | 1989-08-17 | 1991-02-20 | Shin-Etsu Handotai Company Limited | Process for producing semiconductor device substrate |
JPH0387012A (en) * | 1989-06-21 | 1991-04-11 | Fujitsu Ltd | Adhered wafer and manufacture thereof |
US6583029B2 (en) | 2000-03-29 | 2003-06-24 | Shin-Etsu Handotai Co., Ltd. | Production method for silicon wafer and SOI wafer, and SOI wafer |
JP2010105141A (en) * | 2008-10-31 | 2010-05-13 | Naoetsu Electronics Co Ltd | Manufacturing method for semiconductor-bonded wafer |
WO2012014137A2 (en) | 2010-07-30 | 2012-02-02 | Memc Electronic Materials, Inc. | Grinding tool for trapezoid grinding of a wafer |
WO2012014138A1 (en) | 2010-07-30 | 2012-02-02 | Memc Electronic Materials, Inc. | Semiconductor and solar wafers |
WO2012014136A1 (en) | 2010-07-30 | 2012-02-02 | Memc Electronic Materials, Inc. | Semiconductor and solar wafers and method for processing same |
JP2013115307A (en) * | 2011-11-30 | 2013-06-10 | Sumitomo Electric Ind Ltd | Method for manufacturing group iii nitride composite substrate |
-
1985
- 1985-05-08 JP JP9750985A patent/JPS61256621A/en active Granted
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6489346A (en) * | 1987-09-29 | 1989-04-03 | Sony Corp | Semiconductor substrate |
JP2535957B2 (en) * | 1987-09-29 | 1996-09-18 | ソニー株式会社 | Semiconductor substrate |
JPH0387012A (en) * | 1989-06-21 | 1991-04-11 | Fujitsu Ltd | Adhered wafer and manufacture thereof |
EP0413547A2 (en) * | 1989-08-17 | 1991-02-20 | Shin-Etsu Handotai Company Limited | Process for producing semiconductor device substrate |
US6583029B2 (en) | 2000-03-29 | 2003-06-24 | Shin-Etsu Handotai Co., Ltd. | Production method for silicon wafer and SOI wafer, and SOI wafer |
JP2010105141A (en) * | 2008-10-31 | 2010-05-13 | Naoetsu Electronics Co Ltd | Manufacturing method for semiconductor-bonded wafer |
WO2012014137A2 (en) | 2010-07-30 | 2012-02-02 | Memc Electronic Materials, Inc. | Grinding tool for trapezoid grinding of a wafer |
WO2012014138A1 (en) | 2010-07-30 | 2012-02-02 | Memc Electronic Materials, Inc. | Semiconductor and solar wafers |
WO2012014136A1 (en) | 2010-07-30 | 2012-02-02 | Memc Electronic Materials, Inc. | Semiconductor and solar wafers and method for processing same |
US8310031B2 (en) | 2010-07-30 | 2012-11-13 | Memc Electronic Materials, Inc. | Semiconductor and solar wafers |
JP2013115307A (en) * | 2011-11-30 | 2013-06-10 | Sumitomo Electric Ind Ltd | Method for manufacturing group iii nitride composite substrate |
Also Published As
Publication number | Publication date |
---|---|
JPH044742B2 (en) | 1992-01-29 |
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