JPS6489346A - Semiconductor substrate - Google Patents

Semiconductor substrate

Info

Publication number
JPS6489346A
JPS6489346A JP24501487A JP24501487A JPS6489346A JP S6489346 A JPS6489346 A JP S6489346A JP 24501487 A JP24501487 A JP 24501487A JP 24501487 A JP24501487 A JP 24501487A JP S6489346 A JPS6489346 A JP S6489346A
Authority
JP
Japan
Prior art keywords
substrate
outer peripheral
peripheral end
semiconductor
standard size
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP24501487A
Other languages
Japanese (ja)
Other versions
JP2535957B2 (en
Inventor
Nobuyuki Izawa
Hiroshi Sato
Hisao Hayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP62245014A priority Critical patent/JP2535957B2/en
Publication of JPS6489346A publication Critical patent/JPS6489346A/en
Application granted granted Critical
Publication of JP2535957B2 publication Critical patent/JP2535957B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Local Oxidation Of Silicon (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To reduce the waste of a semiconductor material by disposing the outer peripheral end of one substrate inside the outer peripheral end of the other substrate in a semiconductor substrate in which two semiconductor substrates are bonded. CONSTITUTION:First and second semiconductor substrates 1, 2 are bonded, and at least the outer peripheral end of the substrate 1 is disposed inside that of the substrate 2. According to a substrate 3 of this construction, the substrate 2 has a specification of standard size by allowing at least part of the outer peripheral end to remain. Accordingly, the outer peripheral end of only the substrate 1 is removed to have a small diameter, thereby avoiding an irregular stepwise difference due to a gap between the substrates 1 and 3 or displacement of them. Thus, a problem of contamination in steps of manufacturing a semiconductor device can be avoided. Further, since the entirety has a diameter of standard size, an apparatus for manufacturing in standard size can be employed, thereby minimizing the waste of a semiconductor material.
JP62245014A 1987-09-29 1987-09-29 Semiconductor substrate Expired - Lifetime JP2535957B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62245014A JP2535957B2 (en) 1987-09-29 1987-09-29 Semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62245014A JP2535957B2 (en) 1987-09-29 1987-09-29 Semiconductor substrate

Publications (2)

Publication Number Publication Date
JPS6489346A true JPS6489346A (en) 1989-04-03
JP2535957B2 JP2535957B2 (en) 1996-09-18

Family

ID=17127292

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62245014A Expired - Lifetime JP2535957B2 (en) 1987-09-29 1987-09-29 Semiconductor substrate

Country Status (1)

Country Link
JP (1) JP2535957B2 (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03250616A (en) * 1990-02-28 1991-11-08 Shin Etsu Handotai Co Ltd Bonded wafer and its manufacture
JPH0590545A (en) * 1991-09-30 1993-04-09 Shin Etsu Handotai Co Ltd Soi substrate and manufacture thereof
US5918139A (en) * 1997-01-31 1999-06-29 Shin Etsu Handotai Co., Ltd. Method of manufacturing a bonding substrate
EP0964436A2 (en) * 1998-06-04 1999-12-15 Shin-Etsu Handotai Company Limited Method for manufacturing SOI wafer and SOI wafer
JP2004281878A (en) * 2003-03-18 2004-10-07 Seiko Epson Corp Method for manufacturing semiconductor substrate, semiconductor substrate to be manufactured by the method, electro-optical device, and electronic apparatus
JP2009071128A (en) * 2007-09-14 2009-04-02 Naoetsu Electronics Co Ltd Method of manufacturing semiconductor-bonded wafer
EP2259301A3 (en) * 2003-10-14 2010-12-22 S.O.I. Tec Silicon on Insulator Technologies Method for preparing and assembling substrates
US8530331B2 (en) 2006-04-10 2013-09-10 Commissariat A L'energie Atomique Process for assembling substrates with low-temperature heat treatments

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4066889B2 (en) 2003-06-09 2008-03-26 株式会社Ｓｕｍｃｏ Bonded substrate and manufacturing method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54116888A (en) * 1978-03-03 1979-09-11 Hitachi Ltd Manufacture of dielectric separate substrate
JPS61144839A (en) * 1984-12-18 1986-07-02 Toshiba Corp Bonding method for semiconductor wafer
JPS61256621A (en) * 1985-05-08 1986-11-14 Toshiba Corp Production of bound-type semiconductor substrate

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54116888A (en) * 1978-03-03 1979-09-11 Hitachi Ltd Manufacture of dielectric separate substrate
JPS61144839A (en) * 1984-12-18 1986-07-02 Toshiba Corp Bonding method for semiconductor wafer
JPS61256621A (en) * 1985-05-08 1986-11-14 Toshiba Corp Production of bound-type semiconductor substrate

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03250616A (en) * 1990-02-28 1991-11-08 Shin Etsu Handotai Co Ltd Bonded wafer and its manufacture
JPH0590545A (en) * 1991-09-30 1993-04-09 Shin Etsu Handotai Co Ltd Soi substrate and manufacture thereof
US5918139A (en) * 1997-01-31 1999-06-29 Shin Etsu Handotai Co., Ltd. Method of manufacturing a bonding substrate
EP0964436A2 (en) * 1998-06-04 1999-12-15 Shin-Etsu Handotai Company Limited Method for manufacturing SOI wafer and SOI wafer
EP0964436A3 (en) * 1998-06-04 2000-10-18 Shin-Etsu Handotai Company Limited Method for manufacturing SOI wafer and SOI wafer
US6534384B2 (en) 1998-06-04 2003-03-18 Shin-Etsu Handotai Co., Ltd. Method for manufacturing SOI wafer including heat treatment in an oxidizing atmosphere
JP2004281878A (en) * 2003-03-18 2004-10-07 Seiko Epson Corp Method for manufacturing semiconductor substrate, semiconductor substrate to be manufactured by the method, electro-optical device, and electronic apparatus
EP2259301A3 (en) * 2003-10-14 2010-12-22 S.O.I. Tec Silicon on Insulator Technologies Method for preparing and assembling substrates
EP2259301B1 (en) * 2003-10-14 2020-08-19 Soitec Method for preparing and assembling substrates
US8530331B2 (en) 2006-04-10 2013-09-10 Commissariat A L'energie Atomique Process for assembling substrates with low-temperature heat treatments
JP2009071128A (en) * 2007-09-14 2009-04-02 Naoetsu Electronics Co Ltd Method of manufacturing semiconductor-bonded wafer

Also Published As

Publication number Publication date
JP2535957B2 (en) 1996-09-18

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