JP2009071128A - Method of manufacturing semiconductor-bonded wafer - Google Patents
Method of manufacturing semiconductor-bonded wafer Download PDFInfo
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本発明は、半導体ウエーハ基板同士を接合して、半導体接合ウエーハを製造する方法に関する。
詳しくは、少なくとも２枚の半導体ウエーハを直接密着させ、これに熱処理を加えて接合させ、この接合された半導体ウエーハの外周に生じる未接合部を研削加工により除去する半導体接合ウエーハの製造方法に関する。
The present invention relates to a method of manufacturing a semiconductor bonded wafer by bonding semiconductor wafer substrates together.
More specifically, the present invention relates to a method for manufacturing a semiconductor bonded wafer in which at least two semiconductor wafers are directly adhered, bonded by heat treatment, and unbonded portions generated on the outer periphery of the bonded semiconductor wafer are removed by grinding.
従来、この種の半導体接合ウエーハの製造方法として、デバイスが作製される側のボンドウエーハと、支持基板となるベースウエーハとを用意し、これらボンドウエーハ及びベースウエーハ同士を清浄な雰囲気下で密着させ、その後、密着させたボンドウエーハとベースウエーハとを、例えば酸化性雰囲気下で固着熱処理を加えて接合させる技術があった。
しかし、このようにして接合された２枚のウエーハの外周は、各ウエーハの鏡面研磨によって外周部がダレた形状になるため、接着時にその部分が隙間となって未接合部を生じることがあった。
これを防止するため、接合後に、ボンドウエーハとベースウエーハの両方の外周部にある未接合部を面取り加工により除去し、そして、ボンドウエーハを所定の厚さにするために、平面研削加工を行い、更にその平面研削面を鏡面研磨して半導体接合ウエーハを完成させている（例えば、特許文献１参照）。
Conventionally, as a method of manufacturing this type of semiconductor bonding wafer, a bond wafer on the side where a device is manufactured and a base wafer to be a support substrate are prepared, and the bond wafer and the base wafer are brought into close contact with each other in a clean atmosphere. Thereafter, there has been a technique of bonding the bonded wafer and base wafer to each other by applying a fixing heat treatment in an oxidizing atmosphere, for example.
However, since the outer periphery of the two wafers joined in this way has a shape in which the outer periphery is sagged by mirror polishing of each wafer, there is a possibility that an unjoined part will be formed as a gap during bonding. It was.
To prevent this, after bonding, unbonded parts on the outer periphery of both the bond wafer and base wafer are removed by chamfering, and surface grinding is performed to make the bond wafer a predetermined thickness. Further, the surface ground surface is mirror-polished to complete a semiconductor bonded wafer (see, for example, Patent Document 1).
しかし乍ら、このような従来の半導体接合ウエーハの製造方法では、接合されたウエーハの外周に生じる未接合部を面取り加工により除去するため、次のような問題があった。
即ち、面取りの際、熱処理時に形成された比較的硬い酸化膜を研削することになるため、面取り治具の寿命が短くなり、これに対応するために面取り治具の研削砥石の番手を粗くして面取り加工を行っていたが、砥石の番手が粗いため、チッピングの原因となる加工歪みが生じるという問題があった。
それだけでなく、砥粒に起因する重金属汚染の虞もあった。
また、上記面取り加工に代えてアルカリ系エッチング剤によるエッチング処理を施すことにより未接合部を除去することも考えられるが、この場合には、エッチレートが遅いため、必要なエッチング量を確保するのに長い時間を要してしまい、生産性が低下するという問題があった。
However, such a conventional method for manufacturing a semiconductor bonded wafer has the following problems because a non-bonded portion generated on the outer periphery of the bonded wafer is removed by chamfering.
That is, when chamfering, the relatively hard oxide film formed during the heat treatment is ground, so the life of the chamfering jig is shortened. To cope with this, the count of the grinding wheel of the chamfering jig is roughened. However, since the count of the grindstone is rough, there is a problem that processing distortion that causes chipping occurs.
In addition, there was a risk of heavy metal contamination due to the abrasive grains.
In addition, it is conceivable to remove the unjoined portion by performing an etching treatment with an alkaline etching agent instead of the chamfering process, but in this case, the etching rate is slow, so that the necessary etching amount is ensured. However, it takes a long time to reduce productivity.
そこで、本発明のうち第一の発明は、研削部の加工歪みや研削部に残った重金属を取り除くことを目的としたものである。
第二の発明は、面取り部の加工歪みや面取り部に残った重金属を取り除くことを目的としたものである。
Accordingly, the first invention of the present invention aims to remove the processing distortion of the grinding part and the heavy metal remaining in the grinding part.
The second invention is intended to remove the processing distortion of the chamfered portion and the heavy metal remaining in the chamfered portion.
前述した目的を達成するために、本発明のうち第一の発明は、未接合部の除去後に、熱処理時にキャリアガスによって形成された酸化膜を半導体ウエーハの表裏両面に残したまま、前記研削加工による研削部をエッチング液でエッチング処理したことを特徴とするものである。
第二の発明は、第一の発明の構成に、前記研削加工による研削部が、面取り加工による面取り部である構成を加えたことを特徴とする。
In order to achieve the above-mentioned object, the first invention of the present invention is characterized in that after the unbonded portion is removed, the grinding process is performed while the oxide films formed by the carrier gas during the heat treatment are left on both the front and back surfaces of the semiconductor wafer. The grinding part is etched with an etching solution.
According to a second aspect of the present invention, in addition to the configuration of the first aspect of the present invention, a configuration in which the grinding portion by the grinding is a chamfered portion by chamfering is added.
本発明のうち第一の発明は、未接合部の除去後に、熱処理時にキャリアガスによって形成された酸化膜を半導体ウエーハの表裏両面に残したまま、研削加工による研削部をエッチング液でエッチング処理することにより、半導体ウエーハ表裏の酸化膜が保護膜として機能し、半導体ウエーハの表裏両面がエッチングされず、研削部のみが所定量エッチングされる。
従って、研削部の加工歪みや研削部に残った重金属を取り除くことができる。
その結果、接合されたウエーハの外周にある未接合部を面取り加工により除去する従来のものに比べ、短時間で研削部の加工歪み及び重金属を取り除くことができた。
また、従来のアルカリ系エッチング剤によるエッチング処理と比較して、品質・生産性・コストの改善が図れる。
According to the first aspect of the present invention, after removing the unbonded portion, the ground portion by grinding is etched with an etching solution while leaving the oxide films formed by the carrier gas at the time of heat treatment on both the front and back surfaces of the semiconductor wafer. As a result, the oxide films on the front and back sides of the semiconductor wafer function as protective films, and the front and back sides of the semiconductor wafer are not etched, and only the grinding part is etched by a predetermined amount.
Therefore, it is possible to remove processing distortion of the grinding part and heavy metal remaining in the grinding part.
As a result, it was possible to remove the processing distortion and heavy metal in the grinding portion in a shorter time compared to the conventional one in which the unjoined portion on the outer periphery of the bonded wafer was removed by chamfering.
In addition, quality, productivity, and cost can be improved as compared with the conventional etching process using an alkaline etching agent.
第二の発明は、未接合部の除去後に、熱処理時にキャリアガスによって形成された酸化膜を半導体ウエーハの表裏両面に残したまま、面取り加工による面取り部をエッチング液でエッチング処理することにより、半導体ウエーハ表裏の酸化膜が保護膜として機能し、半導体ウエーハの表裏両面がエッチングされず、面取り部のみが所定量エッチングされる。
従って、面取り部の加工歪みや面取り部に残った重金属を取り除くことができる。
その結果、接合されたウエーハの外周にある未接合部を面取り加工により除去する従来のものに比べ、短時間で面取り部の加工歪み及び重金属を取り除くことができた。
この方法を採用すれば、通常のシリコン基板の面取り形状の半導体接合ウエーハが製造でき、通常のシリコン基板と同じ扱いでデバイス作製工程にも投入できる。
また、従来のアルカリ系エッチング剤によるエッチング処理と比較して、品質・生産性・コストの改善が図れる。
According to a second aspect of the present invention, after removing the unbonded portion, the chamfered portion by chamfering is etched with an etching solution while leaving the oxide film formed by the carrier gas at the time of heat treatment on both the front and back surfaces of the semiconductor wafer. The oxide films on the front and back sides of the wafer function as protective films, and both the front and back sides of the semiconductor wafer are not etched, and only a chamfered portion is etched by a predetermined amount.
Accordingly, it is possible to remove processing distortion of the chamfered portion and heavy metal remaining in the chamfered portion.
As a result, it was possible to remove the processing distortion and heavy metal in the chamfered portion in a short time compared to the conventional one in which the unjoined portion on the outer periphery of the bonded wafer was removed by chamfering.
If this method is adopted, a semiconductor bonding wafer having a chamfered shape of a normal silicon substrate can be manufactured, and can be input into a device manufacturing process in the same manner as a normal silicon substrate.
In addition, quality, productivity, and cost can be improved as compared with the conventional etching process using an alkaline etching agent.
本発明の半導体接合ウエーハＡの製造方法の実施形態は、図１（ａ）〜（ｄ）に示す如く、貼り合わせる少なくとも２枚の半導体ウエーハ１，２の接合面１ａ，２ａを直接密着させ、これに所定温度の固着熱処理を加えて所望の接合強度に接合させ、この接合された半導体ウエーハ１，２の外周に生じる未接合部３を研削加工によって除去し、その後にエッチング処理を行って、該研削加工による研削部の加工歪みや研削部に残った重金属を取り除く方法である。 As shown in FIGS. 1 (a) to 1 (d), the embodiment of the method for manufacturing a semiconductor bonded wafer A of the present invention directly adheres the bonded surfaces 1a and 2a of at least two semiconductor wafers 1 and 2 to be bonded together. This is subjected to a fixing heat treatment at a predetermined temperature to be bonded to a desired bonding strength, the unbonded portion 3 generated on the outer periphery of the bonded semiconductor wafers 1 and 2 is removed by grinding, and then an etching process is performed. This is a method for removing the processing distortion of the grinding part due to the grinding and the heavy metal remaining in the grinding part.
詳しく説明すると、２枚の半導体ウエーハ１，２として、支持基板となるベースウエーハと、デバイスが作製される側のボンドウエーハを用意し、これらベースウエーハ１及びボンドウエーハ２の接合面１ａ，２ａを鏡面研磨し、その際に、これら接合面１ａ，２ａに形成されている自然酸化膜を除去することが好ましい。 More specifically, as the two semiconductor wafers 1 and 2, a base wafer serving as a support substrate and a bond wafer on the side on which a device is manufactured are prepared, and bonding surfaces 1a and 2a of the base wafer 1 and the bond wafer 2 are provided. It is preferable that the natural oxide film formed on the bonding surfaces 1a and 2a is removed by mirror polishing.
このように鏡面研磨された両ウエーハ１，２の接合面１ａ，２ａを、図１（ａ）に示す如く、清浄な雰囲気下で密接させる。
この時、密接させる様子を赤外線透過影像法によって未接着部分（ボイド）が無いことを確認しながら貼り合せることが好ましい。
The joining surfaces 1a and 2a of both wafers 1 and 2 thus mirror-polished are brought into close contact under a clean atmosphere as shown in FIG.
At this time, it is preferable to perform the bonding while confirming that there is no unbonded portion (void) by the infrared transmission image method.
その後、これら密接されたベースウエーハ１及びボンドウエーハ２の結合を強固にするために、図１（ｂ）に示す如く、酸化性雰囲気下で約１０００℃〜１２００℃、２時間程度の固着熱処理（結合熱処理）を行って、該接合面１ａ，２ａ同士を直接密着し、接合させる。 Thereafter, in order to strengthen the bonding between the intimate base wafer 1 and the bond wafer 2, as shown in FIG. 1 (b), an adhesion heat treatment (about 1000 ° C. to 1200 ° C. for about 2 hours in an oxidizing atmosphere) Bonding heat treatment) is performed, and the bonding surfaces 1a and 2a are directly adhered to each other and bonded.
それにより、半導体接合ウエーハＡが作製され、その外表面である接合後のベースウエーハ１及びボンドウエーハ２の表裏両面１ｂ，２ｂを含む全体に亘って、固着熱処理時のキャリアガスによって酸化膜４が形成される。 Thereby, the semiconductor bonding wafer A is manufactured, and the oxide film 4 is formed by the carrier gas at the time of the fixing heat treatment over the entire surface including both the front and back surfaces 1b and 2b of the bonded base wafer 1 and the bond wafer 2 which are the outer surfaces. It is formed.
また、接合前の鏡面研磨によってベースウエーハ１及びボンドウエーハ２の外周部は、ダレ形状になるため、これらウエーハ１，２を接合した後でも外周部には隙間が生じるので、こうして作製された半導体接合ウエーハＡの外周の約１〜２ｍｍの幅部分には、未接合部３が生じる。 Further, since the outer peripheral portions of the base wafer 1 and the bond wafer 2 are formed in a sagging shape by mirror polishing before bonding, a gap is generated in the outer peripheral portion even after the wafers 1 and 2 are bonded. An unjoined portion 3 is formed in a width portion of about 1 to 2 mm on the outer periphery of the joined wafer A.
そのため、この接合工程の後に、上記未接合部３を除去する必要が生じ、上述したベースウエーハ１及びボンドウエーハ２の接合後に、図１（ｃ）に示す如く、それらの外周を例えば面取りなどの機械的な研削加工によって、両ウエーハ１，２の外周部及び酸化膜４を所定の直径まで縮径していた。 Therefore, it is necessary to remove the unjoined portion 3 after this joining step, and after joining the base wafer 1 and the bond wafer 2 described above, as shown in FIG. The outer peripheral portions of both wafers 1 and 2 and the oxide film 4 were reduced in diameter to a predetermined diameter by mechanical grinding.
それにより、半導体接合ウエーハＡの外周から未接合部３が除去されて、上記研削加工による該半導体接合ウエーハＡの研削部５が酸化膜４なしで露出する。
しかし、上記研削加工の際、前記固着熱処理時に形成された酸化膜４によって研削工具の寿命が短くなるため、研削砥石の番手（砥粒粒度）を粗くして研削加工を行っていたが、研削具の番手が粗いと、チッピングの原因となる加工歪みが生ずると共に、砥粒から生じる重金属汚染の問題もある。
Thereby, the unbonded portion 3 is removed from the outer periphery of the semiconductor bonded wafer A, and the ground portion 5 of the semiconductor bonded wafer A by the above-described grinding process is exposed without the oxide film 4.
However, during the grinding process, the life of the grinding tool is shortened by the oxide film 4 formed at the time of the fixing heat treatment. Therefore, the grinding process is performed with a coarse grindstone count (abrasive grain size). When the count of the tool is rough, processing distortion that causes chipping occurs, and there is also a problem of heavy metal contamination generated from the abrasive grains.
そこで本発明では、このような未接合部３の除去工程後に、図１（ｄ）に示す如く、上述した固着熱処理時のキャリアガスによって形成された半導体ウエーハ１，２の表裏両面１ｂ，２ｂの酸化膜４を残したまま、エッチング液６に浸漬して、上記研削加工による研削部５をエッチング処理することにより、これら酸化膜４が保護膜として機能し、半導体ウエーハ１，２の表裏両面１ｂ，２ｂがエッチングされず、研削部５のみが所定量エッチングされて、該研削部５の加工歪みや重金属の残渣が生じることがない。
以下、本発明の一実施例を図面に基づいて説明する。
Therefore, in the present invention, after the removal process of the unbonded portion 3, as shown in FIG. 1D, the front and back surfaces 1b and 2b of the semiconductor wafers 1 and 2 formed by the carrier gas at the time of the fixing heat treatment described above are used. By immersing in the etching solution 6 while leaving the oxide film 4 and etching the grinding portion 5 by the grinding process, the oxide film 4 functions as a protective film, and both the front and back surfaces 1b of the semiconductor wafers 1 and 2 are formed. , 2b are not etched, and only the grinding part 5 is etched by a predetermined amount, so that processing distortion of the grinding part 5 and heavy metal residues do not occur.
Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
この実施例１は、前記半導体ウエーハ１，２のベースウエーハ及びボンドウエーハとして、２枚のシリコン基板（例えば直径６インチ、結晶方位＜１００＞）を用意し、これらの接合面１ａ，２ａを直接密着させ、これに固着熱処理を加えて接合させた後に、前記研削加工として面取り加工により、両シリコン基板１，２の外周に生じる未接合部３を除去して、前記研削部５である面取り部が酸化膜４なしで露出され、この未接合部３の除去工程後に、上記固着熱処理時のキャリアガスによって形成された酸化膜４をシリコン基板１，２の表裏両面１ｂ，２ｂに残したまま、エッチング液６としてフッ酸、硝酸、酢酸などが所定の割合で混合される混酸液中に浸漬した場合を示すものである。 In the first embodiment, two silicon substrates (for example, 6 inches in diameter, crystal orientation <100>) are prepared as the base wafer and bond wafer of the semiconductor wafers 1 and 2, and the bonding surfaces 1a and 2a are directly connected. After being bonded and bonded by applying a fixing heat treatment, the chamfering process as the grinding process is performed to remove the unbonded part 3 formed on the outer circumferences of the silicon substrates 1 and 2, and the chamfered part which is the grinding part 5 Is exposed without the oxide film 4, and after the removal process of the unbonded portion 3, the oxide film 4 formed by the carrier gas during the fixing heat treatment is left on both the front and back surfaces 1b and 2b of the silicon substrates 1 and 2, This shows a case where the etching solution 6 is immersed in a mixed acid solution in which hydrofluoric acid, nitric acid, acetic acid and the like are mixed at a predetermined ratio.
上記面取り加工後の面取り部５におけるベースウエーハ１とボンドウエーハ２の接合部分を走査型電子顕微鏡（ＳＥＭ）で観察した拡大写真を図２（ａ）に示す。 FIG. 2A shows an enlarged photograph of the bonding portion of the base wafer 1 and the bond wafer 2 in the chamfered portion 5 after the chamfering process observed with a scanning electron microscope (SEM).
そして、この混酸液６のエッチングにおいては、接合されたシリコン基板１，２の表裏両面１ｂ，２ｂが酸化膜４で保護されるため、これらの表裏両面１ｂ，２ｂはエッチングされない。 In the etching of the mixed acid solution 6, the front and back surfaces 1 b and 2 b of the bonded silicon substrates 1 and 2 are protected by the oxide film 4, so that the front and back surfaces 1 b and 2 b are not etched.
詳しく説明すれば、事前に酸化膜厚とエッチング量の変化に伴って、接合された半導体ウエーハ１，２の総合厚さ寸法の変化について測定を行って、エッチングされないことを確認した。その結果を表１に示す。 More specifically, the change in the total thickness of the bonded semiconductor wafers 1 and 2 was measured in advance with changes in the oxide film thickness and the etching amount, and it was confirmed that etching was not performed. The results are shown in Table 1.
この表中で「酸化膜厚」とは、シリコン基板１，２の表裏両面１ｂ，２ｂに形成された酸化膜４の面内９点において、各酸化膜４の厚さ寸法を夫々測定して、その最大値、最小値と平均値を列記したものである。
また、「エッチング量」とは、１１００℃、２時間の固着熱処理を行った後にエッチング処理を行い、上記「酸化膜厚」に対するエッチング処理による両ウエーハ１，２の外周部及び酸化膜４の縮径量を列記したものである。
In this table, “oxide film thickness” means that the thickness dimension of each oxide film 4 is measured at nine points in the surface of the oxide film 4 formed on the front and back surfaces 1b and 2b of the silicon substrates 1 and 2, respectively. The maximum value, minimum value and average value are listed.
The “etching amount” means that after the fixing heat treatment at 1100 ° C. for 2 hours, the etching process is performed, and the outer peripheral portions of both wafers 1 and 2 and the oxide film 4 are contracted by the etching process with respect to the “oxide film thickness”. The diameters are listed.
それにより、シリコン基板１，２の表裏両面１ｂ，２ｂに酸化膜４が約８０ｎｍ以上残るように、上記面取り加工による面取り部５を約３０μｍまで縮径しても、接合されたシリコン基板１，２の総合厚さ寸法が変化せず、これら表裏両面１ｂ，２ｂのシリコンがエッチングされないことが解る。 As a result, even if the chamfered portion 5 by chamfering is reduced to about 30 μm so that the oxide film 4 remains on the front and back surfaces 1b, 2b of the silicon substrates 1, 2, the bonded silicon substrate 1, It can be seen that the total thickness dimension of 2 does not change and the silicon on both the front and back surfaces 1b and 2b is not etched.
このような製造方法で製作された半導体接合ウエーハＡの表裏両面１ｂ，２ｂから酸化膜を除去し、上記面取り部５におけるベースウエーハ１とボンドウエーハ２の接合部分を走査型電子顕微鏡（ＳＥＭ）で観察した拡大写真を図２（ｂ）に示す。 The oxide film is removed from the front and back surfaces 1b and 2b of the semiconductor bonding wafer A manufactured by such a manufacturing method, and the bonding portion of the base wafer 1 and the bond wafer 2 in the chamfered portion 5 is scanned with a scanning electron microscope (SEM). The observed enlarged photograph is shown in FIG.
上述したエッチング処理前の面取り部５におけるベースウエーハ１とボンドウエーハ２の接合部分を観察したＳＥＭ拡大写真と、エッチング処理後の面取り部５におけるベースウエーハ１とボンドウエーハ２の接合部分を観察したＳＥＭ拡大写真とを目視で比較すると、エッチング処理前よりもエッチング処理後の表面粗さが大幅に改善されていることが容易に解る。
それにより、後工程でチップ・カケが低減されることを期待できる。
The SEM enlarged photograph which observed the junction part of base wafer 1 and bond wafer 2 in chamfer part 5 before an etching process mentioned above, and the SEM which observed the junction part of base wafer 1 and bond wafer 2 in chamfer part 5 after an etching process Comparing the enlarged photograph with the naked eye, it can be easily understood that the surface roughness after the etching process is greatly improved than before the etching process.
Thereby, it can be expected that chip and chipping will be reduced in the subsequent process.
更に、上記エッチング処理前の面取り部５における加工歪みと、エッチング処理後の面取り部５における加工歪みを、粗さ測定機（chapman:チャップマンMP2000）で測定したところ、エッチング前の加工歪みが最大粗さ（Ｒｍａｘ）０．７μｍ程度であったのに対し、エッチング後の加工歪みは最大粗さ（Ｒｍａｘ）約０．１μｍ以下となり、目視では解らない加工歪みが除去されていることも解る。 Furthermore, when the processing distortion in the chamfered part 5 before the etching process and the processing distortion in the chamfered part 5 after the etching process were measured with a roughness measuring machine (chapman: Chapman MP2000), the processing distortion before the etching was the maximum roughness. While the thickness (Rmax) is about 0.7 μm, the processing strain after etching is about 0.1 μm or less in maximum roughness (Rmax), and it is also understood that processing strain that is not visually recognized is removed.
また、上記エッチング処理後の面取り部５における重金属不純物をＩＣＰ−ＭＳ又はＡＡＳ測定により分析したところ、図３のグラフに示すようになった。
この表中で縦軸の単位が「ａｔｏｍｓ／ｃｍ２」であり、例えば「１Ｅ＋１１」とは１０１１ａｔｏｍｓ／ｃｍ２を示し、「１Ｅ＋８」とは１０８ａｔｏｍｓ／ｃｍ２を示している。
Further, when the heavy metal impurities in the chamfered portion 5 after the etching treatment were analyzed by ICP-MS or AAS measurement, the result was as shown in the graph of FIG.
In this table, the unit of the vertical axis is “atoms / cm 2 ”. For example, “1E + 11” indicates 10 11 atoms / cm 2 and “1E + 8” indicates 10 8 atoms / cm 2 .
その結果、「エッチング無し」と「２５μｍエッチング」〜「３０μｍエッチング」とを比較すると、重金属不純物（Ｎａ、Ｍｇ、Ａｌ、Ｋ、Ｃａ、Ｔｉ、Ｃｒ、Ｍｎ、Ｆｅ、Ｎｉ、Ｃｕ、Ｚｎ）は、１０１１ａｔｏｍｓ／ｃｍ２台から１０８ａｔｏｍｓ／ｃｍ２台となり、大幅に低減されていることが解る。 As a result, comparing “no etching” with “25 μm etching” to “30 μm etching”, heavy metal impurities (Na, Mg, Al, K, Ca, Ti, Cr, Mn, Fe, Ni, Cu, Zn) are From 10 11 atoms / cm 2 to 10 8 atoms / cm 2 , it can be seen that the number is greatly reduced.
尚、前示実施例では、２枚の半導体ウエーハ１，２の接合面１ａ，２ａを直接密着させ、これに固着熱処理を加えて接合させたが、これに限定されず、３枚以上の半導体ウエーハを接合させても良く、この場合も上述した製造方法と同様に行う。
更に、上記固着熱処理後に、研削加工として面取り加工により未接合部３を除去したが、これに限定されず、面取り加工以外の機械研削で未接合部３を除去しても良い。
In the embodiment described above, the bonding surfaces 1a and 2a of the two semiconductor wafers 1 and 2 are directly adhered and bonded to each other by a fixing heat treatment. However, the present invention is not limited to this. Wafers may be joined, and in this case, the manufacturing method is the same as described above.
Furthermore, after the fixing heat treatment, the unjoined portion 3 is removed by chamfering as a grinding process. However, the present invention is not limited to this, and the unjoined portion 3 may be removed by mechanical grinding other than chamfering.
Ａ 半導体接合ウエーハ １ 半導体ウエーハ（ベースウエーハ）
１ａ 接合面 １ｂ 表面
２ 半導体ウエーハ（ボンドウエーハ） ２ａ 接合面
２ｂ 表面 ３ 未接合部
４ 酸化膜 ５ 研削部（面取り部）
６ エッチング液（混酸液）
A Semiconductor bonding wafer 1 Semiconductor wafer (base wafer)
DESCRIPTION OF SYMBOLS 1a Bonding surface 1b Surface 2 Semiconductor wafer (bond wafer) 2a Bonding surface 2b Surface 3 Unbonded portion 4 Oxide film 5 Grinding portion (chamfered portion)
6 Etching solution (mixed acid solution)
Claims (2)
前記未接合部（３）の除去後に、熱処理時にキャリアガスによって形成された酸化膜（４）を半導体ウエーハ（１，２）の表裏両面（１ｂ，２ｂ）に残したまま、前記研削加工による研削部（５）をエッチング液（６）でエッチング処理したことを特徴とする半導体接合ウエーハの製造方法。 At least two semiconductor wafers (1, 2) are directly adhered to each other and subjected to heat treatment for bonding, and the unbonded portion (3) generated on the outer periphery of the bonded semiconductor wafer (1, 2) is ground by grinding. In the method of manufacturing a semiconductor junction wafer to be removed,
After removal of the unbonded portion (3), the oxide film (4) formed by the carrier gas during the heat treatment is left on the front and back surfaces (1b, 2b) of the semiconductor wafer (1, 2) and is ground by the grinding process. A method for manufacturing a semiconductor bonded wafer, wherein the part (5) is etched with an etching solution (6).
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| JPS6489346A (en) * | 1987-09-29 | 1989-04-03 | Sony Corp | Semiconductor substrate |
| JPH05109677A (en) * | 1991-10-16 | 1993-04-30 | Sony Corp | Manufacture of soi substrate |
| JPH08107091A (en) * | 1994-09-30 | 1996-04-23 | Kyushu Komatsu Denshi Kk | Manufacture of soi substrate |
| JPH10233351A (en) * | 1997-02-20 | 1998-09-02 | Nec Corp | Structure of semiconductor substrate and manufacture of the same |
| JP2006339330A (en) * | 2005-06-01 | 2006-12-14 | Shin Etsu Handotai Co Ltd | Manufacturing method of laminated wafer |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6489346A (en) * | 1987-09-29 | 1989-04-03 | Sony Corp | Semiconductor substrate |
| JPH05109677A (en) * | 1991-10-16 | 1993-04-30 | Sony Corp | Manufacture of soi substrate |
| JPH08107091A (en) * | 1994-09-30 | 1996-04-23 | Kyushu Komatsu Denshi Kk | Manufacture of soi substrate |
| JPH10233351A (en) * | 1997-02-20 | 1998-09-02 | Nec Corp | Structure of semiconductor substrate and manufacture of the same |
| JP2006339330A (en) * | 2005-06-01 | 2006-12-14 | Shin Etsu Handotai Co Ltd | Manufacturing method of laminated wafer |
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