JPS61144839A - Bonding method for semiconductor wafer - Google Patents

Bonding method for semiconductor wafer

Info

Publication number
JPS61144839A
JPS61144839A JP26717384A JP26717384A JPS61144839A JP S61144839 A JPS61144839 A JP S61144839A JP 26717384 A JP26717384 A JP 26717384A JP 26717384 A JP26717384 A JP 26717384A JP S61144839 A JPS61144839 A JP S61144839A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
step
wafer
lapping
polished
made
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26717384A
Inventor
Kiyoshi Fukuda
Kazuyoshi Furukawa
Masaru Shinpo
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques

Abstract

PURPOSE:To prevent any polishing flaw or crack from generating in the lapping process by a method wherein a step is provided along the outer peripheral part of the polished surface of the semiconductor wafer on at least one side of two sheets of semiconductor wafers and two sheets of the semiconductor wafers are directly bonded. CONSTITUTION:A step 2 is processed along the outer periphery of the mirror polished surface of a wafer 1 on one side. The width of the step is made a little larger than the polished sag and the height thereof is made equal to the residual thickness in after the lapping process finish. The processing depends upon an etching. After the step is processed, the wafer 1 is sufficiently cleansed and the fellow polished surfaces of the wafer 1 and the other wafer 3 are made to directly bond without making any foreign substance interpose between the polished surfaces of both wafers. A resin 4 so forth are filled in the gap of the step 2 of the bonded body obtainable and a lapping is performed. As the gap to be formed by the step 2 is previously made equal to the desired residual thickness in after the lapping process finish, the processing finishes at the point when the filling material 4 is exposed and the filling material 4 is removed. According to this constitution, the generation of a polishing flaw, which is caused by some lacking of the non-bonding parts at the time of lapping, or the generation of a crack due to the flaw can be prevented.
JP26717384A 1984-12-18 1984-12-18 Bonding method for semiconductor wafer Pending JPS61144839A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26717384A JPS61144839A (en) 1984-12-18 1984-12-18 Bonding method for semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26717384A JPS61144839A (en) 1984-12-18 1984-12-18 Bonding method for semiconductor wafer

Publications (1)

Publication Number Publication Date
JPS61144839A true true JPS61144839A (en) 1986-07-02

Family

ID=17441114

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26717384A Pending JPS61144839A (en) 1984-12-18 1984-12-18 Bonding method for semiconductor wafer

Country Status (1)

Country Link
JP (1) JPS61144839A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6351349U (en) * 1986-09-20 1988-04-07
JPS6489346A (en) * 1987-09-29 1989-04-03 Sony Corp Semiconductor substrate
JPH0361331U (en) * 1989-10-19 1991-06-17
JP2011510518A (en) * 2008-01-24 2011-03-31 ブルーワー サイエンス アイ エヌ シー. How the device wafers mounted in opposite to the carrier substrate
JP2016025116A (en) * 2014-07-16 2016-02-08 株式会社ディスコ Wafer processing method

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6351349U (en) * 1986-09-20 1988-04-07
JPS6489346A (en) * 1987-09-29 1989-04-03 Sony Corp Semiconductor substrate
JP2535957B2 (en) * 1987-09-29 1996-09-18 ソニー株式会社 A semiconductor substrate
JPH0361331U (en) * 1989-10-19 1991-06-17
JP2011510518A (en) * 2008-01-24 2011-03-31 ブルーワー サイエンス アイ エヌ シー. How the device wafers mounted in opposite to the carrier substrate
JP2012253367A (en) * 2008-01-24 2012-12-20 Brewer Science Inc Method for reversibly mounting device wafer to carrier substrate
JP2016025116A (en) * 2014-07-16 2016-02-08 株式会社ディスコ Wafer processing method

Similar Documents

Publication Publication Date Title
US5389579A (en) Method for single sided polishing of a semiconductor wafer
US6048411A (en) Silicon-on-silicon hybrid wafer assembly
US5400548A (en) Process for manufacturing semiconductor wafers having deformation ground in a defined way
US5032544A (en) Process for producing semiconductor device substrate using polishing guard
US20030008478A1 (en) Production method for silicon wafer and soi wafer, and soi wafer
US5897743A (en) Jig for peeling a bonded wafer
JPH03256665A (en) Polishing method for silicone wafer
US20040121557A1 (en) Method of smoothing the outline of a useful layer of material transferred onto a support substrate
JPH07183255A (en) Cutting method of joint substrate
JPS6419729A (en) Manufacture of semiconductor wafer
JPS63285195A (en) Bonding of quartz single crystal
JPH0897111A (en) Method for manufacturing soi substrate
JPS60123047A (en) Semiconductor device
JP2002319554A (en) Method and device for dividing wafer
JPS6051700A (en) Bonding method of silicon crystalline body
US6910403B1 (en) Method for cutting semiconductor wafer protecting sheet
JPS61145839A (en) Semiconductor wafer bonding method and bonding jig
US6077149A (en) Method and apparatus for surface-grinding of workpiece
JPS59214554A (en) Beveling grinder for wafer
JPH02125651A (en) Lead frame
JPS56140632A (en) Method for giving strain to semiconductor wafer
JPS618960A (en) Lead frame
JPS62132324A (en) Removing method for chamfered grinding damage layer of wafer and removing jig
JPH02267950A (en) Semiconductor substrate
JPS5552235A (en) Fastening of semiconductor wafer on substrate