JPH08107193A - Manufacture of soi substrate - Google Patents
Manufacture of soi substrateInfo
- Publication number
- JPH08107193A JPH08107193A JP27417894A JP27417894A JPH08107193A JP H08107193 A JPH08107193 A JP H08107193A JP 27417894 A JP27417894 A JP 27417894A JP 27417894 A JP27417894 A JP 27417894A JP H08107193 A JPH08107193 A JP H08107193A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- wafer
- manufacturing
- soi substrate
- outer peripheral
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、支持基板として機能す
る半導体ウェハと、活性基板として機能する半導体ウェ
ハを貼り合わせて得られる貼合せウェハからSOI基板
を製造するSOI基板の製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an SOI substrate manufacturing method for manufacturing an SOI substrate from a bonded wafer obtained by bonding a semiconductor wafer functioning as a supporting substrate and a semiconductor wafer functioning as an active substrate. is there.
【0002】[0002]
【従来の技術】近年、高性能の半導体デバイス用基板と
して、その高耐圧性や高速性などからSOI基板が要求
されており、この種の要求を満たす大面積で結晶欠陥の
少ないSOI基板は、2枚の半導体ウェハを貼り合わせ
て得られる貼合せウェハから比較的容易に作れるように
なった。通常、このような貼合せウェハの製造は次に示
すような工程で行われる(図3参照)。 (1)活性基板11を熱処理し、その表面に酸化膜13
を形成した後、支持基板12との接合面11aに鏡面仕
上げを施す一方、支持基板12の接合面12aにも鏡面
仕上げを施す(図3(a))。 (2)それぞれの基板の鏡面仕上げを施した接合面11
a、12aを洗浄、親水処理し、乾燥処理した後、まだ
親水性を保持した状態でそれぞれの接合面11a、12
aを互いに接合させる。これに再度熱処理を行うことに
より活性基板11と支持基板12は互いに貼着すると共
に、支持基板12側にも酸化膜13が形成される。これ
により貼合せウェハ14を得られる(図3(b))。2. Description of the Related Art In recent years, an SOI substrate has been required as a substrate for high-performance semiconductor devices because of its high withstand voltage and high speed, and an SOI substrate having a large area and few crystal defects meets the requirements of this type. It has become relatively easy to make a bonded wafer obtained by bonding two semiconductor wafers. Usually, such a bonded wafer is manufactured by the following steps (see FIG. 3). (1) The active substrate 11 is heat-treated, and an oxide film 13 is formed on the surface thereof.
After forming, the joint surface 11a with the support substrate 12 is mirror-finished, while the joint surface 12a of the support substrate 12 is also mirror-finished (FIG. 3A). (2) Bonding surface 11 with mirror finish of each substrate
After cleaning, hydrophilic treatment, and drying treatment of a and 12a, the bonding surfaces 11a and 12 of the respective bonding surfaces 11a and 12 are kept hydrophilic.
Join a together. By heat-treating this again, the active substrate 11 and the supporting substrate 12 are attached to each other, and the oxide film 13 is also formed on the supporting substrate 12 side. Thereby, the bonded wafer 14 is obtained (FIG. 3 (b)).
【0003】ところが、この親水処理及び乾燥処理をす
ることにより残留水素や水素イオンがこの貼合せウェハ
14の外周部に集まりやすく、それが気泡を形成して未
接着部(ボイド)発生の原因となる。この未接着部は他
の部位より強度が落ち、後のデバイス工程でチッピング
やパーティクル発生の原因となることから、未接着部を
含む活性基板11の外周部を取り除く必要がある。従
来、この活性基板11の外周部を取り除く方法として、
次のような貼合せウェハ14の径を小さくする方法が行
われている。すなわち、図4(a)に示すように、活性
基板11の上面を所定の厚さまで平面研削した後、貼合
せウェハ14を水平方向に回転させると共に、異形ホイ
ール15を水平方向に回転さる。この異形ホイール15
の上部研削面15aに貼合せウェハ14の外周部を当接
させ、水平方向から約1インチ程度の幅だけ研削し径を
小さくする。次に図4(b)、(c)に示すように、径
を小さくされた貼合せウェハ14の周縁部を異形ホイー
ル15の下部研削面15bに当接させ、この周縁部を面
取りする。最後に、中間酸化膜5aを残した状態でフッ
酸溶液によるエッチングで酸化膜13を除去し、活性基
板11の上面をさらに薄く研磨してSOI基板(図示せ
ず)が得られる。However, by performing the hydrophilic treatment and the drying treatment, residual hydrogen and hydrogen ions are likely to collect on the outer peripheral portion of the bonded wafer 14, which causes bubbles to form unbonded portions (voids). Become. Since the strength of the non-bonded portion is lower than that of other portions and causes chipping or particle generation in a later device process, it is necessary to remove the outer peripheral portion of the active substrate 11 including the non-bonded portion. Conventionally, as a method of removing the outer peripheral portion of the active substrate 11,
The following method is used to reduce the diameter of the bonded wafer 14. That is, as shown in FIG. 4A, after the upper surface of the active substrate 11 is surface-ground to a predetermined thickness, the bonded wafer 14 is rotated in the horizontal direction and the profile wheel 15 is rotated in the horizontal direction. This variant wheel 15
The outer peripheral portion of the bonded wafer 14 is brought into contact with the upper grinding surface 15a of the above, and is ground by a width of about 1 inch from the horizontal direction to reduce the diameter. Next, as shown in FIGS. 4B and 4C, the peripheral edge of the bonded wafer 14 having a reduced diameter is brought into contact with the lower grinding surface 15b of the deformed wheel 15, and the peripheral edge is chamfered. Finally, with the intermediate oxide film 5a left, the oxide film 13 is removed by etching with a hydrofluoric acid solution, and the upper surface of the active substrate 11 is further thinly polished to obtain an SOI substrate (not shown).
【0004】[0004]
【発明が解決しようとする課題】しかしながら、このよ
うな貼合せウェハの外周部を水平方向から研削し、貼合
せウェハの径を小さくする方法においては、研削する幅
が約1インチ程度と大きく、水平方向の研削ストレスが
長時間に渡って貼合せウェハにかかることにより加工歪
みが生じ、これにより亀裂などの結晶欠陥(ピット)が
発生するという問題点があった。また、研削する幅が約
1インチ程度と大きく、水平方向からの研削では時間が
かかり過ぎ、生産効率が悪いという問題点があった。本
発明は、上記問題に鑑みなされたもので、貼合せウェハ
に対して研削ストレスをかけず結晶欠陥(ピット)の発
生を防止できると共に、従来技術の製造方法に比し生産
効率がよいSOI基板の製造方法を提供することを目的
とするものである。However, in the method of grinding the outer peripheral portion of such a bonded wafer from the horizontal direction to reduce the diameter of the bonded wafer, the width to be ground is as large as about 1 inch. The horizontal grinding stress is applied to the bonded wafer for a long period of time, resulting in processing strain, which causes crystal defects (pits) such as cracks. Further, the width to be ground is as large as about 1 inch, and it takes too much time to grind from the horizontal direction, resulting in a problem of poor production efficiency. The present invention has been made in view of the above problems, and an SOI substrate that can prevent the generation of crystal defects (pits) without applying a grinding stress to a bonded wafer and has a higher production efficiency than the conventional manufacturing method. It is an object of the present invention to provide a manufacturing method of.
【0005】[0005]
【課題を解決するための手段】このため本発明では、支
持基板として機能する半導体ウェハと、活性基板として
機能する半導体ウェハを貼り合わせてSOI基板を製造
するに当たり、貼り合わせた半導体ウェハの外周部を除
去する方法において、貼り合わせた半導体ウェハに対し
て略垂直方向に回転するカッターにより前記半導体ウェ
ハの外周部を切断するようにしたものである。Therefore, in the present invention, when a semiconductor wafer functioning as a supporting substrate and a semiconductor wafer functioning as an active substrate are bonded to each other to manufacture an SOI substrate, an outer peripheral portion of the bonded semiconductor wafers is used. In the method of removing the semiconductor wafer, the outer peripheral portion of the semiconductor wafer is cut by a cutter that rotates in a direction substantially perpendicular to the bonded semiconductor wafer.
【0006】[0006]
【実施例】以下、本発明の実施例を図面に基づいて説明
する。図1は本発明に係るSOI基板の製造方法を示す
模式図、図2は本発明に係るSOI基板の製造方法の製
造工程を示す図、図3は貼合せウェハの製造工程の一例
を示す図、図4は従来技術のSOI基板の製造方法を示
す図である。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic diagram showing a method for manufacturing an SOI substrate according to the present invention, FIG. 2 is a diagram showing a manufacturing process for the method for manufacturing an SOI substrate according to the present invention, and FIG. 3 is a diagram showing an example of a manufacturing process for a bonded wafer. FIG. 4 is a diagram showing a conventional method for manufacturing an SOI substrate.
【0007】本実施例のSOI基板の製造方法は、貼合
せウェハ4を得るところまでは上記した従来技術と同様
である。すなわち、図2(a)に示すように、支持基板
2を熱処理し、その表面に酸化膜5を成長させた後、親
水処理および乾燥処理を経て、その上面に活性基板3を
接合させる。図2(b)に示すように、接合した支持基
板2と活性基板3を熱処理することにより互いに貼着さ
せると共に、全体に酸化膜5を成長させて貼合せウェハ
4を得る。図2(c)に示すように、貼合せウェハ4の
活性基板3の上面を研削機により平面研削する。The method of manufacturing the SOI substrate of this embodiment is the same as the above-mentioned conventional technique until the bonded wafer 4 is obtained. That is, as shown in FIG. 2A, the support substrate 2 is heat-treated, and after the oxide film 5 is grown on the surface of the support substrate 2, the active substrate 3 is bonded to the upper surface of the support substrate 2 through hydrophilic treatment and drying treatment. As shown in FIG. 2B, the bonded support substrate 2 and active substrate 3 are heat-bonded to each other, and an oxide film 5 is grown on the entire surface to obtain a bonded wafer 4. As shown in FIG. 2C, the upper surface of the active substrate 3 of the bonded wafer 4 is surface ground by a grinding machine.
【0008】次に本実施例の外周部の除去方法について
説明する。図1(a)に示すように、平面研削された貼
合せウェハ4を水平方向に回転させる。次に、ダイシン
グマシンに設けられた円盤状のカッター1を活性基板3
に対して略垂直方向に回転させ、上方から矢印Aの方向
に降ろしていく。図1(b)に示すように、カッター1
が降りるにしたがって、活性基板3と支持基板2は外周
部に沿った同一面で略垂直に切断され、カッター1が支
持基板2の底面の酸化膜5を切断したところで未接着部
を含む外周部はドーナッツ状となり貼合せウェハ4から
切り離され、切断が終了する。Next, a method of removing the outer peripheral portion of this embodiment will be described. As shown in FIG. 1A, the surface-ground bonded wafer 4 is rotated in the horizontal direction. Next, the disk-shaped cutter 1 provided on the dicing machine is attached to the active substrate 3
It is rotated in a substantially vertical direction with respect to and is lowered in the direction of arrow A from above. As shown in FIG. 1B, the cutter 1
As the substrate goes down, the active substrate 3 and the supporting substrate 2 are cut substantially vertically on the same plane along the outer peripheral portion, and when the cutter 1 cuts the oxide film 5 on the bottom surface of the supporting substrate 2, the outer peripheral portion including the unbonded portion is cut. Becomes a donut shape and is separated from the bonded wafer 4, and the cutting is completed.
【0009】さらに、図2の工程図に戻りSOI基板は
次の工程で製造される。図2(d)に示すように、ドー
ナッツ状の外周部が貼合せウェハ4から取り外される。
図2(e)に示すように、外周部が取り外された貼合せ
ウェハ4に面取り加工が施される。最後に、この貼合せ
ウェハ4の底面に残った酸化膜5がフッ酸溶液によるエ
ッチングにより取り除かれ、活性基板3の上面をさらに
薄く研磨し、SOI基板(図示せず)を得る。Further, returning to the process diagram of FIG. 2, the SOI substrate is manufactured in the next process. As shown in FIG. 2D, the donut-shaped outer peripheral portion is removed from the bonded wafer 4.
As shown in FIG. 2E, the bonded wafer 4 from which the outer peripheral portion has been removed is chamfered. Finally, the oxide film 5 remaining on the bottom surface of the bonded wafer 4 is removed by etching with a hydrofluoric acid solution, and the upper surface of the active substrate 3 is further thinly polished to obtain an SOI substrate (not shown).
【0010】尚、上記実施例では活性基板3を平面研削
した後、貼合せウェハ4を切断していたが、これに限ら
れるものではなく、活性基板を平面研削する前に貼合せ
ウェハを切断して、その後に活性基板を平面研削するよ
うにしたものでもよい。Although the bonded wafer 4 is cut after the active substrate 3 is ground in the above embodiment, the invention is not limited to this, and the bonded wafer is cut before the active substrate is ground. Then, the active substrate may be subjected to surface grinding thereafter.
【0011】[0011]
【発明の効果】本発明では以上のように構成したので、
貼合せウェハの外周部の未接着部を取り除くに当り、貼
合せウェハに研削ストレスがかかることがなく、これに
より結晶欠陥(ピット)の発生を防止できるという優れ
た効果がある。また、垂直方向からの切断は水平方向か
らの研削よりも短時間で外周部を取り除くことができ、
生産効率がよいという優れた効果がある。Since the present invention is configured as described above,
In removing the unbonded portion on the outer peripheral portion of the bonded wafer, grinding stress is not applied to the bonded wafer, which has an excellent effect of preventing generation of crystal defects (pits). Also, cutting from the vertical direction can remove the outer peripheral portion in a shorter time than grinding from the horizontal direction,
It has an excellent effect of high production efficiency.
【図1】本発明に係るSOI基板の製造方法を示す模式
図である。FIG. 1 is a schematic view showing a method for manufacturing an SOI substrate according to the present invention.
【図2】本発明に係るSOI基板の製造方法の製造工程
を示す図である。FIG. 2 is a diagram showing a manufacturing process of an SOI substrate manufacturing method according to the present invention.
【図3】貼合せウェハの製造工程の一例を示す図であ
る。FIG. 3 is a diagram showing an example of a manufacturing process of a bonded wafer.
【図4】従来技術のSOI基板の製造方法を示す図であ
る。FIG. 4 is a diagram showing a method for manufacturing an SOI substrate according to the related art.
1 カッター 2 支持基板 3 活性基板 4 貼合せウェハ 5 酸化膜 5a 中間酸化膜 11 活性基板 12 支持基板 13 酸化膜 13a 中間酸化膜 14 貼合せウェハ 15 異形ホイール 15a 上部研削面 15b 下部研削面 1 Cutter 2 Support Substrate 3 Active Substrate 4 Bonded Wafer 5 Oxide Film 5a Intermediate Oxide Film 11 Active Substrate 12 Support Substrate 13 Oxide Film 13a Intermediate Oxide Film 14 Bonded Wafer 15 Deformed Wheel 15a Upper Grinding Surface 15b Lower Grinding Surface
───────────────────────────────────────────────────── フロントページの続き (72)発明者 橋口 英里子 宮崎県宮崎郡清武町大字木原1112番地 九 州コマツ電子株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Eriko Hashiguchi 1112 Kihara, Kiyotake-cho, Miyazaki-gun, Miyazaki Prefecture Komatsu Electronics Co., Ltd.
Claims (3)
と、活性基板として機能する半導体ウェハを貼り合わせ
てSOI基板を製造するに当たり、貼り合わせた半導体
ウェハの外周部を除去する方法において、貼り合わせた
半導体ウェハに対して略垂直方向に回転するカッターに
より前記半導体ウェハの外周部を切断するようにしたこ
とを特徴とするSOI基板の製造方法。1. A method of removing an outer peripheral portion of a bonded semiconductor wafer when bonding a semiconductor wafer functioning as a supporting substrate and a semiconductor wafer functioning as an active substrate to each other to manufacture an SOI substrate. A method of manufacturing an SOI substrate, wherein an outer peripheral portion of the semiconductor wafer is cut by a cutter that rotates in a direction substantially perpendicular to the wafer.
回転させ、該半導体ウェハの外周部を切断するようにし
たことを特徴とする請求項1記載のSOI基板の製造方
法。2. The method for manufacturing an SOI substrate according to claim 1, wherein the bonded semiconductor wafer is rotated in the horizontal direction and the outer peripheral portion of the semiconductor wafer is cut.
マシンに設けられた円盤状のカッターにより貼り合わせ
た半導体ウェハの外周部を切断するようにしたことを特
徴とする請求項1記載のSOI基板の製造方法。3. The manufacturing of an SOI substrate according to claim 1, wherein a dicing machine is used, and the outer peripheral portion of the bonded semiconductor wafers is cut by a disk-shaped cutter provided in the dicing machine. Method.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27417894A JPH08107193A (en) | 1994-09-30 | 1994-09-30 | Manufacture of soi substrate |
TW85100485A TW303483B (en) | 1994-09-30 | 1996-01-16 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27417894A JPH08107193A (en) | 1994-09-30 | 1994-09-30 | Manufacture of soi substrate |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH08107193A true JPH08107193A (en) | 1996-04-23 |
Family
ID=17538129
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP27417894A Pending JPH08107193A (en) | 1994-09-30 | 1994-09-30 | Manufacture of soi substrate |
Country Status (2)
Country | Link |
---|---|
JP (1) | JPH08107193A (en) |
TW (1) | TW303483B (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007535158A (en) * | 2004-04-27 | 2007-11-29 | エス.オー.アイ.テック、シリコン、オン、インシュレター、テクノロジーズ | Method of making a chip and associated support |
JP2011524083A (en) * | 2008-09-02 | 2011-08-25 | エス.オー.アイ.テック シリコン オン インシュレータ テクノロジーズ | Incremental trimming |
US8535117B2 (en) | 2009-12-03 | 2013-09-17 | Ebara Corporation | Method and apparatus for polishing a substrate having a grinded back surface |
CN110854011A (en) * | 2019-09-30 | 2020-02-28 | 芯盟科技有限公司 | Method for processing stacked bonded wafers |
-
1994
- 1994-09-30 JP JP27417894A patent/JPH08107193A/en active Pending
-
1996
- 1996-01-16 TW TW85100485A patent/TW303483B/zh active
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007535158A (en) * | 2004-04-27 | 2007-11-29 | エス.オー.アイ.テック、シリコン、オン、インシュレター、テクノロジーズ | Method of making a chip and associated support |
JP4782107B2 (en) * | 2004-04-27 | 2011-09-28 | エス.オー.アイ.テック、シリコン、オン、インシュレター、テクノロジーズ | Method of making a chip and associated support |
JP2011524083A (en) * | 2008-09-02 | 2011-08-25 | エス.オー.アイ.テック シリコン オン インシュレータ テクノロジーズ | Incremental trimming |
US8535117B2 (en) | 2009-12-03 | 2013-09-17 | Ebara Corporation | Method and apparatus for polishing a substrate having a grinded back surface |
CN110854011A (en) * | 2019-09-30 | 2020-02-28 | 芯盟科技有限公司 | Method for processing stacked bonded wafers |
Also Published As
Publication number | Publication date |
---|---|
TW303483B (en) | 1997-04-21 |
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