JPS61206240A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS61206240A
JPS61206240A JP4730985A JP4730985A JPS61206240A JP S61206240 A JPS61206240 A JP S61206240A JP 4730985 A JP4730985 A JP 4730985A JP 4730985 A JP4730985 A JP 4730985A JP S61206240 A JPS61206240 A JP S61206240A
Authority
JP
Japan
Prior art keywords
film
polycrystalline silicon
polycrystalline
interlayer insulating
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4730985A
Other languages
Japanese (ja)
Inventor
Shigeaki Ide
繁章 井手
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP4730985A priority Critical patent/JPS61206240A/en
Publication of JPS61206240A publication Critical patent/JPS61206240A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To contrive to improve the dielectric breaking strength by a method wherein the thinly formed recessed parts of the second oxide film on the side surfaces of the nitride film are filled with a polycrystalline Si film thinner than the first polycrystalline Si film, which is then oxidized to form a polycrystalline Si oxiden films, and moreover, through a thermal oxidation the polycrystallinen Si oxide film is formed into an interlayer insulating film. CONSTITUTION:An etching is performed on a first polycrystalline Si film 5 and a nitride film 4 using a photosensitive resin film 6 performed a patterning as a mask, and after that, a thermal oxidation is performed, whereby an interlayer insulating film 7 is formed and parts 9 and 9' are formed on the side surfaces of the nitride film 4. When a polycrystalline Si film 11 thinner than the first polycrystalline Si film 5 is deposited on the whole surface of a semiconductor substrate 1, parts of the polycrystalline Si film 11 are deposited on the recessed parts 9 and 9' and become overhang-shaped parts (b) and (b'). An oxidation is performed on the polycrystalline Si film 11 and polycrystalline Si oxide films 12 and 12' are formed on the whole surface. In this process, the interlayer insulating film 7 and the polycrystalline Si film 11 thinner than the first polycrystalline Si film 5 are oxidized and in case the polycrystalline Si oxide film 12 is seen as a whole, the polycrystalline Si oxide film 12 is eliminated parts to become thinner locally.

Description

【発明の詳細な説明】 〈産業上の利用分野〉 この発明は、MOSLSI(モス集積回路)等の半導体
装置の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a method of manufacturing a semiconductor device such as a MOSLSI (MOS integrated circuit).

〈従来の技術〉 従来、例えば、第2図(a)から第2図(g)までに示
すようなシリコンゲートMOSダイナミックメモリLS
Iの製造方法がある。まず、第2図(a)に示すように
、半導体基板1上にロコス酸化法によりフィールド酸化
膜2を形成した後、第1ゲート酸化膜3およびチッ化膜
4を形成し、さらに第1多結晶シリコン膜5を形成して
、通常の写真食刻技術を用いて、所望のパターンが形成
されるように感光性樹脂6を残置させる。次に、第2図
(b)に示すように、パターンニングされた感光性樹脂
6をマスクに上記第1多結晶シリコン膜5.チッ化膜4
.第1ゲート酸化膜3を順次エツチングした後、第2図
(C)に示すように、上記半導体基板lを熱酸化するこ
とにより、層間絶縁M7を形成する。その後、第2図(
d)に示すように、第2多結晶シリコン膜8を被着し、
最後に、第2図(e)に示すように、通常の写真食刻技
術を用い、第2多結晶ンリコン膜8を所定の形状にパタ
ーンニングしている。
<Prior art> Conventionally, for example, silicon gate MOS dynamic memory LS as shown in FIGS. 2(a) to 2(g)
There is a method for producing I. First, as shown in FIG. 2(a), a field oxide film 2 is formed on a semiconductor substrate 1 by the Locos oxidation method, and then a first gate oxide film 3 and a nitride film 4 are formed, and then a first multilayer film 2 is formed. A crystalline silicon film 5 is formed, and a photosensitive resin 6 is left behind so that a desired pattern is formed using a conventional photolithography technique. Next, as shown in FIG. 2(b), using the patterned photosensitive resin 6 as a mask, the first polycrystalline silicon film 5. Nitride film 4
.. After sequentially etching the first gate oxide film 3, as shown in FIG. 2C, the semiconductor substrate 1 is thermally oxidized to form an interlayer insulation M7. After that, see Figure 2 (
As shown in d), a second polycrystalline silicon film 8 is deposited;
Finally, as shown in FIG. 2(e), the second polycrystalline silicon film 8 is patterned into a predetermined shape using a normal photolithography technique.

〈発明が解決しようとする問題点〉 ところが、上記製造方法では、第2図(f)中に示され
る部分a、すなわちチッ化膜4の側面に形成される層間
絶縁膜7の部分aが局部的に薄くなるため、第1多結晶
シリコン膜5と第2多結晶シリコン膜8とが第2図(f
)中の部分aで、電気的にショートする可能性が高くな
る問題がある。
<Problems to be Solved by the Invention> However, in the above manufacturing method, the portion a shown in FIG. 2(f), that is, the portion a of the interlayer insulating film 7 formed on the side surface of the nitride film 4 is As a result, the first polycrystalline silicon film 5 and the second polycrystalline silicon film 8 are
) There is a problem in that there is a high possibility of electrical short-circuiting at part a.

また、上記第2多結晶シリコン膜8を異方性エツチング
でパターンニングする際、層間絶縁膜7が第2図(g)
に示すように層間絶縁膜7の薄くなる部分に隣接する部
分すでひさし状となっているため、この部分すに第2多
結晶シリコン膜8が、エツチングされずに残り、第2多
結晶シリコン配線8同志でショートする可能性が高くな
り、期待される歩留が得られない問題がある。
Furthermore, when patterning the second polycrystalline silicon film 8 by anisotropic etching, the interlayer insulating film 7 is etched as shown in FIG. 2(g).
As shown in , since the part adjacent to the thinned part of the interlayer insulating film 7 has already formed an eaves shape, the second polycrystalline silicon film 8 remains in this part without being etched. There is a problem that the possibility of short-circuiting between the wiring lines 8 becomes high, and the expected yield cannot be obtained.

そこで、この発明の目的は、層間絶縁膜の耐圧の向上と
、第1多結晶シリコン膜の側面の形状の改善を図って、
第1多結晶シリコン膜と第2多結晶シリコン膜とが電気
的にショートするのを防止し、かつ、第2多結晶シリコ
ン配線同志がショートするのを防止し、期待される歩留
が得られる半導体装置の製造方法を提供することにある
Therefore, an object of the present invention is to improve the breakdown voltage of the interlayer insulating film and the shape of the side surface of the first polycrystalline silicon film.
The expected yield can be obtained by preventing electrical short-circuiting between the first polycrystalline silicon film and the second polycrystalline silicon film, as well as preventing short-circuiting between the second polycrystalline silicon wirings. An object of the present invention is to provide a method for manufacturing a semiconductor device.

く問題点を峠決するための手段〉 上記目的を達成するため、この発明の半導体装置の製造
方法は、半導体基板上に第1ゲート酸化膜とチッ化膜を
重ねて二層絶縁膜を形成し、上記二層絶縁膜上に第1多
結晶シリコン膜を形成し、上記第1多結晶シリコン膜と
上記チッ化膜をパターンニングした後、熱酸化により第
2酸化膜を形成し、上記第2酸化膜を覆って上記半導体
基板の全面上に上記第1多結晶シリコン膜よりも薄い多
結晶シリコン膜を堆積し、次に上記薄い多結晶シリコン
膜を酸化して多結晶シリコン酸化膜を形成し、次に上記
多結晶シリコン酸化膜のエツチングを行なって上記第1
多結晶シリコン膜の存在しない部分の上記多結晶シリコ
ン酸化膜を除去し、その後、熱酸化により層間絶縁膜を
形成し、次に上記層間絶縁膜の全面に第2多結晶シリコ
ン膜を堆積して上記第2多結晶シリコン膜を所定の形状
にパターン形成することを特徴とする。
In order to achieve the above object, the method for manufacturing a semiconductor device of the present invention includes forming a two-layer insulating film by overlapping a first gate oxide film and a nitride film on a semiconductor substrate. , forming a first polycrystalline silicon film on the two-layer insulating film, patterning the first polycrystalline silicon film and the nitride film, forming a second oxide film by thermal oxidation; A polycrystalline silicon film thinner than the first polycrystalline silicon film is deposited over the entire surface of the semiconductor substrate covering the oxide film, and then the thin polycrystalline silicon film is oxidized to form a polycrystalline silicon oxide film. Next, the polycrystalline silicon oxide film is etched to form the first
The polycrystalline silicon oxide film is removed from the portion where the polycrystalline silicon film does not exist, and then an interlayer insulating film is formed by thermal oxidation, and then a second polycrystalline silicon film is deposited on the entire surface of the interlayer insulating film. The method is characterized in that the second polycrystalline silicon film is patterned into a predetermined shape.

〈実施例〉 以下、この発明を図示の実施例により詳細に説明する。<Example> Hereinafter, the present invention will be explained in detail with reference to illustrated embodiments.

まず、第1図(a)に示すように、半導体基板I上にロ
コス酸化法によりフィールド酸化膜2を形成した後、第
1ゲート酸化膜3およびチッ化膜4からなる二層絶縁膜
を形成し、さらにその上に第1多結晶シリコン膜5を形
成する。そして、通常の写真食刻技術を用いて、所望の
パターンが形成されるように感光性樹脂6を残置する。
First, as shown in FIG. 1(a), a field oxide film 2 is formed on a semiconductor substrate I by the Locos oxidation method, and then a two-layer insulating film consisting of a first gate oxide film 3 and a nitride film 4 is formed. Then, a first polycrystalline silicon film 5 is further formed thereon. Then, the photosensitive resin 6 is left behind so that a desired pattern is formed using a normal photolithography technique.

次に、第1図(b)に示すように、パターンニングされ
た感光性樹脂6をマスクに上記第1多結晶シリコン膜5
.チッ化膜4をエツチングする。その後、第1図(C)
に示すように、熱酸化することにより層間絶縁膜7を形
成する。このとき、上記チッ化膜4の側面に上記層間絶
縁膜7の薄くなった部分9,9が形成される。第1図(
d)に示すように、上記半導体基板1の全面上に第1多
結晶シリコン膜5より薄い多結晶シリコン膜11を10
0〜l000人堆積する。そうすると、上記多結晶シリ
コン膜11が上記薄くなった部分9.9すなわち、くぼ
み部分9,9に堆積してひさし状の部分す。
Next, as shown in FIG. 1(b), using the patterned photosensitive resin 6 as a mask, the first polycrystalline silicon film 5 is
.. The nitride film 4 is etched. After that, Figure 1 (C)
As shown in FIG. 2, an interlayer insulating film 7 is formed by thermal oxidation. At this time, thinned portions 9, 9 of the interlayer insulating film 7 are formed on the side surfaces of the nitride film 4. Figure 1 (
As shown in d), a polycrystalline silicon film 11 thinner than the first polycrystalline silicon film 5 is deposited on the entire surface of the semiconductor substrate 1.
0-1000 people deposit. Then, the polycrystalline silicon film 11 is deposited on the thinned portions 9.9, that is, the recessed portions 9, 9, forming eaves-like portions.

boとなる。第1図(e)に示すように、上記多結晶シ
リコン膜11を酸化して、全面に多結晶シリコン酸化膜
12.12’を形成する。この過程で上記層間絶縁膜7
および薄い多結晶シリコン膜tiは酸化されて、多結晶
シリコン酸化膜12全体として見た場合には、第2図に
示す従来例の如き局部的に薄くなる部分aはなくなる。
It becomes bo. As shown in FIG. 1(e), the polycrystalline silicon film 11 is oxidized to form a polycrystalline silicon oxide film 12.12' over the entire surface. In this process, the interlayer insulating film 7
Then, the thin polycrystalline silicon film ti is oxidized, and when looking at the polycrystalline silicon oxide film 12 as a whole, there is no locally thinned portion a as in the conventional example shown in FIG.

次に、第1図(f)に示すように、多結晶シリコン酸化
膜12の全面に渡って多結晶シリコン酸化膜12をエツ
チングすることにより第1多結晶シリコン膜5の存在し
ない部分の酸化膜12°を除去する。次に、第1図(g
)に示すように、層間絶縁膜7を形成し、続いて第1図
(h)に示すように、第2多結晶シリコン膜8を被着す
る。その後、第1図(Dに示すように上記第2多結晶シ
リコン膜8を所望の形状にパターンニングして、MOS
ダイナミックメモリLSIが製造される。
Next, as shown in FIG. 1(f), by etching the polycrystalline silicon oxide film 12 over the entire surface of the polycrystalline silicon oxide film 12, the oxide film is etched in the areas where the first polycrystalline silicon film 5 does not exist. Remove 12°. Next, in Figure 1 (g
), an interlayer insulating film 7 is formed, and then, as shown in FIG. 1(h), a second polycrystalline silicon film 8 is deposited. Thereafter, the second polycrystalline silicon film 8 is patterned into a desired shape as shown in FIG.
A dynamic memory LSI is manufactured.

この工程を経るこ、とにより、第2図(d)に示す如く
、チッ化膜4の側面の酸化膜のくぼみ部分aを薄い多結
晶シリコン膜で埋め、それを酸化することにより、従来
法に見られるチッ化膜側面での酸化膜の厚さの減少が防
止でき、かつ、層間絶縁膜7の絶縁破壊強度を向上でき
、さらに第2多結晶シリコン膜8の異方性エツチングに
よるパターンニングの際のチッ化膜側面での第2多結晶
ンリコン膜8の残りを防止することができる。
By going through this process, as shown in FIG. 2(d), the recessed part a of the oxide film on the side surface of the nitride film 4 is filled with a thin polycrystalline silicon film, and by oxidizing it, the conventional method It is possible to prevent the decrease in the thickness of the oxide film on the side surface of the nitride film, which is seen in the above, and to improve the dielectric breakdown strength of the interlayer insulating film 7, and to pattern the second polycrystalline silicon film 8 by anisotropic etching. It is possible to prevent the second polycrystalline silicon film 8 from remaining on the side surface of the nitride film during this process.

〈発明の効果〉 以上の説明から明らかなように、この発明によれば、チ
ッ化膜の側面の第2酸化膜の薄くなったくぼみ部分を第
1多結晶シリコン膜より薄い多結晶シリコン膜で埋め、
次いで、これを酸化して多結晶シリコン酸化膜を形成し
、さらにこれを熱酸化して層間絶縁膜を形成して、層間
絶縁膜全体としてみた場合には均一な厚さとなり、局部
的に薄くなる部分がなくなるので、層間絶縁膜の絶縁破
壊強度を向上でき、かつ、第2多結品シリコン膜の異方
性エツチングによるパターンニングの際のチッ化膜側面
における従来例で生じていたひさし状に残る部分がなく
なるので、半導体装置の性能を向上でき、歩留も向上で
きる。
<Effects of the Invention> As is clear from the above description, according to the present invention, the thinned hollow portion of the second oxide film on the side surface of the nitride film is filled with a polycrystalline silicon film that is thinner than the first polycrystalline silicon film. Fill,
Next, this is oxidized to form a polycrystalline silicon oxide film, which is then thermally oxidized to form an interlayer insulating film, so that the interlayer insulating film has a uniform thickness when viewed as a whole, and is locally thinned. Since the dielectric breakdown strength of the interlayer insulating film is eliminated, the dielectric breakdown strength of the interlayer insulating film can be improved, and the eaves shape that occurs in the conventional example on the side surface of the nitride film during patterning by anisotropic etching of the second multicrystalline silicon film can be eliminated. Since there is no remaining portion, the performance of the semiconductor device can be improved and the yield can also be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)から第1図(i)はこの発明の一実施例の
製造工程を示す図、第2図(a)から第2図(8)は従
来例の半導体装置の製造工程を示す図、第2図(f)は
第2図(e)のA部拡大図、第2図(g)は第2図(e
)のB部拡大図である。 1・・・半導体基板、3・・・第1ゲート酸化膜、4・
・・チッ化膜、5・・・第1多結晶シリコン膜、7・・
・層間絶縁膜、8・・・第2多結晶シリコン膜、11・
・・多結晶シリコン膜、 12.12°・・・多結晶シリコン酸化膜。 特 許 出 願 人  シャープ株式会社代 理 人 
弁理士  前出 葆 外2名第1図((1) 亭1 m(hJ 第2の(0) j 第29(b) 箪2図(C) 第2図(d) 第2図(e)
1(a) to 1(i) are diagrams showing the manufacturing process of an embodiment of the present invention, and FIGS. 2(a) to 2(8) are diagrams showing the manufacturing process of a conventional semiconductor device. Figure 2(f) is an enlarged view of part A in Figure 2(e), and Figure 2(g) is an enlarged view of part A in Figure 2(e).
) is an enlarged view of part B of FIG. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 3... First gate oxide film, 4...
... nitride film, 5... first polycrystalline silicon film, 7...
- Interlayer insulating film, 8... second polycrystalline silicon film, 11.
...Polycrystalline silicon film, 12.12°...Polycrystalline silicon oxide film. Patent applicant: Sharp Corporation Agent
Patent attorney, previously mentioned, 2 people Fig. 1 ((1) Tei 1 m (hJ 2nd (0) j No. 29 (b) Fig. 2 (C) Fig. 2 (d) Fig. 2 (e)

Claims (1)

【特許請求の範囲】[Claims] (1)半導体基板上に第1ゲート酸化膜とチッ化膜を重
ねて二層絶縁膜を形成し、上記二層絶縁膜上に第1多結
晶シリコン膜を形成し、上記第1多結晶シリコン膜と上
記チッ化膜をパターンニングした後、熱酸化により第2
酸化膜を形成し、上記第2酸化膜を覆って上記半導体基
板の全面上に上記第1多結晶シリコン膜よりも薄い多結
晶シリコン膜を堆積し、次に上記薄い多結晶シリコン膜
を酸化して多結晶シリコン酸化膜を形成し、次に上記多
結晶シリコン酸化膜のエッチングを行なって上記第1多
結晶シリコン膜の存在しない部分の上記多結晶シリコン
酸化膜を除去し、その後、熱酸化により層間絶縁膜を形
成し、次に上記層間絶縁膜の全面に第2多結晶シリコン
膜を堆積して上記第2多結晶シリコン膜を所定の形状に
パターン形成することを特徴とする半導体装置の製造方
法。
(1) forming a two-layer insulating film by overlapping a first gate oxide film and a nitride film on a semiconductor substrate; forming a first polycrystalline silicon film on the two-layer insulating film; After patterning the film and the nitride film, a second layer is formed by thermal oxidation.
forming an oxide film, depositing a polycrystalline silicon film thinner than the first polycrystalline silicon film over the entire surface of the semiconductor substrate covering the second oxide film, and then oxidizing the thin polycrystalline silicon film. Next, the polycrystalline silicon oxide film is etched to remove the polycrystalline silicon oxide film in the area where the first polycrystalline silicon film does not exist, and then thermal oxidation is performed to form a polycrystalline silicon oxide film. Manufacturing a semiconductor device characterized by forming an interlayer insulating film, then depositing a second polycrystalline silicon film on the entire surface of the interlayer insulating film, and patterning the second polycrystalline silicon film into a predetermined shape. Method.
JP4730985A 1985-03-08 1985-03-08 Manufacture of semiconductor device Pending JPS61206240A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4730985A JPS61206240A (en) 1985-03-08 1985-03-08 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4730985A JPS61206240A (en) 1985-03-08 1985-03-08 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS61206240A true JPS61206240A (en) 1986-09-12

Family

ID=12771691

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4730985A Pending JPS61206240A (en) 1985-03-08 1985-03-08 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS61206240A (en)

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