JPS61210661A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61210661A JPS61210661A JP60052125A JP5212585A JPS61210661A JP S61210661 A JPS61210661 A JP S61210661A JP 60052125 A JP60052125 A JP 60052125A JP 5212585 A JP5212585 A JP 5212585A JP S61210661 A JPS61210661 A JP S61210661A
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline silicon
- film
- silicon film
- oxide film
- etched
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 239000004065 semiconductor Substances 0.000 title claims description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 87
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 11
- 239000002344 surface layer Substances 0.000 claims abstract description 4
- 239000011229 interlayer Substances 0.000 claims description 15
- 150000004767 nitrides Chemical class 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 9
- 239000010410 layer Substances 0.000 claims description 8
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims 1
- 239000011347 resin Substances 0.000 abstract description 9
- 229920005989 resin Polymers 0.000 abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- 238000007796 conventional method Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 8
- 238000000059 patterning Methods 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
〈産業」二の利用分野〉
この発明は、ＭＯ９ＬＳ＋（モス集積回路）等の半導体
装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION <Industry> Second Field of Application The present invention relates to a method of manufacturing a semiconductor device such as MO9LS+ (MOS integrated circuit).
〈従来の技術〉
従来、例えば、第２図（ａ）から第２図（ｇ）までに示
すようなシリコンゲ−１−Ｍ ＯＳグイナミソクメモリ
ＬＳＩの製造方法がある。まず、第２図（ａ）に示すよ
うに、半導体基板１上にロコス酸化法によりフィールド
酸化膜２を形成した後、第１ゲート酸化膀３およびヂノ
化膜４を形成し、さらに第１多結晶シリコン膜５を形成
して、通常の写真食刻技術を用いて、所望のパターンか
形成されろように感光性樹脂６を残置させろ。<Prior Art> Conventionally, there is a method of manufacturing a silicon game 1-MOS memory LSI as shown in FIGS. 2(a) to 2(g), for example. First, as shown in FIG. 2(a), a field oxide film 2 is formed on a semiconductor substrate 1 by the Locos oxidation method, and then a first gate oxide film 3 and a diodide film 4 are formed, and then a first gate oxide film 3 and a diodide film 4 are formed. A polycrystalline silicon film 5 is formed, and a photosensitive resin 6 is left behind so that a desired pattern can be formed using a conventional photolithography technique.
次に、第２図（１））に示すように、パターンニングさ
れた感光性樹脂６をマスクに上記第１多結晶ノリコン膜
５、チン化膜４、第１ゲート酸化膜３を順次エツチング
した後、第２図（Ｃ）に示すように、上記半導体基板ｌ
を熱酸化することににす、層間絶縁膜７を形成する。そ
の後、第２図（ｄ）に示すように、第２多結晶シリコン
模８を被着し、最後に、第２図（ｅ）に示すように、通
常の写真食刻技術を用い、第２多結晶シリコン膜８を所
定の形状にパターンニングしている。Next, as shown in FIG. 2(1)), the first polycrystalline silicon film 5, the tinned film 4, and the first gate oxide film 3 were sequentially etched using the patterned photosensitive resin 6 as a mask. After that, as shown in FIG. 2(C), the semiconductor substrate l
An interlayer insulating film 7 is formed by thermal oxidation. Thereafter, as shown in FIG. 2(d), a second polycrystalline silicon pattern 8 is deposited, and finally, as shown in FIG. 2(e), a second Polycrystalline silicon film 8 is patterned into a predetermined shape.
〈発明が解決しようとする問題点〉
ところが、上記製造方法では、第２図（ｆ）中に示され
る部分ａ、ずなわちチン化膜４の側面に形成される層間
絶縁膜７の部分ａが局部的に薄くなるため、第１多結晶
ノリコン膜５と第２多結晶シリコン膜８とが第２図（ｆ
）中の部分ａで、電気的にショートする可能性が高くな
る問題がある。<Problems to be Solved by the Invention> However, in the above manufacturing method, the portion a shown in FIG. 2 (f), the first polycrystalline silicon film 5 and the second polycrystalline silicon film 8 become thin locally.
) There is a problem in that there is a high possibility of electrical short-circuiting at part a.
また、上記第２多結晶シリコン膜８を異方性エツチング
でパターンニングする際、層間絶縁膜７が第２図（ｇ）
に示すように層間絶縁膜７の薄くなる部分に隣接する部
分りでひさし状となっているため、この部分すに第２多
結晶シリコン膜８°がエツチングされずに残り、第２多
結晶ノリコン配線８同志でショートする可能性が高くな
り、期待される歩留が得られない問題がある。Furthermore, when patterning the second polycrystalline silicon film 8 by anisotropic etching, the interlayer insulating film 7 is etched as shown in FIG. 2(g).
As shown in the figure, since the part adjacent to the thinner part of the interlayer insulating film 7 has an eave shape, 8 degrees of the second polycrystalline silicon film remains without being etched in this part, and the second polycrystalline silicon film 8 is left unetched. There is a problem that the possibility of short-circuiting between the wiring lines 8 becomes high, and the expected yield cannot be obtained.
そこで、この発明の目的は、層間絶縁膜の耐圧の向上と
、第１多結晶シリコン膜の側面の形状の改善を図って、
第１多結晶シリコン膜と第２多結晶シリコン膜とが電気
的にショートするのを防止し、かつ、第２多結晶シリコ
ン配線同志がショートするのを防止し、期待される歩留
が得られる半導体装置の製造方法を提供することにある
。Therefore, an object of the present invention is to improve the breakdown voltage of the interlayer insulating film and the shape of the side surface of the first polycrystalline silicon film.
The expected yield can be obtained by preventing electrical short-circuiting between the first polycrystalline silicon film and the second polycrystalline silicon film, as well as preventing short-circuiting between the second polycrystalline silicon wirings. An object of the present invention is to provide a method for manufacturing a semiconductor device.
〈問題点を解決するための手段〉
上記目的を達成するため、この発明の半導体装置の製造
方法は、半導体基板上に第１ゲート酸化膜とチン化膜を
重ねて二層絶縁膜を形成し、上記二層絶縁膜上に第１多
結晶シリコン膜を形成し、上記第１多結晶シリコン膜を
所定の形状にパターンニングし、次に上記チン化膜を上
記所定の形状にパターンニングされて残っている第１多
結晶シリコン膜と第１ゲート酸化膜の間に存する端部ま
で過度にエツチングし、上記第１多結晶シリコン膜を覆
って上記半導体基板の全面上に上記第１多結晶シリコン
膜よりも薄い多結晶ノリコン膜を堆積し、次に上記薄い
多結晶シリコン膜および上記第１多結晶シリコン膜の表
面層を酸化して多結晶ノリコン酸化膜を形成し、次に上
記多結晶シリコン酸化膜のエツチングを行なって、上記
第１多結晶シリコン膜の存在しない部分の上記多結晶シ
リコン酸化膜を除去し、その後、熱酸化により層間絶縁
膜を形成し、次に上記層間絶縁膜の全面に第２多結晶シ
リコン膜を堆積して上記第２多結晶シリコン膜を所定の
形状にパターン形成する。<Means for Solving the Problems> In order to achieve the above object, the method for manufacturing a semiconductor device of the present invention includes forming a two-layer insulating film by overlapping a first gate oxide film and a tinned film on a semiconductor substrate. , forming a first polycrystalline silicon film on the two-layer insulating film, patterning the first polycrystalline silicon film into a predetermined shape, and then patterning the tinned film into the predetermined shape. The first polycrystalline silicon film is etched excessively to the edge existing between the remaining first polycrystalline silicon film and the first gate oxide film, and the first polycrystalline silicon film is etched over the entire surface of the semiconductor substrate, covering the first polycrystalline silicon film. A polycrystalline silicon film thinner than the polycrystalline silicon film is deposited, and then the surface layer of the thin polycrystalline silicon film and the first polycrystalline silicon film is oxidized to form a polycrystalline silicon oxide film, and then the polycrystalline silicon film is deposited. The oxide film is etched to remove the polycrystalline silicon oxide film in areas where the first polycrystalline silicon film does not exist, and then an interlayer insulating film is formed by thermal oxidation, and then the entire surface of the interlayer insulating film is etched. Then, a second polycrystalline silicon film is deposited, and the second polycrystalline silicon film is patterned into a predetermined shape.
〈実施例〉 以下、この発明を図示の実施例により詳細に説明する。<Example> Hereinafter, the present invention will be explained in detail with reference to illustrated embodiments.
まず、第１図（ａ）に示すように、半導体基板１」二に
ロコス酸化法によりフィールド酸化膜２を形成した後、
第１ゲート酸化膜３とチン化膜４からなる二層絶縁膜を
形成し、さらにその」二に化学的気相成長法により第１
多結晶シリコン膜５を４０００〜５０００人の厚さで被
着する。その後、通常の写真食刻技術を用いて感光性樹
脂６が所望の形状となるように上記第１多結晶シリコン
膜５」二に感光性樹脂６を残置する。次に、第１図（ｂ
）に示すように、パターンニングされた感光性樹脂６を
マスクに上記第１多結晶シリコン膜５をエツチングした
後、上記感光性樹脂６を除去する。上記パターンニング
された第１多結晶シリコン膜５をマスクにリン酸系の液
で上記チッ化膜４を約２００人だけエツチングして、図
中Ａ部分に示すように上記第１多結晶シリコン膜５の端
部から内へ約２００人だけ上記チン化膜４がくぼんだ状
態に上記チッ化膜４を過度にエツチングする（以下、こ
のエツチングをオーバエツチングという）。すなわち、
このオーバエツチングにより、パターンニングされて残
っている第１多結晶シリコン膜５と第１ゲート酸化膜３
の間に存する端部２０が除去される。First, as shown in FIG. 1(a), after forming a field oxide film 2 on a semiconductor substrate 1'' by the Locos oxidation method,
A two-layer insulating film consisting of a first gate oxide film 3 and a tinned film 4 is formed, and then a first
A polycrystalline silicon film 5 is deposited to a thickness of 4,000 to 5,000 layers. Thereafter, the photosensitive resin 6 is left on the first polycrystalline silicon film 5'' using a conventional photolithography technique so that the photosensitive resin 6 has a desired shape. Next, Figure 1 (b
), the first polycrystalline silicon film 5 is etched using the patterned photosensitive resin 6 as a mask, and then the photosensitive resin 6 is removed. Using the patterned first polycrystalline silicon film 5 as a mask, the nitride film 4 is etched by about 200 people using a phosphoric acid solution, and the first polycrystalline silicon film is etched as shown in part A in the figure. The nitride film 4 is excessively etched so that the nitride film 4 is recessed by about 200 degrees inward from the edge of the nitride film (hereinafter, this etching is referred to as over-etching). That is,
This overetching removes the patterned remaining first polycrystalline silicon film 5 and first gate oxide film 3.
The end portion 20 located in between is removed.
その後、第１図（ｃ）に示ずように、上記半導体基板ｌ
の全面上に第１多結晶シリコン膜５より薄い多結晶シリ
コン膜１１を厚さ１００〜１０００人堆積する。上記多
結晶シリコン膜１１は多結晶シリコン膜１１が上記チッ
化膜４の除去された第１ゲ−川・酸化膜３と第１多結晶
シリコン膜５との間の空所にも堆積する。次に、第１図
（ｄ）に示すように、上記薄い多結晶ノリコン膜１１お
」；び上記第１多結晶シリコン膜５の表面層を酸化して
、全面に多結晶シリコン酸化膜１２を形成する。この過
程で薄い多結晶シリコン膜ＩＩは全て酸化され、上記多
結晶シリコン酸化膜１２全体として見た場合に上記チッ
化膜４がオーバエツチングされているので、第２図（Ｃ
）に示す従来例の如き局部的に傳くなる部分ａはなくな
る。次に、第１図（ｅ）に示すように、上記多結晶シリ
コン酸化膜１２の全面に渡って多結晶シリコン酸化膜１
２をエツチングすることにより第１多結晶シリコン膜５
の存在しない部分の多結晶シリコン酸化膜１２′ を除
去する。Thereafter, as shown in FIG. 1(c), the semiconductor substrate l
A polycrystalline silicon film 11 thinner than the first polycrystalline silicon film 5 is deposited on the entire surface to a thickness of 100 to 1000 layers. The polycrystalline silicon film 11 is also deposited in the space between the first silicon oxide film 3 and the first polycrystalline silicon film 5 from which the nitride film 4 has been removed. Next, as shown in FIG. 1(d), the surface layer of the thin polycrystalline silicon film 11 and the first polycrystalline silicon film 5 is oxidized to form a polycrystalline silicon oxide film 12 on the entire surface. Form. In this process, the thin polycrystalline silicon film II is completely oxidized, and when the polycrystalline silicon oxide film 12 is viewed as a whole, the nitride film 4 is overetched, as shown in FIG.
) The locally changing portion a as in the conventional example is eliminated. Next, as shown in FIG. 1(e), a polycrystalline silicon oxide film 1 is formed over the entire surface of the polycrystalline silicon oxide film 12.
2 by etching the first polycrystalline silicon film 5.
The polycrystalline silicon oxide film 12' is removed from the portions where the polycrystalline silicon oxide film 12' is not present.
さらに、第１図（ｆ）に示すように、熱酸化により層間
絶縁膜７を形成し、続いて第１図（ｇ）に示すように、
第２多結晶シリコン膜８を被着する。その後、第１図（
ｈ）に示すように、所定の形状に上記第２多結晶シリコ
ン膜８をパターンニングしてＭＯＳダイナミックメモリ
ＬＳＩが製造される。Furthermore, as shown in FIG. 1(f), an interlayer insulating film 7 is formed by thermal oxidation, and then as shown in FIG. 1(g),
A second polycrystalline silicon film 8 is deposited. After that, see Figure 1 (
As shown in h), a MOS dynamic memory LSI is manufactured by patterning the second polycrystalline silicon film 8 into a predetermined shape.
この工程を経ることにより、第１図（ｆ）に示ず如くチ
ッ化膜４をオーバエツチングしたくぼみ部分Ａを多結晶
ノリコン膜１１で埋め、それを酸化するため、従来例に
見られるチッ化膜４の側面での層間絶縁膜７の厚さの減
少を防止でき、かつ、第２多結晶シリコン膜８の異方性
エツチングによるパターンニングの際のチッ化膜側面の
第２多結晶シリコン膜８のエッチ残りを防止できて、層
間絶縁膜７の絶縁破壊強度を向」二できる。By going through this process, as shown in FIG. 1(f), the recessed portion A where the nitride film 4 has been overetched is filled with the polycrystalline Noricon film 11, and it is oxidized, so that the nitride film 4 is overetched. The thickness of the interlayer insulating film 7 on the side surface of the film 4 can be prevented from decreasing, and the second polycrystalline silicon film on the side surface of the nitride film during patterning by anisotropic etching of the second polycrystalline silicon film 8 can be prevented. 8 can be prevented from remaining after etching, and the dielectric breakdown strength of the interlayer insulating film 7 can be improved.
〈発明の効果〉
以上の説明から明らかなように、この発明によれば、第
１多結晶シリコン膜をエツチングした後、第１多結晶シ
リコン膜をマスクにチッ化膜をそのチッ化膜側面にくぼ
み部分が形成されるように過度にエツチングし、このく
ぼみ部分を第１多結晶シリコン膜より薄い多結晶シリコ
ン膜で埋め、次いでそれを酸化して多結晶シリコン酸化
膜を形成し、さらにこれを熱酸化して層間絶縁膜を形成
して、層間絶縁膜が局部的に薄くなる部分がなくな一′
ｌ−
るので、層間絶縁膜の絶縁破壊強度を向上でき、かつ、
第２多結晶シリコン膜の異方性エツチングによるパター
ンニングの際における従来例の如きヂソ化膜側面に第２
多結晶シリコン膜がひさし状に残る部分がなくなるので
、半導体装置の性能を向上でき、歩留りも向上できる。<Effects of the Invention> As is clear from the above description, according to the present invention, after etching the first polycrystalline silicon film, a nitride film is etched on the side surface of the nitride film using the first polycrystalline silicon film as a mask. Excessive etching is performed to form a recessed portion, and this recessed portion is filled with a polycrystalline silicon film thinner than the first polycrystalline silicon film, which is then oxidized to form a polycrystalline silicon oxide film, and this is further etched. By thermally oxidizing and forming an interlayer insulating film, the interlayer insulating film is no longer locally thinned.
l-, the dielectric breakdown strength of the interlayer insulating film can be improved, and
When patterning the second polycrystalline silicon film by anisotropic etching, a second layer is placed on the side surface of the dioxide film as in the conventional example.
Since no portion of the polycrystalline silicon film remains in the form of an eaves, the performance of the semiconductor device can be improved and the yield can also be improved.
第１図（ａ）から第１図（ｈ）はこの発明の一実施例の
製造工程を示す図、第２図（ａ）から第２図（ｅ）は従
来例の半導体装置の製造工程、第２図（「）は第２図（
ｅ）のＡ部拡大図、第２図（ｇ）は第２図（ｅ）のＢ部
拡大図である。
１ 半導体基板、 ３・・・第１ゲート酸化膜、４ チ
ッ化膜、 １第１多結晶シリコン膜、７・層間絶縁膜
、 ＩＩ・・・薄い多結晶シリコン膜、１２．１２°
・−多結晶シリコン酸化膜。
特 許 出 願 人 シャープ株式会社代 理 人
弁理士 前出 葆 外２名＝８−FIGS. 1(a) to 1(h) are diagrams showing the manufacturing process of an embodiment of the present invention, and FIGS. 2(a) to 2(e) are diagrams showing the manufacturing process of a conventional example of a semiconductor device. Figure 2 (') is Figure 2 (')
Fig. 2(g) is an enlarged view of part A in Fig. 2(e). 1 Semiconductor substrate, 3... First gate oxide film, 4 Nitride film, 1 First polycrystalline silicon film, 7. Interlayer insulating film, II... Thin polycrystalline silicon film, 12.12°
-Polycrystalline silicon oxide film. Patent applicant: Sharp Corporation Agent
Patent attorney: 2 other people = 8-
Claims (1)
ねて二層絶縁膜を形成し、上記二層絶縁膜上に第１多結
晶シリコン膜を形成し、上記第１多結晶シリコン膜を所
定の形状にパターンニングし、次に上記チッ化膜を上記
所定の形状にパターンニングされて残っている第１多結
晶シリコン膜と第１ゲート酸化膜の間に存する端部まで
過度にエッチングし、上記第１多結晶シリコン膜を覆っ
て上記半導体基板の全面上に上記第１多結晶シリコン膜
よりも薄い多結晶シリコン膜を堆積し、次に上記薄い多
結晶シリコン膜および上記第１多結晶シリコン膜の表面
層を酸化して多結晶シリコン酸化膜を形成し、次に上記
多結晶シリコン酸化膜のエッチングを行なって、上記第
１多結晶シリコン膜の存在しない部分の上記多結晶シリ
コン酸化膜を除去し、その後、熱酸化により層間絶縁膜
を形成し、次に上記層間絶縁膜の全面に第２多結晶シリ
コン膜を堆積して上記第２多結晶シリコン膜を所定の形
状にパターン形成することを特徴とする半導体装置の製
造方法。(1) forming a two-layer insulating film by overlapping a first gate oxide film and a nitride film on a semiconductor substrate; forming a first polycrystalline silicon film on the two-layer insulating film; The film is patterned into a predetermined shape, and then the nitride film is patterned into the predetermined shape and is excessively patterned to the edge between the first polycrystalline silicon film and the first gate oxide film. etching, depositing a polycrystalline silicon film thinner than the first polycrystalline silicon film over the entire surface of the semiconductor substrate, covering the first polycrystalline silicon film; A surface layer of the polycrystalline silicon film is oxidized to form a polycrystalline silicon oxide film, and then the polycrystalline silicon oxide film is etched to remove the polycrystalline silicon in the portion where the first polycrystalline silicon film does not exist. After removing the oxide film, an interlayer insulating film is formed by thermal oxidation, and then a second polycrystalline silicon film is deposited on the entire surface of the interlayer insulating film, and the second polycrystalline silicon film is patterned into a predetermined shape. 1. A method of manufacturing a semiconductor device, characterized by forming a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60052125A JPS61210661A (en) | 1985-03-14 | 1985-03-14 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60052125A JPS61210661A (en) | 1985-03-14 | 1985-03-14 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61210661A true JPS61210661A (en) | 1986-09-18 |
Family
ID=12906152
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60052125A Pending JPS61210661A (en) | 1985-03-14 | 1985-03-14 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61210661A (en) |
-
1985
- 1985-03-14 JP JP60052125A patent/JPS61210661A/en active Pending
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