JPS61222158A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS61222158A
JPS61222158A JP60051315A JP5131585A JPS61222158A JP S61222158 A JPS61222158 A JP S61222158A JP 60051315 A JP60051315 A JP 60051315A JP 5131585 A JP5131585 A JP 5131585A JP S61222158 A JPS61222158 A JP S61222158A
Authority
JP
Japan
Prior art keywords
polycrystalline silicon
film
silicon film
thin
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60051315A
Other languages
Japanese (ja)
Inventor
Shigeaki Ide
繁章 井手
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP60051315A priority Critical patent/JPS61222158A/en
Publication of JPS61222158A publication Critical patent/JPS61222158A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/01Manufacture or treatment
    • H10B12/02Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03Making the capacitor or connections thereto

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To improve a layer insulation withstand-voltage and reform a side surface shape of the first polycrystalline silicon film, by overetching a nitrided film, covering only the side surface part with a thin polycrystal silicon film, and then forming a layer insulation oxide film. CONSTITUTION:Likewise as before, the first polycrystalline silicon film 15 is etched, with patterning-processed photo-sensitive resin 16 serving as mask, and after removing the photo-sensitive resin 16, a nitrided film 14 is overetched, with a patterning-processed first polycrystalline silicon film 15 serving as mask. Then, a thin polycrystalline silicon film 17 is piled all over the surface, and the thin polycrystalline silicon film 17 is etched, by thickness of he film, by the use of an anisotropic etching, so that only the side surface part of the nitrided film 14 is covered with the thin polycrystalline silicon film 17. Next, with the first polycrystalline silicon film 15 serving as mask, the first gate oxide film 13 is removed, and a layer insulation oxide film is formed by thermally oxidizing a semiconductor substrate 11, and then the second polycrystalline silicon film is made to grow into a desired shape patterning.

Description

【発明の詳細な説明】 〈産業上の利用分野〉 本発明は半導体装置(半導体集積回路:シリコンゲー)
MOSダイナミックメモリ集積回路等)の製造方法に関
する。
[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a semiconductor device (semiconductor integrated circuit: silicon game).
MOS dynamic memory integrated circuit, etc.).

〈発明の概要〉 本発明の、半導体装置の製造方法は、以下のa)乃至e
)の工程から成ることを特徴とするものである。
<Summary of the Invention> The method of manufacturing a semiconductor device of the present invention includes the following steps a) to e.
).

a)半導体基板上にゲート酸化膜、窒化膜を重ねて二層
絶縁膜を形成し、更に、この二層絶縁膜上に第1の多結
晶シリコン膜を形成する工程。
a) Step of forming a two-layer insulating film by overlapping a gate oxide film and a nitride film on a semiconductor substrate, and further forming a first polycrystalline silicon film on this two-layer insulating film.

b)前記第1の多結晶シリコン膜を所定の形状にパター
ニングする工程。
b) Patterning the first polycrystalline silicon film into a predetermined shape.

C)前記窒化膜を過度にエツチングした後に、前起生導
体基板上全面に前記第1の多結晶シリコン膜よりも薄い
多結晶シリコン膜を堆積する工程。
C) After excessively etching the nitride film, a step of depositing a polycrystalline silicon film thinner than the first polycrystalline silicon film over the entire surface of the raised conductor substrate.

d)前記薄い多結晶シリコン膜をその膜厚弁だけ異方性
エツチングし、前記窒化膜の側面部だけに該薄い多結晶
シリコン膜を残存させる工程。
d) A step of anisotropically etching the thin polycrystalline silicon film by its thickness, leaving the thin polycrystalline silicon film only on the side surfaces of the nitride film.

e)該窒化膜側面部の薄い多結晶シリコン膜及び前記第
1の多結晶シリコン膜の表面層を酸化した後、全面に第
2の多結晶シリコン膜を堆積し、この第2の多結晶シリ
コン膜を所定の形状にパターニングする工程。
e) After oxidizing the thin polycrystalline silicon film on the side surface of the nitride film and the surface layer of the first polycrystalline silicon film, a second polycrystalline silicon film is deposited on the entire surface, and this second polycrystalline silicon film is A process of patterning a film into a predetermined shape.

〈従来の技術〉 まず、従来の方法について説明する。<Conventional technology> First, a conventional method will be explained.

第2図は従来方法の製造工程図である。FIG. 2 is a manufacturing process diagram of a conventional method.

Iゲート酸化膜8.窒化膜4を形成し、さらに多結晶シ
リコン膜5を形成し、通常の写真食刻技術を用いて、所
望のパターンが形成されるように感光性樹脂6を残置さ
せる。
I gate oxide film 8. A nitride film 4 is formed, and then a polycrystalline silicon film 5 is formed, and a photosensitive resin 6 is left behind so that a desired pattern is formed using a normal photolithography technique.

次に第2図(b)に示すように、パターニングされた感
光性樹脂6をマスクに前記多結晶シリコン膜5、窒化膜
4.第1ゲート酸化膜3を順次エツチングした後、第2
図(e)に示す様に、前記半導体基板lを熱酸化するこ
とにより層間絶縁酸化膜7を形成する。
Next, as shown in FIG. 2(b), using the patterned photosensitive resin 6 as a mask, the polycrystalline silicon film 5, the nitride film 4. After sequentially etching the first gate oxide film 3, the second gate oxide film 3 is etched.
As shown in Figure (e), an interlayer insulating oxide film 7 is formed by thermally oxidizing the semiconductor substrate l.

次に、第2図(d)に示すように、第2の多結晶シリコ
ン膜8を被着する。
Next, as shown in FIG. 2(d), a second polycrystalline silicon film 8 is deposited.

最後に、第2図(e)に示すように、通常の写真食刻技
術を用い、第2の多結晶シリコン膜8を所定の形状にパ
ターニングする。
Finally, as shown in FIG. 2(e), the second polycrystalline silicon film 8 is patterned into a predetermined shape using a normal photolithography technique.

〈発明が解決しようとする問題点〉 上記従来法によれば、第2図(e)に9として示される
個所、すなわち、窒化膜4の側面に形成される酸化膜7
が局部的に薄くなるために(拡大図を第3図+11に示
す)、第1の多結晶シリコン膜5と第2の多結晶シリコ
ン膜8とが、該第2図(e)の9の個所で電気的にシ目
−卜する可能性が高くなり、また、第2の多結晶シリコ
ン膜8を異方性エツチングでパターニングする際、眉間
絶縁酸化膜7が第2 図(e)の1oの部分でひさし状
となっ′C“るため(拡大図を第8図(2)に示す)、
この部分に第2の多結晶シリコン8がエツチングされず
に残り、第2の多結晶シリコン同士でショートする可能
性が高くなシ、期待される歩留まシが得られないという
欠点を有していた。
<Problems to be Solved by the Invention> According to the above conventional method, the oxide film 7 formed at the location shown as 9 in FIG. 2(e), that is, the side surface of the nitride film 4
(An enlarged view is shown in FIG. 3+11), the first polycrystalline silicon film 5 and the second polycrystalline silicon film 8 become thinner locally (an enlarged view is shown in FIG. 3+11). In addition, when patterning the second polycrystalline silicon film 8 by anisotropic etching, the insulating oxide film 7 between the eyebrows is Because it becomes an eave shape at the part (an enlarged view is shown in Figure 8 (2)),
The second polycrystalline silicon 8 remains in this part without being etched, and there is a high possibility that the second polycrystalline silicon will short-circuit with each other, and the expected yield rate cannot be obtained. was.

本発明は従来法に於ける上記問題点を解決することを目
的とするものである。すなわち、本発明は、上記欠点を
取り除き、眉間絶縁耐圧の向上と、第1多結晶シリコン
膜の側面の形状の改善を図ることを可能にする半導体装
置の製造方法を提供するものである。
The present invention aims to solve the above-mentioned problems in the conventional method. That is, the present invention provides a method of manufacturing a semiconductor device that eliminates the above-mentioned drawbacks and makes it possible to improve the glabellar dielectric strength and the shape of the side surface of the first polycrystalline silicon film.

〈問題点を解決するた込の手段〉 窒化膜をオーバーエツチングし、その側面部だけを薄い
多結晶シリコン膜で覆い、その後層間絶縁酸化膜を形成
する構成とする。
<Means for resolving the problem> The nitride film is over-etched, only the side surfaces thereof are covered with a thin polycrystalline silicon film, and then an interlayer insulating oxide film is formed.

〈作用〉 上記構成とすることにより、層間絶縁酸化膜の局部的な
膜厚減少を防止することができるので、従来問題点とな
っていた多結晶シリコン膜間の短絡を解消することがで
きるものである。
<Function> By having the above structure, it is possible to prevent a local decrease in the thickness of the interlayer insulating oxide film, thereby solving the problem of short circuits between polycrystalline silicon films, which has been a problem in the past. It is.

〈実施例〉 以下、実施例に基づいて本発明の詳細な説明する。<Example> Hereinafter, the present invention will be described in detail based on Examples.

第1図は本発明の一実施例の製造工程図である。FIG. 1 is a manufacturing process diagram of an embodiment of the present invention.

まず、半導体基板ll上にロコス酸化法によりフィール
ド酸化膜12を形成した後、第1ゲート酸化膜13.窒
化膜14を形成し、引き続き化学的気相成長法により厚
さ4000〜500oλの第1の多結晶シリコン膜15
を形成し、通常の写真食刻技術により感光性樹脂16i
所望の形状となるように残置させて、第1図(a)に示
される構造を得る。
First, a field oxide film 12 is formed on a semiconductor substrate 11 by the Locos oxidation method, and then a first gate oxide film 13. After forming a nitride film 14, a first polycrystalline silicon film 15 with a thickness of 4000 to 500oλ is formed by chemical vapor deposition.
and photosensitive resin 16i by ordinary photolithography technology.
The structure shown in FIG. 1(a) is obtained by leaving it in a desired shape.

次に1パターニングされた感光性樹脂16をマスクに第
1の多結晶シリコン膜15iエツチングし、前記感光性
樹脂16を除去した後、パターニングされた前記第1の
多結晶シリコン膜15iマスクに前記窒化膜14t−リ
ン酸系の液で約200λオーバーエツチングさせて、第
1図(b)に示される構造を得る。
Next, the first polycrystalline silicon film 15i is etched using the patterned photosensitive resin 16 as a mask, and after removing the photosensitive resin 16, the nitrided silicon film 15i is etched onto the patterned first polycrystalline silicon film 15i as a mask. The film 14 is over-etched by about 200λ with a phosphoric acid solution to obtain the structure shown in FIG. 1(b).

次に、第1図(c)に示すように、全面に薄い多結晶シ
リコン膜17i100〜100OA堆積する。
Next, as shown in FIG. 1(c), a thin polycrystalline silicon film 17i with a thickness of 100 to 100 OA is deposited over the entire surface.

次に、異方性エツチングにより、前記薄い多結晶シリコ
ン膜17をその膜厚分エツチングし、前記窒化膜14の
側面部だけを薄い多結晶シリコン膜17で覆い、第1図
(d)の構造を得る。
Next, the thin polycrystalline silicon film 17 is etched by the thickness thereof by anisotropic etching, and only the side surfaces of the nitride film 14 are covered with the thin polycrystalline silicon film 17, resulting in the structure shown in FIG. 1(d). get.

次に、第1のゲート電極形状にパターニングされた第1
の多結晶シリコン膜15をマスクに、第1の多結晶シリ
コン膜の存在しない部分の第1ゲート酸化膜13を酸化
膜エツチングにより除去し、第1図(e)の形状を得る
Next, the first gate electrode patterned in the shape of the first gate electrode is
Using the polycrystalline silicon film 15 as a mask, portions of the first gate oxide film 13 where the first polycrystalline silicon film does not exist are removed by oxide film etching to obtain the shape shown in FIG. 1(e).

次に、半導体基板11を熱酸化することにより、第1図
(f)に示す如く、眉間絶縁酸化膜18i形成し、続い
て第2多結晶シリコン膜!9を成長して、第1図(ロ)
)の構造を得る。この第2多結晶シリコン膜19を所望
の形状にパターニングして第1図(h)の構造を得る。
Next, by thermally oxidizing the semiconductor substrate 11, as shown in FIG. 1(f), an insulating oxide film 18i between the eyebrows is formed, followed by a second polycrystalline silicon film! Growing up to 9, Figure 1 (b)
) to obtain the structure. This second polycrystalline silicon film 19 is patterned into a desired shape to obtain the structure shown in FIG. 1(h).

〈発明の効果〉 以上詳細に説明したように、本発明によれば、窒化膜を
オーバーエツチングし、その側面部だけを薄い多結晶シ
リコン膜で覆うことにより、前記層間絶縁酸化膜を形成
する際、従来法に見られた第1の多結晶シリコン膜の側
面下部に於ける局部的な酸化膜厚の減少を防止でき、従
来法の欠点とされていた眉間絶縁酸化膜の絶縁破壊強度
を向上させることができると共に、第2多結晶シリコン
膜の異方性エツチングによるパターニングの際もエツチ
ング残りの発生を防止することができ、第2多結晶シリ
コン膜同士のショートも防止することができるものであ
る。
<Effects of the Invention> As described above in detail, according to the present invention, the nitride film is over-etched and only the side surfaces thereof are covered with a thin polycrystalline silicon film, thereby making it possible to form the interlayer insulating oxide film. , it is possible to prevent the local reduction in oxide film thickness at the lower side of the first polycrystalline silicon film, which was seen in the conventional method, and improve the dielectric breakdown strength of the glabella insulating oxide film, which was a drawback of the conventional method. In addition, it is possible to prevent etching residues from occurring during patterning of the second polycrystalline silicon film by anisotropic etching, and it is also possible to prevent short circuits between the second polycrystalline silicon films. be.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)乃至(h)は本発明の一実施例の製造工程
図、第2図(a)乃至(e)は従来の製造方法の製造工
程図、第3図(1) 、 (2)は第2図(e)の部分
拡大図である。 符号の説明 1:半導体基板、2:フィールド酸化膜、3:第1ゲー
ト酸化膜、4:ゲート窒化膜、5:第1多結晶シリコン
膜、6:感光性樹脂、7:層間絶縁酸化膜、8:第2多
結晶シリコン膜、9:層間絶縁酸化膜の局部的に薄い部
分、10:第2多結晶シリコン膜のエツチング残り部分
、11:半導体基板、12:°フィールド酸化膜、18
:第1ゲート酸化膜、14:ゲート窒化膜、15:第1
多結晶シリコン膜、!6:感光性樹脂、17:薄い多結
晶シリコン膜、18二眉間絶縁酸化膜、19:第2多結
晶シリコン膜。 代理人 弁理士 福 士 愛 彦(他2名)第1図
Figures 1 (a) to (h) are manufacturing process diagrams of an embodiment of the present invention, Figures 2 (a) to (e) are manufacturing process diagrams of a conventional manufacturing method, and Figures 3 (1), ( 2) is a partially enlarged view of FIG. 2(e). Explanation of symbols 1: Semiconductor substrate, 2: Field oxide film, 3: First gate oxide film, 4: Gate nitride film, 5: First polycrystalline silicon film, 6: Photosensitive resin, 7: Interlayer insulation oxide film, 8: second polycrystalline silicon film, 9: locally thin portion of interlayer insulating oxide film, 10: etched remaining portion of second polycrystalline silicon film, 11: semiconductor substrate, 12: ° field oxide film, 18
: first gate oxide film, 14: gate nitride film, 15: first
Polycrystalline silicon film! 6: photosensitive resin, 17: thin polycrystalline silicon film, 18 bibrow insulating oxide film, 19: second polycrystalline silicon film. Agent Patent attorney Aihiko Fukushi (and 2 others) Figure 1

Claims (1)

【特許請求の範囲】 1、以下のa)乃至e)の工程から成ることを特徴とす
る、半導体装置の製造方法。 a)半導体基板上にゲート酸化膜、窒化膜を重ねて二層
絶縁膜を形成し、更に、この二層絶縁膜上に第1の多結
晶シリコン膜を形成する工程。 b)前記第1の多結晶シリコン膜を所定の形状にパター
ニングする工程。 c)前記窒化膜を過度にエッチングした後に、前記半導
体基板上全面に前記第1の多結晶シリコン膜よりも薄い
多結晶シリコン膜を堆積する工程。 d)前記薄い多結晶シリコン膜をその膜厚分だけ異方性
エッチングし、前記窒化膜の側面部だけに該薄い多結晶
シリコン膜を残存させる工程。 e)該窒化膜側面部の薄い多結晶シリコン膜及び前記第
1の多結晶シリコン膜の表面層を酸化した後、全面に第
2の多結晶シリコン膜を堆積し、この第2の多結晶シリ
コン膜を所定の形状にパターニングする工程。
[Claims] 1. A method for manufacturing a semiconductor device, characterized by comprising the following steps a) to e). a) Step of forming a two-layer insulating film by overlapping a gate oxide film and a nitride film on a semiconductor substrate, and further forming a first polycrystalline silicon film on this two-layer insulating film. b) Patterning the first polycrystalline silicon film into a predetermined shape. c) After excessively etching the nitride film, depositing a polycrystalline silicon film thinner than the first polycrystalline silicon film over the entire surface of the semiconductor substrate. d) A step of anisotropically etching the thin polycrystalline silicon film by the thickness thereof, leaving the thin polycrystalline silicon film only on the side surfaces of the nitride film. e) After oxidizing the thin polycrystalline silicon film on the side surface of the nitride film and the surface layer of the first polycrystalline silicon film, a second polycrystalline silicon film is deposited on the entire surface, and this second polycrystalline silicon film is A process of patterning a film into a predetermined shape.
JP60051315A 1985-03-13 1985-03-13 Manufacture of semiconductor device Pending JPS61222158A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60051315A JPS61222158A (en) 1985-03-13 1985-03-13 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60051315A JPS61222158A (en) 1985-03-13 1985-03-13 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS61222158A true JPS61222158A (en) 1986-10-02

Family

ID=12883481

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60051315A Pending JPS61222158A (en) 1985-03-13 1985-03-13 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS61222158A (en)

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