JPH09330922A - Method for separating element of semiconductor device - Google Patents
Method for separating element of semiconductor deviceInfo
- Publication number
- JPH09330922A JPH09330922A JP9052934A JP5293497A JPH09330922A JP H09330922 A JPH09330922 A JP H09330922A JP 9052934 A JP9052934 A JP 9052934A JP 5293497 A JP5293497 A JP 5293497A JP H09330922 A JPH09330922 A JP H09330922A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- field oxide
- element isolation
- semiconductor device
- mask pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 53
- 238000000034 method Methods 0.000 title claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 230000003647 oxidation Effects 0.000 claims abstract description 29
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 29
- 238000005530 etching Methods 0.000 claims abstract description 8
- 230000001590 oxidative effect Effects 0.000 claims abstract description 5
- 238000000059 patterning Methods 0.000 claims abstract description 5
- 238000002955 isolation Methods 0.000 claims description 36
- 150000004767 nitrides Chemical class 0.000 claims description 26
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 6
- 230000003139 buffering effect Effects 0.000 claims description 4
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 3
- 230000002265 prevention Effects 0.000 claims description 2
- 239000011800 void material Substances 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 241000293849 Cordylanthus Species 0.000 description 7
- 238000007796 conventional method Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000010354 integration Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000003963 antioxidant agent Substances 0.000 description 1
- 230000003078 antioxidant effect Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置の素子分
離方法に係り、特にシリコンの局部的な酸化法（Local
Oxidation of Silicon：ＬＯＣＯＳ）を用いる半導体装
置の素子分離方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an element isolation method for a semiconductor device, and more particularly to a local oxidation method of silicon (Local
The present invention relates to an element isolation method for a semiconductor device using Oxidation of Silicon (LOCOS).
【０００２】[0002]
【従来の技術】半導体装置において、半導体基板上に形
成されたトランジスタ、ダイオード及び抵抗などの各種
の素子を電気的に分離することは必須的である。さら
に、半導体装置の高集積化に伴い、微細な素子分離のた
めの多くの研究が行われている。素子分離領域形成工程
は全ての半導体製造工程段階における初期段階の工程で
あって、活性領域の大きさ及び後工程段階の工程マージ
ンを左右するので、半導体装置の高集積化による素子分
離領域の縮小は不可避である。2. Description of the Related Art In a semiconductor device, it is essential to electrically separate various elements such as transistors, diodes and resistors formed on a semiconductor substrate. Further, with the high integration of semiconductor devices, many studies for fine element isolation have been conducted. The device isolation region formation process is an initial process in all semiconductor manufacturing process steps, and affects the size of the active region and the process margin of the subsequent process steps. Therefore, the device isolation region is reduced due to high integration of the semiconductor device. Is unavoidable.
【０００３】半導体装置の素子分離方法としては、シリ
コンの局部的な酸化法（以下、ＬＯＣＯＳという）が一
般的に用いられる。このＬＯＣＯＳ工程は、シリコン基
板上にパッド酸化膜及び窒化膜を順次に蒸着して積層形
成する段階と、前記窒化膜をパタニングする段階と、前
記窒化膜のパタニングにより露出されるシリコン基板を
酸化させてフィールド酸化膜を形成する段階とからな
る。As a device isolation method for a semiconductor device, a local oxidation method of silicon (hereinafter referred to as LOCOS) is generally used. The LOCOS process includes a step of sequentially depositing and stacking a pad oxide film and a nitride film on a silicon substrate, a step of patterning the nitride film, and an oxidation of the silicon substrate exposed by the patterning of the nitride film. Forming a field oxide film.
【０００４】しかしながら、このような一般的なＬＯＣ
ＯＳ工程によれば、シリコン基板と窒化膜とのストレス
を緩和させるためにパッド酸化膜を形成するので、シリ
コン基板の選択酸化時にマスクとして用いられる窒化膜
の下部で前記パッド酸化膜の側面に酸素が拡散してフィ
ールド酸化膜の端部にバーズビーク（bird's beak ）が
発生する。このようなバーズビークにより、フィールド
酸化膜が前記バーズビークの長さほど活性領域側に拡張
するので、チャンネルの長さも短くなる。これにより、
スレショルド電圧が増加する“狭いチャンネル効果”が
誘発されてトランジスタの電気的な特性を劣化させると
いう問題がある。However, such a general LOC
According to the OS process, since the pad oxide film is formed to relieve the stress between the silicon substrate and the nitride film, oxygen is formed on the side surface of the pad oxide film below the nitride film used as a mask during the selective oxidation of the silicon substrate. Are diffused and bird's beaks are generated at the edges of the field oxide film. By such bird's beak, the field oxide film extends toward the active region by the length of the bird's beak, and the channel length also becomes shorter. This allows
There is a problem that the "narrow channel effect" of increasing the threshold voltage is induced and the electrical characteristics of the transistor are deteriorated.
【０００５】バーズビークにより素子分離領域は増え、
活性領域は減るので、前記ＬＯＣＯＳ工程を高集積の半
導体素子に適用することは困難である。前記バーズビー
クの発生問題を解決するため、酸化バッファー層として
用いられた前記パッド酸化膜をオキシナイトライドを用
いて形成する方法が提案している。これを図１乃至図４
を参照して説明する。The bird's beak increases the element isolation region,
Since the active area is reduced, it is difficult to apply the LOCOS process to a highly integrated semiconductor device. In order to solve the problem of bird's beak generation, a method of forming the pad oxide film used as the oxidation buffer layer by using oxynitride has been proposed. This is shown in FIGS.
This will be described with reference to FIG.
【０００６】まず、図１を参照すれば、半導体基板１１
０の上に酸化バッファー層として、例えばオキサナイト
ライド膜１２０を形成し、その上に窒化膜１３０を形成
する。図２を参照すれば、通常の写真食刻技術を用いて
フィールド酸化膜１４０が形成される部分（Ａ）の窒化
膜１３０及びオキシナイトライド膜１２０を順次に取り
除き、前記半導体基板１１０の非活性領域を露出させ
る。First, referring to FIG. 1, a semiconductor substrate 11
For example, an oxanitride film 120 is formed as an oxidation buffer layer on 0, and a nitride film 130 is formed thereon. Referring to FIG. 2, the nitride film 130 and the oxynitride film 120 in the portion (A) where the field oxide film 140 is formed are sequentially removed using a normal photo-etching technique to remove the inactive layer of the semiconductor substrate 110. Expose the area.
【０００７】図３を参照すれば、前記窒化膜１３０及び
オキシナイトライド膜１２０が部分的に食刻されて露出
された前記半導体基板１１０を熱酸化させることにより
非活性領域にフィールド酸化膜１４０を形成する。図４
を参照すれば、前記窒化膜１３０及びオキシナイトライ
ド膜１２０を完全に取り除き、活性領域を露出させる。Referring to FIG. 3, the nitride film 130 and the oxynitride film 120 are partially etched to thermally oxidize the exposed semiconductor substrate 110, thereby forming a field oxide film 140 in an inactive region. Form. FIG.
Referring to FIG. 4, the nitride layer 130 and the oxynitride layer 120 are completely removed to expose the active region.
【０００８】かかる過程により形成される従来のフィー
ルド酸化膜は、従来のＬＯＣＯＳ方法によるものよりバ
ーズビークが減少している。しかしながら、フィールド
酸化膜のエッジ部分が基板となす角度（図４のθ参照）
が小さいため、急な傾斜及び大きい段差をもたらして後
続く工程で各種の問題を発生させる。例えば、フィール
ド酸化膜の表面とシリコン基板との段差が大きく、その
角度は小さい場合、フィールド酸化膜のエッジ部分に形
成される金属配線に過多なストレスが与えられて金属配
線のショートを発生させる。かつ、前記フィールド酸化
膜上に導電層又は酸化膜を多層とする場合、アスペクト
比の大きいコンタクトホールで発生するものと類似した
ボイド（Void）が隣接するフィールド酸化膜の間に形成
して素子の動作時、誤動作を引き起こす。The conventional field oxide film formed by the above process has less bird's beaks than the conventional field oxide film. However, the angle formed by the edge of the field oxide film with the substrate (see θ in FIG. 4)
Is small, it causes a steep inclination and a large step, which causes various problems in subsequent steps. For example, when the step between the surface of the field oxide film and the silicon substrate is large and the angle is small, excessive stress is applied to the metal wiring formed at the edge portion of the field oxide film, causing a short circuit of the metal wiring. In addition, when a conductive layer or an oxide film is formed in multiple layers on the field oxide film, a void similar to that generated in a contact hole having a large aspect ratio is formed between adjacent field oxide films to form a device. In operation, it causes malfunction.
【０００９】その上、フィールド酸化膜と基板との段差
を減少させるための犠牲酸化工程により、フィールド酸
化膜のエッジ部分に接する基板の表面に溝が生じる。し
たがって、ゲート酸化膜の形成時、酸化膜の成長は小さ
くなる。これにより、酸化膜が薄く形成される現象が発
生して素子の信頼性が低下する。Moreover, the sacrificial oxidation process for reducing the step between the field oxide film and the substrate causes a groove to be formed on the surface of the substrate in contact with the edge portion of the field oxide film. Therefore, when the gate oxide film is formed, the growth of the oxide film is small. As a result, a phenomenon in which the oxide film is formed thinly occurs and the reliability of the device is reduced.
【００１０】[0010]
【発明が解決しようとする課題】本発明は、前記従来の
技術の問題点を解決するために創出されたものであり、
本発明の目的は、フィールド酸化膜の形成工程を２段階
に分けて行うことによりフィールド酸化膜の段差を減ら
すと共に、フィールド酸化膜のエッジ部分の急な傾斜を
減らすことのできる半導体装置の素子分離方法を提供す
ることにある。DISCLOSURE OF THE INVENTION The present invention was created to solve the above-mentioned problems of the prior art,
It is an object of the present invention to reduce the step of the field oxide film by performing the step of forming the field oxide film in two steps, and to reduce the steep inclination of the edge portion of the field oxide film. To provide a method.
【００１１】[0011]
【課題を解決するための手段】前記目的を達成するため
の本発明は、素子分離領域と活性領域に分けられた半導
体基板上に酸化防止マスク層を形成する第１段階と、前
記マスク層をパタニングしてマスクパターンを形成する
ことにより、素子分離領域内の前記半導体基板の一部を
露出させる第２段階と、露出された前記半導体基板を熱
酸化して所定の厚さを有する第１フィールド酸化膜を形
成する第３段階と、前記マスクパターンの側壁を部分的
に食刻して前記第１フィールド酸化膜と前記マスクパタ
ーンとの間に存在する素子分離領域内の前記半導体基板
を露出させる第４段階と、前記第１フィールド酸化膜と
前記マスクパターンとの間で露出された前記半導体基板
を熱酸化して前記第１フィールド酸化膜より薄い第２フ
ィールド酸化膜を形成する第５段階と、前記マスクパタ
ーンを取り除く第６段階とを備えることを特徴とする半
導体装置の素子分離方法を提供する。In order to achieve the above object, the present invention provides a first step of forming an antioxidant mask layer on a semiconductor substrate divided into an element isolation region and an active region, and the mask layer A second step of exposing a part of the semiconductor substrate in the isolation region by patterning to form a mask pattern, and a first field having a predetermined thickness by thermally oxidizing the exposed semiconductor substrate. A third step of forming an oxide film, and partially etching the sidewalls of the mask pattern to expose the semiconductor substrate in an isolation region existing between the first field oxide film and the mask pattern. In a fourth step, the semiconductor substrate exposed between the first field oxide layer and the mask pattern is thermally oxidized to form a second field oxide layer thinner than the first field oxide layer. A fifth step of forming, provides an isolation method for a semiconductor device, characterized in that it comprises a sixth step of removing the mask pattern.
【００１２】本発明の望ましい実施例によれば、前記マ
スク層は酸化バッファー層及び窒化膜の積層により形成
される。前記第４段階では、等方性食刻を用いて前記窒
化膜の全面を所定の厚さほど取り除き、前記等方性食刻
はリン酸（Ｈ3 ＰＯ4 ）を用いることが望ましい。本発
明の望ましい実施例によれば、前記第１フィールド酸化
膜は３０００Å以上の厚さで形成され、前記第２フィー
ルド酸化膜は２００Å以上の厚さで形成される。かつ、
フィールド酸化膜の形成時に緩衝的な役割をするよう
に、前記第２段階又は第４段階におけるマスクパターン
の形成時、前記酸化バッファー層の一部を残す。According to a preferred embodiment of the present invention, the mask layer is formed by stacking an oxidation buffer layer and a nitride film. In the fourth step, it is preferable that the entire surface of the nitride film is removed by a predetermined thickness using isotropic etching, and phosphoric acid (H 3 PO 4 ) is used for the isotropic etching. According to a preferred embodiment of the present invention, the first field oxide film is formed to a thickness of 3000 Å or more, and the second field oxide film is formed to a thickness of 200 Å or more. And,
A part of the oxidation buffer layer is left during the formation of the mask pattern in the second or fourth step so that the field oxide film plays a buffering role.
【００１３】本発明によれば、活性領域に隣接するフィ
ールド酸化膜の厚さを薄く形成するように、フィールド
酸化膜を２回にかけて形成するので、フィールド酸化膜
と活性領域との角度が大きくなると共に、これらの段差
は小さくなる。これにより、後続く工程を容易に行うこ
とができる。かつ、導電層や絶縁層を積層して形成して
も、ボイトが発生しない。したがって、素子の信頼性を
向上させ得る。According to the present invention, since the field oxide film is formed twice so that the thickness of the field oxide film adjacent to the active region is thin, the angle between the field oxide film and the active region becomes large. At the same time, these steps become smaller. This makes it possible to easily carry out subsequent steps. Moreover, no void is generated even when the conductive layer and the insulating layer are laminated. Therefore, the reliability of the device can be improved.
【００１４】[0014]
【発明の実施の形態】以下、添付した図面に基づき本発
明の実施の形態を詳しく説明する。図５乃至図１０は、
本発明の一実施例による半導体装置の素子分離方法を説
明するための断面図である。図５を参照すれば、活性領
域と素子分離領域に分けられた半導体基板１０の上に酸
化防止マスクとして、例えば酸化バッファー層２０と窒
化膜３０を順次にデポジットする。この際、前記酸化バ
ッファー層２０は、１００〜３００Å厚さのオキシナイ
トライド膜で形成することが望ましい。かつ、前記窒化
膜３０は、１００Å以上の厚さで形成することが望まし
い。Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. 5 to FIG.
FIG. 6 is a cross-sectional view illustrating an element isolation method for a semiconductor device according to an exemplary embodiment of the present invention. Referring to FIG. 5, for example, an oxidation buffer layer 20 and a nitride film 30 are sequentially deposited as an oxidation prevention mask on the semiconductor substrate 10 divided into an active region and an element isolation region. At this time, the oxidation buffer layer 20 is preferably formed of an oxynitride film having a thickness of 100 to 300Å. In addition, it is desirable that the nitride film 30 is formed with a thickness of 100 Å or more.
【００１５】図６を参照すれば、酸化バッファー層２０
及び窒化バッファー層３０が積層された結果物上にフォ
トレジストを塗布した後、それを露光・現像してフォト
レジストパターン（図示せず）を形成する。次に、フォ
トレジストパターンをマスクとして用い、基板１０上に
積層された前記層を順次に食刻して窒化膜パターン３
０’及び酸化バッファー層パターン２０’を形成するこ
とにより、前記基板１０を露出させる。この際、露出さ
れる部分１０ａの面積が最終に形成されるフィールド酸
化膜の面積より小さくすることが望ましい。Referring to FIG. 6, the oxidation buffer layer 20.
A photoresist is applied on the resultant structure having the nitriding buffer layer 30 laminated thereon, and then the photoresist is exposed and developed to form a photoresist pattern (not shown). Next, using the photoresist pattern as a mask, the layers stacked on the substrate 10 are sequentially etched to form the nitride film pattern 3
The substrate 10 is exposed by forming 0'and the oxidation buffer layer pattern 20 '. At this time, it is desirable that the area of the exposed portion 10a be smaller than the area of the field oxide film to be finally formed.
【００１６】図７を参照すれば、酸化バッファー層パタ
ーン２０’及び窒化膜パターン３０’が形成されて露出
された前記半導体基板１０を通常の方法で熱酸化させる
ことにより、所定の厚さを有する第１フィールド酸化膜
４０を形成する。この際、前記第１フィールド酸化膜４
０は、３０００Å以上の厚さ、例えば３０００〜４００
０Åの厚さで形成することが望ましい。Referring to FIG. 7, the exposed semiconductor substrate 10 having the oxide buffer layer pattern 20 'and the nitride film pattern 30' formed thereon is thermally oxidized by a conventional method to have a predetermined thickness. A first field oxide film 40 is formed. At this time, the first field oxide film 4
0 is a thickness of 3000 Å or more, for example, 3000 to 400
It is desirable to form it with a thickness of 0Å.
【００１７】図８を参照すれば、窒化膜及びオキシナイ
トライド膜を食刻する、例えばリン酸（Ｈ3 ＰＯ4 ）を
用いて第１フィールド酸化膜４０が形成されている前記
結果物の全面を湿式食刻することにより、前記窒化膜パ
ターン３０’を１５０〜２５０Å、望ましくは、２００
Åの厚さほど取り除く。前記窒化膜パターン２０’の食
刻により露出される前記酸化バッファー層パターン２
０’を、例えばＢＯＥ（Buffered Oxide Etchant）を用
いて取り除く。Referring to FIG. 8, the nitride film and the oxynitride film are etched, for example, the first field oxide film 40 is formed using phosphoric acid (H 3 PO 4 ) on the entire surface of the resultant structure. By wet-etching the nitride film pattern 30 'to 150-250Å, preferably 200
Remove about Å thick. The oxidation buffer layer pattern 2 exposed by the etching of the nitride film pattern 20 '.
0'is removed using, for example, BOE (Buffered Oxide Etchant).
【００１８】これにより、窒化膜パターン３０’及び酸
化バッファー層パターン２０’で構成されるマスクパタ
ーンの大きさは小さくなり、第１フィールド酸化膜４０
と窒化膜パターン３０’は分離して前記半導体基板１０
の一部が露出される（１０ｂ参照）。この際、露出され
る部分１０ｂと第１フィールド酸化膜４０の面積との和
は、最終に形成されるフィールド酸化膜の面積と同一で
ある。As a result, the size of the mask pattern composed of the nitride film pattern 30 'and the oxidation buffer layer pattern 20' is reduced, and the first field oxide film 40 is formed.
And the nitride film pattern 30 'are separated from each other to form the semiconductor substrate 10
Is partially exposed (see 10b). At this time, the sum of the exposed area 10b and the area of the first field oxide film 40 is the same as the area of the finally formed field oxide film.
【００１９】図９を参照すれば、窒化膜パターン３０’
及び酸化バッファー層２０’の選択的な除去により露出
された半導体基板の所定部位１０ｂを通常の方法で熱酸
化して第２フィールド酸化膜５０を形成する。ここで、
前記第２フィールド酸化膜５０は前記第１フィールド酸
化膜４０より薄く形成し、２００Å以上、望ましくは２
５０〜３５０Åで形成する。Referring to FIG. 9, a nitride film pattern 30 '.
The predetermined portion 10b of the semiconductor substrate exposed by the selective removal of the oxidation buffer layer 20 'is thermally oxidized by a normal method to form the second field oxide film 50. here,
The second field oxide film 50 is formed to be thinner than the first field oxide film 40 and has a thickness of 200 Å or more, preferably 2 or more.
It is formed with 50 to 350Å.
【００２０】図１０を参照すれば、基板１０の上に形成
されている前記窒化膜パターン３０’及び酸化バッファ
ー層パターン２０’を取り除いて活性領域を露出させ、
第１，第２フィールド酸化膜４０、５０で構成されるフ
ィールド酸化膜を完成する。一方、本発明の他の実施例
によれば、バーズビークの発生を抑制するために用いら
れる前記酸化バッファー層２０として、オキシナイトラ
イド膜の代わりに１００Å以下の厚さで形成された酸化
膜を用いることができる。Referring to FIG. 10, the nitride layer pattern 30 'and the oxidation buffer layer pattern 20' formed on the substrate 10 are removed to expose the active region.
A field oxide film composed of the first and second field oxide films 40 and 50 is completed. Meanwhile, according to another embodiment of the present invention, as the oxidation buffer layer 20 used to suppress the generation of bird's beak, an oxide film formed to a thickness of 100 Å or less is used instead of the oxynitride film. be able to.
【００２１】かつ、前記図６又は図８に示した窒化膜パ
ターン３０’及び酸化バッファー層パターン２０’の除
去時、前記半導体基板１０の上に酸化バッファー層パタ
ーン２０’の一部を残して、図７又は図９に示した第
１、第２フィールド酸化膜４０、５０の形成時、緩衝的
な役割を保たせる。Further, when the nitride film pattern 30 'and the oxidation buffer layer pattern 20' shown in FIG. 6 or 8 are removed, a part of the oxidation buffer layer pattern 20 'is left on the semiconductor substrate 10, A buffering role is maintained during formation of the first and second field oxide films 40 and 50 shown in FIG. 7 or 9.
【００２２】[0022]
【発明の効果】上述したように、本発明による半導体装
置の素子分離方法は、活性領域が形成される基板に隣接
するフィールド酸化膜の厚さを薄く形成するように、フ
ィールド酸化膜を２段階で形成する。すなわち、本発明
により形成されたフィールド酸化膜は所定の厚さの第１
フィールド酸化膜と、第１フィールド酸化膜より薄く形
成されて活性領域に隣接する第２フィールド酸化膜とか
らなる。As described above, in the element isolation method for a semiconductor device according to the present invention, the field oxide film is formed in two steps so that the field oxide film adjacent to the substrate on which the active region is formed is thin. To form. That is, the field oxide film formed according to the present invention has a predetermined thickness of the first oxide film.
It comprises a field oxide film and a second field oxide film which is formed thinner than the first field oxide film and is adjacent to the active region.
【００２３】したがって、従来の方法に比べてフィール
ド酸化膜と活性領域との角度が大きくなると共に、これ
らの段差は小さくなり、後続く工程を容易に行うことが
できる。かつ、導電層や絶縁層を積層して形成しても、
ボイドが発生しない。したがって、素子の信頼性を向上
させ得る。本発明は前記の実施例に限るものでなく、多
くの変形が本発明の技術的な思想内で当分野の通常の知
識を持つ者により可能なのは明らかである。Therefore, as compared with the conventional method, the angle between the field oxide film and the active region becomes large, and the step between them becomes small, so that the subsequent steps can be easily performed. And even if it is formed by laminating a conductive layer and an insulating layer,
No void occurs. Therefore, the reliability of the device can be improved. The present invention is not limited to the above embodiments, and it is obvious that many modifications can be made by a person having ordinary skill in the art within the technical idea of the present invention.
【図１】従来の技術による半導体装置の素子分離方法を
説明するための断面図である。FIG. 1 is a sectional view illustrating an element isolation method of a semiconductor device according to a conventional technique.
【図２】従来の技術による半導体装置の素子分離方法を
説明するための断面図である。FIG. 2 is a sectional view illustrating an element isolation method for a semiconductor device according to a conventional technique.
【図３】従来の技術による半導体装置の素子分離方法を
説明するための断面図である。FIG. 3 is a sectional view illustrating an element isolation method of a semiconductor device according to a conventional technique.
【図４】従来の技術による半導体装置の素子分離方法を
説明するための断面図である。FIG. 4 is a cross-sectional view for explaining a conventional element isolation method for a semiconductor device.
【図５】本発明の一実施例による半導体装置の素子分離
方法を説明するための断面図である。FIG. 5 is a cross-sectional view illustrating an element isolation method for a semiconductor device according to an exemplary embodiment of the present invention.
【図６】本発明の一実施例による半導体装置の素子分離
方法を説明するための断面図である。FIG. 6 is a cross-sectional view illustrating an element isolation method for a semiconductor device according to an exemplary embodiment of the present invention.
【図７】本発明の一実施例による半導体装置の素子分離
方法を説明するための断面図である。FIG. 7 is a cross-sectional view illustrating an element isolation method for a semiconductor device according to an exemplary embodiment of the present invention.
【図８】本発明の一実施例による半導体装置の素子分離
方法を説明するための断面図である。FIG. 8 is a sectional view illustrating an element isolation method for a semiconductor device according to an exemplary embodiment of the present invention.
【図９】本発明の一実施例による半導体装置の素子分離
方法を説明するための断面図である。FIG. 9 is a cross-sectional view illustrating an element isolation method for a semiconductor device according to an exemplary embodiment of the present invention.
【図１０】本発明の一実施例による半導体装置の素子分
離方法を説明するための断面図である。FIG. 10 is a cross-sectional view illustrating an element isolation method for a semiconductor device according to an exemplary embodiment of the present invention.
１０ 半導体基板 ２０ 酸化バッファー層 ３０ 窒化膜 ４０ 第１フィールド酸化膜 ５０ 第２フィールド酸化膜 10 semiconductor substrate 20 oxidation buffer layer 30 nitride film 40 first field oxide film 50 second field oxide film
Claims (8)
導体基板上に酸化防止マスク層を形成する第１段階と、 前記マスク層をパタニングしてマスクパターンを形成す
ることにより、素子分離領域内の前記半導体基板の一部
を露出させる第２段階と、 露出された前記半導体基板を熱酸化して所定の厚さを有
する第１フィールド酸化膜を形成する第３段階と、 前記マスクパターンの側壁を部分的に食刻して前記第１
フィールド酸化膜と前記マスクパターンとの間に存在す
る素子分離領域内の前記半導体基板を露出させる第４段
階と、 前記第１フィールド酸化膜と前記マスクパターンとの間
で露出された前記半導体基板を熱酸化して前記第１フィ
ールド酸化膜より薄い第２フィールド酸化膜を形成する
第５段階と、 前記マスクパターンを取り除く第６段階とを備えること
を特徴とする半導体装置の素子分離方法。1. A first step of forming an oxidation prevention mask layer on a semiconductor substrate divided into an element isolation region and an active region, and patterning the mask layer to form a mask pattern, thereby forming a mask pattern in the element isolation region. A second step of exposing a part of the semiconductor substrate, a third step of thermally oxidizing the exposed semiconductor substrate to form a first field oxide film having a predetermined thickness, and a sidewall of the mask pattern. Partially etching the first
A fourth step of exposing the semiconductor substrate in an element isolation region existing between the field oxide film and the mask pattern; and exposing the semiconductor substrate exposed between the first field oxide film and the mask pattern. An element isolation method for a semiconductor device, comprising: a fifth step of thermally oxidizing to form a second field oxide film thinner than the first field oxide film; and a sixth step of removing the mask pattern.
窒化膜の積層により形成されることを特徴とする請求項
１に記載の半導体装置の素子分離方法。2. The element isolation method for a semiconductor device according to claim 1, wherein the mask layer is formed by stacking an oxidation buffer layer and a nitride film.
０Å厚さのオキシナイトライド膜又は１００Å以下の厚
さの酸化膜のうち、いずれか一つであることを特徴とす
る請求項２に記載の半導体装置の素子分離方法。3. The oxidation buffer layer is 100-30.
The element isolation method for a semiconductor device according to claim 2, wherein the oxynitride film has a thickness of 0Å or an oxide film having a thickness of 100Å or less.
前記窒化膜の全面を所定の厚さほど取り除くことを特徴
とする請求項２に記載の半導体装置の素子分離方法。4. The element isolation method for a semiconductor device according to claim 2, wherein in the fourth step, the entire surface of the nitride film is removed to a predetermined thickness by using isotropic etching.
Ｏ4 ）を用いることを特徴とする請求項４に記載の半導
体装置の素子分離方法。5. The isotropic etching is phosphoric acid (H 3 P
5. The element isolation method for a semiconductor device according to claim 4, wherein O 4 ) is used.
以上の厚さで形成され、前記第２フィールド酸化膜は２
００Å以上の厚さで形成されることを特徴とする請求項
１に記載の半導体装置の素子分離方法。6. The first field oxide film has a thickness of 3000 Å
The second field oxide film is formed to have the above thickness and has a thickness of 2
The element isolation method for a semiconductor device according to claim 1, wherein the element isolation method is formed with a thickness of at least 00Å.
割をするように、前記第２段階におけるマスクパターン
の形成時、前記酸化バッファー層の一部を残すことを特
徴とする請求項２に記載の半導体装置の素子分離方法。7. The method according to claim 2, wherein a part of the oxidation buffer layer is left when the mask pattern is formed in the second step so as to play a buffering role when forming a field oxide film. Element isolation method for semiconductor device.
割をするように、前記第４段階におけるマスクパターン
の食刻時、前記酸化バッファー層の一部を残すことを特
徴とする請求項７に記載の半導体装置の素子分離方法。8. The method according to claim 7, wherein a part of the oxidation buffer layer is left when the mask pattern is etched in the fourth step so as to play a buffering role when forming a field oxide film. An element isolation method for a semiconductor device as described above.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960007108A KR970067769A (en) | 1996-03-16 | 1996-03-16 | Device isolation method of semiconductor device |
| KR1996P7108 | 1996-03-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09330922A true JPH09330922A (en) | 1997-12-22 |
Family
ID=19453237
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9052934A Pending JPH09330922A (en) | 1996-03-16 | 1997-03-07 | Method for separating element of semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPH09330922A (en) |
| KR (1) | KR970067769A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6495431B2 (en) | 2000-08-03 | 2002-12-17 | Nec Corporation | Semiconductor device and method for manufacturing the same that includes a dual oxidation |
-
1996
- 1996-03-16 KR KR1019960007108A patent/KR970067769A/en active IP Right Grant
-
1997
- 1997-03-07 JP JP9052934A patent/JPH09330922A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6495431B2 (en) | 2000-08-03 | 2002-12-17 | Nec Corporation | Semiconductor device and method for manufacturing the same that includes a dual oxidation |
Also Published As
| Publication number | Publication date |
|---|---|
| KR970067769A (en) | 1997-10-13 |
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