JPS61194853A - Package for semiconductor ic - Google Patents

Package for semiconductor ic

Info

Publication number
JPS61194853A
JPS61194853A JP3540086A JP3540086A JPS61194853A JP S61194853 A JPS61194853 A JP S61194853A JP 3540086 A JP3540086 A JP 3540086A JP 3540086 A JP3540086 A JP 3540086A JP S61194853 A JPS61194853 A JP S61194853A
Authority
JP
Japan
Prior art keywords
package
semiconductor integrated
integrated circuit
shape
circuit package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3540086A
Other languages
Japanese (ja)
Inventor
フリツツ・キールヴアイン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telefunken Electronic GmbH
Original Assignee
Telefunken Electronic GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telefunken Electronic GmbH filed Critical Telefunken Electronic GmbH
Publication of JPS61194853A publication Critical patent/JPS61194853A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/544Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K13/00Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
    • H05K13/0084Containers and magazines for components, e.g. tube-like magazines
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/5442Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/54473Marks applied to semiconductor devices or parts for use after dicing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/54473Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/54486Located on package parts, e.g. encapsulation, leads, package substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Packaging Frangible Articles (AREA)
  • Drying Of Solid Materials (AREA)
  • Printing Methods (AREA)
  • Die Bonding (AREA)
  • Control And Other Processes For Unpacking Of Materials (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、基体およびリードから成る半導体集積回路用
パッケージに関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a package for a semiconductor integrated circuit comprising a base body and leads.

従来の技術 半導体集積回路用パッケージは種種の例が既に知られて
おり、例えばDIP 14ピン、QIP14ビン、L)
IC1’(ビン、Q I P 、 SOT 、 S I
 P等の呼称で周知である。
Various types of packages for conventional semiconductor integrated circuits are already known, such as DIP 14 pins, QIP 14 pins, L)
IC1' (bin, Q I P, SOT, S I
It is well known by the names such as P.

半導体集積回路の名称その他を表示するためにパッケー
ジ上面に印字されるのが普通である。
It is usually printed on the top surface of the package to display the name and other information of the semiconductor integrated circuit.

従来用いられている印字方式の場合、印字済みの完成し
たパッケージは乾燥処理を受けてからケースに納められ
る。この乾燥処理によれば、印字インキがまだ固まって
ない内に印字が損なわれるようなことは防止される。
In the case of conventional printing methods, the completed printed package is dried before being placed in a case. This drying process prevents the print from being damaged while the printing ink has not yet hardened.

しかしながら、大抵はオフセット印刷方式による従来の
この印字方式は次のような難点を有している。即ち、生
産速度にとって支障となり、過大な乾燥温度が場合によ
っては集積回路の電気的パラメータの変動をきたすこと
になる。
However, this conventional printing method, which is mostly an offset printing method, has the following drawbacks. That is, production rates are hindered and excessive drying temperatures may lead to variations in the electrical parameters of the integrated circuit.

本発明が解決しようとする課題 本発明は、半導体集積回路の印字工程を前述の難点なし
に効果的に行なえるようにすることを課題とする。
Problems to be Solved by the Present Invention An object of the present invention is to enable a printing process for semiconductor integrated circuits to be carried out effectively without the above-mentioned difficulties.

課題を解決するだめの手段 この課題を本発明は次のようにして解決した。A means to solve problems The present invention solved this problem as follows.

即ち、印字用に設けられた基体の上面が、上面の縁取り
部よりも低くなるように形成されているのである。
In other words, the upper surface of the base provided for printing is formed to be lower than the edge of the upper surface.

実施態様によれば上面の縁取り部はテープ状、直方形状
又はビード状に形成されている。
According to one embodiment, the border on the upper surface is formed in the form of a tape, a rectangular parallelepiped, or a bead.

基体上面のこのような構成によれば、印字インキの従来
の不都合な性質、つまり長いポット時間および乾燥時間
によって製作工程の妨げもしくは遅れが生ずるようなこ
とはもはやないと。
With this configuration of the top surface of the substrate, the traditional disadvantageous properties of printing inks, namely long pot times and drying times, which hinder or delay the production process, are no longer present.

いう利点が得られる。This gives you the advantage of

さらに本発明の別の利点は、所要の印字を迅速に行なえ
る点にある。即ち、長時間の乾燥時間を考慮する必要が
なく、何らかの不都合な直接又は間接のパッケージ加熱
を避けることができるからである。この場合印字インキ
のポット時間と乾燥時間との比は支障の小さいパラメー
タである。インキは、性質並びに粘ちょう度を失なうこ
となくできるだけ長くポット内に貯えることができ、か
つ印字後直ちに固定もしくは乾燥するものが望ましい。
Yet another advantage of the present invention is that the required printing can be done quickly. That is, there is no need to consider a long drying time, and any inconvenient direct or indirect heating of the package can be avoided. In this case, the ratio between the pot time and drying time of the printing ink is a parameter with little hindrance. It is desirable that the ink can be stored in the pot for as long as possible without losing its properties and consistency, and that it can be fixed or dried immediately after printing.

実施例 次に、図面に示した実施例に従い本発明を詳述する: 第1図に示す半導体集積回路用パッケージは直方体状の
基体3から成っており、この基体3はその外部寸法を冒
頭に述べたような規格のパッケージに合わせることがで
き、材料はプラスチック又はセラミックである。両横か
らリード・1が延びている。このパッケージはL)lP
16ビン、即ち16ビンを有するシュアルインラインパ
ッケージである。
Embodiment Next, the present invention will be described in detail according to the embodiment shown in the drawings: The package for a semiconductor integrated circuit shown in FIG. It can be made into a standard package as mentioned and the material can be plastic or ceramic. Lead 1 extends from both sides. This package is L)lP
It is a true in-line package with 16 bins, namely 16 bins.

上面2aには縦軸線に対して対称的に、ひいては互いに
平行に外縁部に沿って縁取り部1aが形成されており、
これら両方の縁取り部1aは上面2aよりも高くされて
いる。この場合の高さは十分の数ミリメートルの値であ
る。この数値は縁取り部1aの幅の大きさでもある。
On the upper surface 2a, a rimming portion 1a is formed along the outer edge symmetrically with respect to the longitudinal axis and parallel to each other,
Both of these edge portions 1a are higher than the upper surface 2a. The height in this case is a few tenths of a millimeter. This value is also the width of the border portion 1a.

上面2aへの印字には例えばオフセット印刷によく似た
タンポ印刷法が適する。
For example, a pad printing method similar to offset printing is suitable for printing on the upper surface 2a.

第2図には縁取り部の別の例が示されている。Another example of a border is shown in FIG.

基体3およびリード4は第1図の例と同様である。上面
2bは4個所のコーナーに形成された直方形の一縁取り
部lbによって限定されている。
The base body 3 and leads 4 are the same as in the example of FIG. The upper surface 2b is limited by rectangular parallelepiped edge portions lb formed at four corners.

縁取り部1bは上面2bに比較して十分の数ミリメート
ルの値で高くされていて、同じ数値の幅を有している。
The border 1b is raised by a few tenths of a millimeter compared to the upper surface 2b and has a width of the same value.

第4図には、鋭角的な移行縁部なしに縁取り部ICを形
成する場合の上面2aの形状が斜視図で示されている。
FIG. 4 shows in a perspective view the shape of the upper surface 2a in the case where the border IC is formed without an acute transition edge.

この場合基体3の横断面が上縁においておう面をなして
いる。
In this case, the cross-section of the base body 3 forms a cap at the upper edge.

第3図には、印字済みの半導体集積回路用パッケージが
ケース5内に納められた状態で示されている。
In FIG. 3, a printed semiconductor integrated circuit package is shown housed in a case 5. As shown in FIG.

印字されている上面2a 、zbが縁取り部よりも低く
されていることによって、ケース5の内側面6において
上面2a 、2bが不都合の接触によって摩耗を生ずる
ことはない。
Due to the fact that the printed upper surfaces 2a, zb are lower than the border, no wear of the upper surfaces 2a, 2b on the inner surface 6 of the case 5 occurs due to undesired contact.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明による1)IP l 6ビンパツケージ
の第1の実施例の斜視図、第2図はパッケージの第2の
実施例の斜視図、第3図はパッケージをケースに納めた
状態で示す端面図、第4図はパッケージの第4の実施例
の斜視図である。 l a 、 1b 、 I C−・・縁取り部、2a 
、 2b 。 2c・・・上面、3・・・基体、4・・・リード、5・
・・ケース、6・・・内側面
Fig. 1 is a perspective view of a first embodiment of the 1) IP l 6-bin package according to the present invention, Fig. 2 is a perspective view of a second embodiment of the package, and Fig. 3 is a state in which the package is housed in the case. FIG. 4 is a perspective view of a fourth embodiment of the package. l a , 1 b , I C - edging part, 2 a
, 2b. 2c...Top surface, 3...Base, 4...Lead, 5...
...Case, 6...Inner surface

Claims (1)

【特許請求の範囲】 1、基体(3)およびリード(4)から成る半導体集積
回路用パツケージであつて、表示マーク印字用の上面(
2a、2b、2c)がその縁取り部(1a、1b、1c
)よりも低く構成されていることを特徴とする、半導体
集積回路用パッケージ 2、上面の縁取り部(1a、1b、1c)が基体(3)
の縦軸線に対して対称的に上面(2a、2b、2c)に
形成されている、特許請求の範囲第1項に記載の半導体
集積回路用パッケージ 3、縁取り部(1a、1b、1c)が上面(2a、2b
2c)に中心対称形に形成されている、特許請求の範囲
第1項又は第2項に記載の半導体集積回路用パッケージ 4、縁取り部(1a、1b)が角柱状、ストライプ状、
直方形状又はビード状に形成されている、特許請求の範
囲第1項から第3項までのいずれか1項に記載の半導体
集積回路用パッケージ 5、基体(3)の上面(2c)がおう面状に形成されて
いる、特許請求の範囲第1項に記載の半導体集積回路用
パツケージ
[Claims] 1. A package for a semiconductor integrated circuit consisting of a base (3) and leads (4), the upper surface for printing display marks (
2a, 2b, 2c) are the edges (1a, 1b, 1c)
), the semiconductor integrated circuit package 2 is characterized by being configured to have a height lower than that of the base body (3), and the edge portions (1a, 1b, 1c) on the top surface are lower than the base body (3).
In the semiconductor integrated circuit package 3 according to claim 1, the edging portions (1a, 1b, 1c) are formed on the upper surface (2a, 2b, 2c) symmetrically with respect to the vertical axis of the semiconductor integrated circuit package 3. Top surface (2a, 2b
2c), the semiconductor integrated circuit package 4 according to claim 1 or 2, which is formed in a centrally symmetrical shape, the edge portions (1a, 1b) having a prismatic shape, a striped shape,
The semiconductor integrated circuit package 5 according to any one of claims 1 to 3, which is formed in a rectangular parallelepiped shape or a bead shape, and the upper surface (2c) of the base (3) is the upper surface. A package for a semiconductor integrated circuit according to claim 1, which is formed in a shape.
JP3540086A 1985-02-22 1986-02-21 Package for semiconductor ic Pending JPS61194853A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19853506172 DE3506172A1 (en) 1985-02-22 1985-02-22 COMPONENT HOUSING
DE3506172.3 1985-02-22

Publications (1)

Publication Number Publication Date
JPS61194853A true JPS61194853A (en) 1986-08-29

Family

ID=6263253

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3540086A Pending JPS61194853A (en) 1985-02-22 1986-02-21 Package for semiconductor ic

Country Status (4)

Country Link
JP (1) JPS61194853A (en)
DE (1) DE3506172A1 (en)
FR (1) FR2578098A1 (en)
GB (1) GB2171359A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8117629B2 (en) 2007-09-05 2012-02-14 Mitsubishi Electric Corporation Optical disc device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19523597A1 (en) * 1995-06-30 1997-01-02 Hans Damm Window of module housing opaque covering method for UV-EPROM

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE760031A (en) * 1969-12-11 1971-05-17 Rca Corp HOUSING FOR SEMICONDUCTOR HYBRID POWER MODULE
JPS5823457A (en) * 1981-08-03 1983-02-12 Mitsubishi Electric Corp Semiconductor device
JPS59228738A (en) * 1983-06-10 1984-12-22 Matsushita Electronics Corp Semiconductor device
JPS6018937A (en) * 1983-07-13 1985-01-31 Hitachi Ltd Electronic part

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8117629B2 (en) 2007-09-05 2012-02-14 Mitsubishi Electric Corporation Optical disc device

Also Published As

Publication number Publication date
FR2578098A1 (en) 1986-08-29
GB2171359A (en) 1986-08-28
DE3506172A1 (en) 1986-09-04
GB8604332D0 (en) 1986-03-26

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