JPS59228738A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS59228738A
JPS59228738A JP58102891A JP10289183A JPS59228738A JP S59228738 A JPS59228738 A JP S59228738A JP 58102891 A JP58102891 A JP 58102891A JP 10289183 A JP10289183 A JP 10289183A JP S59228738 A JPS59228738 A JP S59228738A
Authority
JP
Japan
Prior art keywords
mark
marking surface
sealer
marking
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58102891A
Other languages
Japanese (ja)
Inventor
Tomio Okamoto
岡本　富美夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp, Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electronics Corp
Priority to JP58102891A priority Critical patent/JPS59228738A/en
Publication of JPS59228738A publication Critical patent/JPS59228738A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54406—Marks applied to semiconductor devices or parts comprising alphanumeric information
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Duplication Or Marking (AREA)

Abstract

PURPOSE:To facilitate the read-out of lead wirings by forming a projection which is projected from the marking surface so as not to contact the marking surface with the other article on the marking surface which indicates a mark of a sealer or on the oblique surface of the periphery, thereby eliminating the removal of the mark. CONSTITUTION:A plurality of leads 4 are projected from a sealer 3 with resin of resin-molded IC, and a semiconductor element is contained in the sealer 3. The element and leads 4 are electrically connected through wirings, and a mark 5 is printed with ink on the main surface of the sealer 3. Further, a plurality of protruded projections 6 are formed on the marking surface or on the oblique surface of the periphery of the marking surface. The marking surface of the sealer 3 and the inner wall of a part feeder are prevented from being contacted directly with each other at the working time such as conveying time, testing time and packaging time after the mark 5 is printed, thereby preventing the removal of the mark.

Description

【発明の詳細な説明】 （産業上の利用分野） 本発明は、封止体にマーキングが施された半導体装置に
関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device in which a sealing body is marked.

（従来例の構成とその問題点） 一般に、半導体装置はその品種名、等級、製造ロット番
号、生産工場、製造年月日およびメーカー名等を示すマ
ークが封止体に表示されていて、例えば、第１図に示す
従来のレジンモールド型のＩＣ（集積回路）では、封止
体１の一生面がマーり２（例えば、Ｍ−１２３４）が表
示されるマーキング面となっていて、このマーキング面
にマーク２がインクにより印刷されている。(Structure of conventional example and its problems) In general, a semiconductor device has a mark indicating its type name, grade, manufacturing lot number, manufacturing factory, manufacturing date, manufacturer name, etc. on the sealed body. In the conventional resin molded IC (integrated circuit) shown in FIG. Mark 2 is printed with ink on the surface.

しかしながら、このような従来の半導体装置では、マー
ク２を印刷した後、搬送、試験および梱包等を行なう際
に、封止体１のマーキング面がノく一ノフィーダーの内
壁に接触するために、振動等に１９マーク２がこすれて
不明瞭になったシ、マーク２が脱落したりする等の欠点
があった。However, in such a conventional semiconductor device, after the mark 2 is printed, the marking surface of the sealing body 1 comes into contact with the inner wall of the feeder during transportation, testing, packaging, etc. There were drawbacks such as the 19 mark 2 being rubbed by vibrations and becoming unclear, and the mark 2 falling off.

（発明の目的） 本発明は、上記従来例の欠点に鑑みてなされたもので、
鮮明なマークを維持することができる半導体装置を提供
するものである。(Object of the invention) The present invention has been made in view of the drawbacks of the above-mentioned conventional examples, and
An object of the present invention is to provide a semiconductor device that can maintain clear marks.

（発明の構成） 上記目的を達成するために、本発明は、封ＩＥ体のマー
クが表示されるマーキング面もしくはその周囲の傾斜部
に、マーキング面よりも突出した突起を設けて、半導体
装置のマーキング面と／く一ツフィーダの内壁とが接触
しないようにしたものである。(Structure of the Invention) In order to achieve the above object, the present invention provides a protrusion protruding from the marking surface on the marking surface where the mark is displayed on the IE sealing body or on the sloped portion around the marking surface, so that the semiconductor device This prevents the marking surface from coming into contact with the inner wall of the shoe feeder.

（実施例の説明） 以下、図面により本発明の実施例を詳細に説明する。(Explanation of Examples) Embodiments of the present invention will be described in detail below with reference to the drawings.

第２図１は、レジンモールド型のＩＣＫおける本発明の
一実施例を示す図である。このＩＣは、レジンからなる
封止体３から複数のり一部４が突出していて、封止体３
内に一部示せぬ半導体素子がリード４とワイヤーを介し
て電気的に接続された状態で内蔵されている。１だ、封
止体３の一主面がマーキング面になっていて、マーク５
（例えばＭ−１２３４）がインクで印刷されている。さ
らに、マーキング面には複数の突起６が形設されていて
、この突起６は、封止体成形用の金型に適当なくぼみを
設けることにより容易に形設することができ、その位置
はマーキング面上であれば特に限定されないが・マーキ
ング面の周縁部に配置すれば、後のマーク印刷工程時に
支障がなく好都合である。FIG. 2 is a diagram showing an embodiment of the present invention in a resin mold type ICK. This IC has a plurality of glue parts 4 protruding from a sealing body 3 made of resin.
A semiconductor element, some of which is not shown, is built in and electrically connected to leads 4 via wires. 1, one main surface of the sealing body 3 is the marking surface, and the mark 5
(for example M-1234) is printed in ink. Furthermore, a plurality of protrusions 6 are formed on the marking surface, and these protrusions 6 can be easily formed by providing appropriate depressions in the mold for molding the sealing body, and their positions can be adjusted. It is not particularly limited as long as it is on the marking surface, but it is convenient if it is placed on the peripheral edge of the marking surface so that it does not interfere with the subsequent mark printing process.

また突起６の形状は、例えば円鉗台形、角錐台形、半球
あるいは半球の一部を平面としたものなど、成形時に金
型熱れが良く、成形後に外力によって欠損し難い形状が
好寸しい。The shape of the protrusion 6 is preferably a shape such as a truncated conical shape, a truncated pyramid shape, a hemisphere, or a part of a hemisphere made into a flat surface, which allows the mold to heat well during molding and is difficult to break due to external force after molding.

上記の構成において、本実施例は、マーク５を印刷した
後の搬送、試験および梱包等の作業時に、封止体３のマ
ーキング面としく一ソフィーダーの内壁とが直接接触す
ることがなく、振動等によりマーク５がこすれて不明瞭
になることがない。In the above configuration, in this embodiment, the marking surface of the sealing body 3 does not come into direct contact with the inner wall of the feeder during transportation, testing, packaging, etc. after printing the mark 5. The mark 5 will not be rubbed and become unclear due to vibration or the like.

なお、レジンモールド型のＩＣＩＣ，Ｉ５＝ける実施例
について説明したが、本発明はトランジスタ、ＬＳＩお
よび混成集積回路等、その他の半導体装置にも広く応用
することができ、封止体のマーキング面の周囲に傾斜部
を有する半導体装置の場合、その傾斜部からマーキング
面よシも上に突出するように突起を設けてもよい。また
、マーキングもインクによる印刷以外の方法によるもの
であってもよい。Although the embodiment of the resin molded ICIC has been described, the present invention can be widely applied to other semiconductor devices such as transistors, LSIs, and hybrid integrated circuits. In the case of a semiconductor device having a sloping portion around the periphery, a protrusion may be provided so as to protrude from the sloping portion above the marking surface as well. Further, the marking may also be done by a method other than printing with ink.

さらに、本発明によれば、特にソー１゛数が多く且つリ
ード間隔が小さいフラノトバノヶ〜ジ型やチップキャリ
ア型のような半導体装置において、特定のリードの近傍
に突起を設けることにより、特定のリードの読み出しを
極めて容易に行なうことができる。Further, according to the present invention, in a semiconductor device such as a flat top hinge type or a chip carrier type in which the number of saws is large and the lead spacing is small, by providing a protrusion near a specific lead, it is possible to can be read out very easily.

（発明の効果） 以上説明したように、本発明は、マーキング面もしくは
マーキング面の周囲の傾斜部に設けた突起により、マー
キング面が他の物体き接触してマークがこすれることを
防止するので、常に鮮明なマークを維持することができ
、さらに、突起を特定のリードの近傍建設けることによ
り、そのＩＪ−ドの読み出しを容易にすることができる
等の効果を有するものである。(Effects of the Invention) As explained above, the present invention prevents the marking surface from coming into contact with another object and causing the mark to be rubbed by the protrusion provided on the marking surface or the inclined portion around the marking surface. It is possible to maintain a clear mark at all times, and furthermore, by erecting a protrusion near a specific lead, it is possible to easily read out the IJ-read.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図１は、従来の半導体装置の斜視図、第２図（づ、
本発明の一実施例の斜視図である。 ３　・−・・・　封止体、　　４　・・・・・　　リー
ド、　　５　・・・・・・・・マーク、　６　・・・・
・・突起。 特許出願人　松下電子工業株式会社 〜１７４ 第１図FIG. 1 is a perspective view of a conventional semiconductor device, and FIG.
FIG. 1 is a perspective view of an embodiment of the present invention. 3... Sealing body, 4... Lead, 5... Mark, 6...
··protrusion. Patent applicant Matsushita Electronics Co., Ltd. ~174 Figure 1

Claims (1)

【特許請求の範囲】[Claims] 封止体のマークが表示されるマーキング面もしくは該マ
ーキング面の周囲の傾斜部に、前記マーキング面が他の
物体と接触し々いように該マーキング面よりも突出した
突起を設け、前記マークが脱落しないようにしたことを
特徴とする半導体装置。A protrusion protruding from the marking surface is provided on the marking surface on which the mark of the sealing body is displayed, or on the slope around the marking surface, so that the marking surface is likely to come into contact with other objects. A semiconductor device characterized by being prevented from falling off.
JP58102891A 1983-06-10 1983-06-10 Semiconductor device Pending JPS59228738A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58102891A JPS59228738A (en) 1983-06-10 1983-06-10 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58102891A JPS59228738A (en) 1983-06-10 1983-06-10 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS59228738A true JPS59228738A (en) 1984-12-22

Family

ID=14339479

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58102891A Pending JPS59228738A (en) 1983-06-10 1983-06-10 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS59228738A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6197848U (en) * 1984-11-30 1986-06-23
FR2578098A1 (en) * 1985-02-22 1986-08-29 Telefunken Electronic Gmbh CONFORMITY INTEGRATED CIRCUIT BOX FOR MARKING

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6197848U (en) * 1984-11-30 1986-06-23
FR2578098A1 (en) * 1985-02-22 1986-08-29 Telefunken Electronic Gmbh CONFORMITY INTEGRATED CIRCUIT BOX FOR MARKING

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