JPS61164257A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS61164257A
JPS61164257A JP60005421A JP542185A JPS61164257A JP S61164257 A JPS61164257 A JP S61164257A JP 60005421 A JP60005421 A JP 60005421A JP 542185 A JP542185 A JP 542185A JP S61164257 A JPS61164257 A JP S61164257A
Authority
JP
Japan
Prior art keywords
semiconductor element
battery
package
fixed
housed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60005421A
Other languages
English (en)
Inventor
Mineo Hayashi
林　峰雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP60005421A priority Critical patent/JPS61164257A/ja
Publication of JPS61164257A publication Critical patent/JPS61164257A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49593—Battery in combination with a leadframe
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01018—Argon [Ar]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明に半導体素子とデータ保持用電池全一つのパッケ
ージ内に収納した半導体装置に関する。
〔従来の技術〕
従来、この種の電池内蔵の半導体素子は第４図に示すよ
うに素子部と電池部を別々に用意し、それら全重ね合わ
せて装着することにエリ構成されていた。すなわち、半
導体素子４３を搭載せる半導体素子部パッケージ４１の
上に電池４４全設けた電池部パッケージ４２が位置して
いた。
〔発明が解決しエリとする問題点〕
上述した従来の半導体装置に半導体素子と電池という２
つの素子全型ね合わせ装着するのでその体積が倍加し、
装置の実装上も問題が多い。
また複数−の累子全同−パッケージ上に収納しようとす
る際、その占有面積が増加する。特にその増加分はある
限られた小型パッケージに半導体素子や電池を実装しよ
うとする場合重要な問題となる。
例えばある半導体記憶素子を配し、外部電源電圧が変化
した場合にメモリ内のデータ全保持するための電池を内
蔵しようとする場合など素子の占有面積や、パッケージ
の外形寸法等が限定されていればそれらの収納に困難と
なる。
〔問題点全解決するための手段〕
本発明の半導体装置は、導電板、もしくは導電膜を有す
る絶縁板の両面のうち一面に半導体素子全固着し、他の
もう一面にデータ保持用電池を固着し結線し、一つのパ
ッケージ内に収納することを特徴とする。
〔実施例〕
次に本発明について図面を参照して説明する。
第１図に本発明の一実施例の断面図である。
リードフレームのアイランド部１１の両面に半導体素子
１３をマウントし、データ保持用電池１４を固着する。
金属配線１５．１５’でそれぞれ内部リード１２．１２
’　と半導体素子１３と電池１４と全接続する。このと
き電池の一方の電極はＩＪ　＋ドフレームと金属配線を
介して半導体素子と接続されている。このような配置を
行なうことにより半導体素子載置部の占有面積全半減で
きる。しかも同一パッケージに収納することにより、パ
ッケージ自体の外形寸法を増加させずにすますことがで
きる。
上記実施例はリードフレームの場合であるが本発明は導
体膜を設けた絶縁体にも適用できる。第２図は本発明の
半導体装置の第２の実施例の断面図である。絶縁基板２
１０半導体素子および電池の載置部並びに金属細線部に
金属の導電膜２２゜２２′を設ける。半導体素子２３．
電池２４全基板の両面にそれぞれ固着し、金属細線２５
．２５’で結線する。
第３図は本発明の半導体装置の第３の実施例の断面図で
ある。第２の実施例と同様に絶縁基板３１の両面に導電
膜３２．３２’ｆｆｉ設け、半導体素子３３、電池３４
を基板の両面の導体膜にそれぞれ固着し、金属細線３５
．３５’で結線する。
〔発明の効果〕
以上説明したように本発明によれば半導体素子載置部の
面積を増加させず、しかも同一パッケージに収納するこ
とにエリ半導体装置自体の体積も増加させることなしに
半導体素子とデータ保持用の電池を実装することが可能
となる。またパッケージ自体の外形寸法を変更する必要
もない。
【図面の簡単な説明】
第１図は本発明の第１の実施例の断面図、第２図は本発
明の第２の実施例の断面図、第３図は本発明の第３の実
施例の断面図である。第４図は従来の電池付半導体装置
の外形図と断面図である。 １１・・・・・・アイランド部、１２．１２’・・・・
・・内部リード、１３・・・・・半導体素子、１４・・
・・・・電池、１５．１５’　　・・・・金属細線、２
１．３１・・・・・・絶縁基板、２２．２２’　、３２
．３２’・・・・・・導電膜、２３．３３・・・・・・
半導体素子、２４．３４・・・・・・電池、２５．２５
’　、３５．３５’・・・・・・金属細線、４１・・・
・・・半導体素子部パッケージ、４２・・・・・電池部
パッケージ、４３・・・・・・半導体素子、４４・・・
・・・電池。 第２図 第條り図

Claims (1)

    【特許請求の範囲】
  1. 導電板もしくは導電膜を有する絶縁板の両面のうち一面
    に半導体素子を固着し、他のもう一面にデータ保持用の
    電池を固着し結線し、一つのパッケージ内に収納したこ
    とを特徴とする半導体装置。
JP60005421A 1985-01-16 1985-01-16 半導体装置 Pending JPS61164257A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60005421A JPS61164257A (ja) 1985-01-16 1985-01-16 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60005421A JPS61164257A (ja) 1985-01-16 1985-01-16 半導体装置

Publications (1)

Publication Number Publication Date
JPS61164257A true JPS61164257A (ja) 1986-07-24

Family

ID=11610693

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60005421A Pending JPS61164257A (ja) 1985-01-16 1985-01-16 半導体装置

Country Status (1)

Country Link
JP (1) JPS61164257A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5196374A (en) * 1990-01-26 1993-03-23 Sgs-Thomson Microelectronics, Inc. Integrated circuit package with molded cell
US5689135A (en) * 1995-12-19 1997-11-18 Micron Technology, Inc. Multi-chip device and method of fabrication employing leads over and under processes

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5196374A (en) * 1990-01-26 1993-03-23 Sgs-Thomson Microelectronics, Inc. Integrated circuit package with molded cell
US5689135A (en) * 1995-12-19 1997-11-18 Micron Technology, Inc. Multi-chip device and method of fabrication employing leads over and under processes
US5898220A (en) * 1995-12-19 1999-04-27 Micron Technology, Inc. Multi-chip device and method of fabrication employing leads over and under processes

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