JPS6112423B2 - - Google Patents

Info

Publication number
JPS6112423B2
JPS6112423B2 JP55049770A JP4977080A JPS6112423B2 JP S6112423 B2 JPS6112423 B2 JP S6112423B2 JP 55049770 A JP55049770 A JP 55049770A JP 4977080 A JP4977080 A JP 4977080A JP S6112423 B2 JPS6112423 B2 JP S6112423B2
Authority
JP
Japan
Prior art keywords
data
central system
terminal
terminal device
mode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55049770A
Other languages
English (en)
Japanese (ja)
Other versions
JPS56146344A (en
Inventor
Tetsuo Hosoe
Kenji Shimojima
Yasuyoshi Ooyama
Hisashi Tanaka
Juichi Tasaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP4977080A priority Critical patent/JPS56146344A/ja
Publication of JPS56146344A publication Critical patent/JPS56146344A/ja
Publication of JPS6112423B2 publication Critical patent/JPS6112423B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)
  • Computer And Data Communications (AREA)
JP4977080A 1980-04-16 1980-04-16 Terminal control device Granted JPS56146344A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4977080A JPS56146344A (en) 1980-04-16 1980-04-16 Terminal control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4977080A JPS56146344A (en) 1980-04-16 1980-04-16 Terminal control device

Publications (2)

Publication Number Publication Date
JPS56146344A JPS56146344A (en) 1981-11-13
JPS6112423B2 true JPS6112423B2 (enrdf_load_stackoverflow) 1986-04-08

Family

ID=12840397

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4977080A Granted JPS56146344A (en) 1980-04-16 1980-04-16 Terminal control device

Country Status (1)

Country Link
JP (1) JPS56146344A (enrdf_load_stackoverflow)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61112264A (ja) * 1984-10-12 1986-05-30 Fujitsu Ltd スタンドアロン型集計装置
JPS61226860A (ja) * 1985-03-30 1986-10-08 Anritsu Corp カード信用取引端末装置
JPS62190544A (ja) * 1986-02-17 1987-08-20 Omron Tateisi Electronics Co プログラマブル・コントロ−ラの上位リンクユニツト

Also Published As

Publication number Publication date
JPS56146344A (en) 1981-11-13

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