JPS61117634A - メモリカ−ド実装方式 - Google Patents

メモリカ−ド実装方式

Info

Publication number
JPS61117634A
JPS61117634A JP59219806A JP21980684A JPS61117634A JP S61117634 A JPS61117634 A JP S61117634A JP 59219806 A JP59219806 A JP 59219806A JP 21980684 A JP21980684 A JP 21980684A JP S61117634 A JPS61117634 A JP S61117634A
Authority
JP
Japan
Prior art keywords
bit
card
memory
cards
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59219806A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0312742B2 (cg-RX-API-DMAC7.html
Inventor
Takashi Ihi
孝 井比
Moriyuki Takamura
守幸 高村
Shigeru Mukogasa
向笠　滋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59219806A priority Critical patent/JPS61117634A/ja
Publication of JPS61117634A publication Critical patent/JPS61117634A/ja
Publication of JPH0312742B2 publication Critical patent/JPH0312742B2/ja
Granted legal-status Critical Current

Links

JP59219806A 1984-10-19 1984-10-19 メモリカ−ド実装方式 Granted JPS61117634A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59219806A JPS61117634A (ja) 1984-10-19 1984-10-19 メモリカ−ド実装方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59219806A JPS61117634A (ja) 1984-10-19 1984-10-19 メモリカ−ド実装方式

Publications (2)

Publication Number Publication Date
JPS61117634A true JPS61117634A (ja) 1986-06-05
JPH0312742B2 JPH0312742B2 (cg-RX-API-DMAC7.html) 1991-02-20

Family

ID=16741327

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59219806A Granted JPS61117634A (ja) 1984-10-19 1984-10-19 メモリカ−ド実装方式

Country Status (1)

Country Link
JP (1) JPS61117634A (cg-RX-API-DMAC7.html)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007061304A (ja) * 2005-08-30 2007-03-15 Olympia:Kk 遊技機

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007061304A (ja) * 2005-08-30 2007-03-15 Olympia:Kk 遊技機

Also Published As

Publication number Publication date
JPH0312742B2 (cg-RX-API-DMAC7.html) 1991-02-20

Similar Documents

Publication Publication Date Title
KR100900909B1 (ko) 멀티―랭크 듀얼 인라인 메모리 모듈을 위한 버퍼 칩
US5371866A (en) Simulcast standard multichip memory addressing system
US5513135A (en) Synchronous memory packaged in single/dual in-line memory module and method of fabrication
EP1154434B1 (en) Method for fabricating a semiconductor device
EP1723526B1 (en) Dynamic command and/or address mirroring system and method for memory modules
EP0548894A2 (en) DRAM interface adapter circuit
EP0066605A4 (en) CHIP TOPOGRAPHY FOR DATA TRANSMISSION CONTROL IN INTEGRATED CIRCUIT TECHNOLOGY.
JPH08167703A (ja) 半導体装置及びその製造方法、ならびにメモリコアチップ及びメモリ周辺回路チップ
JP2539012B2 (ja) メモリカ―ド
KR950010089A (ko) 개선된 패드의 배치를 구비한 반도체 집적회로 장치
KR0179824B1 (ko) 아이씨 메모리 카드
JPS61117634A (ja) メモリカ−ド実装方式
JPH1097463A (ja) セレクトバス機能付き積層型半導体装置
TW446881B (en) Expandable time sharing bus structure
JPH10116913A (ja) 半導体集積回路装置
JP4230886B2 (ja) マルチチップパッケージ型メモリシステム
CN108256269B (zh) 一种处理器芯片及印制电路板
EP0248353A2 (en) Memory address circuit having function of exchanging selected bits of address input
JP2003282813A (ja) 半導体装置、メモリコア部チップ、メモリ周辺回路部チップおよび半導体メモリ装置
JPS6055591A (ja) メモリユニットのアクセス方法
CN100334925C (zh) 用于存储设备的数据总线连接
JP3349929B2 (ja) メモリ制御装置
JPH03126143A (ja) 中央処理装置の周辺回路
JPS61231640A (ja) メモリ制御装置
JPH01144140A (ja) メモリボードのアロケーション方式