KR950010089A - 개선된 패드의 배치를 구비한 반도체 집적회로 장치 - Google Patents
개선된 패드의 배치를 구비한 반도체 집적회로 장치 Download PDFInfo
- Publication number
- KR950010089A KR950010089A KR1019940022764A KR19940022764A KR950010089A KR 950010089 A KR950010089 A KR 950010089A KR 1019940022764 A KR1019940022764 A KR 1019940022764A KR 19940022764 A KR19940022764 A KR 19940022764A KR 950010089 A KR950010089 A KR 950010089A
- Authority
- KR
- South Korea
- Prior art keywords
- semiconductor chip
- lead
- leads
- disposed
- package
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract 34
- 238000010586 diagram Methods 0.000 description 3
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1045—Read-write mode select circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C2029/1804—Manipulation of word size
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6605—High-frequency electrical connections
- H01L2223/6611—Wire connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
- H01L2224/06136—Covering only the central area of the surface to be connected, i.e. central arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Nanotechnology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Manufacturing & Machinery (AREA)
- Dram (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
DRAM(10)은 패키지(1)와, 패키지내에 수납된 반도체칩(2)과, 각각이 패키지의 외측에서 반도체칩의 주변에 걸쳐서 배치된 복수의 리드(3, 31-18)를 포함한다.
전원 전위(Vcc)는 약간의 어드에 주어진다.
한편의 전원 리드(31)에 대응하여, 한편의 전원 패드(41)와 한편의 선택 패드(MS1)가 형성된다.
또다른편의 전원 리드(32)에 대응하여, 또다른편의 전원 패드(42)와 또다른 편의 선택 패드(MS2)가 형성된다.
이들 2개의 선택 패드의 각각은 본딩에 의해서 대응하는 전원 리드에 접속되거나 또는 접속되지 않는다.
그 결과, 4개의 단어 구성 중의 하나가 선택된다.
이들 2개의 선택 패드는 각각 대응하는 전원 리드의 근방에 배치되기 때문에 한편의 전원 리드에 대한 본딩의 횟수가 저감된다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 실시예 1에 의한 DARM이 구성을 표시하는 도면이다.
제2도는 "x1 구성", "x4 구성", 및 "x9 구성"을 가지는 DRAM의 핀배치를 표시하는 도면이다.
제3도는 "16 구성"을 가지는 DRAM의 핀배치를 표시하는 도면이다.
Claims (9)
- 패키지(1)와; 상기 패키지내에 수납되어 복수의 제1의 소정 동작 중 어느 것을 선택적으로 수행하는 반도체칩(2)과; 각각이 상기 패키지의 외측에서 상기 반도체칩의 주변에 걸쳐서 배치되며, 전원 전위(Vcc)를 받기 위한 제1의 전원 리드(31)와 전원 전위(Vcc)를 받기 위한 상기 제1의 전원 리드로부터 떨어진 곳에 위치하는 제2의 전원 리드(32)를 포함하는 복수의 리드(3)와; 상기 반도체칩상에 배치되어 제1의 전원 리드에 접속된 제1의 전원 패드(41)와; 상기 반도체칩상에 배치되어 제2의 전원 리드에 접속된 제1의 전원 패드(42)와; 상기 반도체칩상에 상기 제1의 전원 리드의 근방에 배치되어 상기 제1의 전원 리드에 접속되는 상태나 그로부터 분리되는 상태를 가지는 제1의 선택 패드(MS1)와; 상기 반도체칩상에서 상기 제2의 전원 리드의 근방에 배치되어 상기제2의 전원 리드에 접속되는 상태나 그로부터 분리되는 상태를 가지는 제2의 선택 패드(MS2)와; 상기 제1 및제2의 접속 패드의 접속/분리 상태에 응답하여 상기 복수의 제1의 소정 동작중의 어느 것을 특징으로 하는 반도체 집적 회로장치.
- 제1항에 있어서, 상기 반도체칩은 복수의 제2의 소정 동작 중의 어느 것을 선택적으로 더욱 수행하고, 상기 복수의 리드는 전원 전위(Vcc)를 받기 위한 제3의 전원 리드(33)와 전원 전위(Vss)를 받기 위한 상기 제3의 전원 리드로부터 떨어진 곳에 위치하는 제4의 전원 리드(38)를 부가하여 구비하는 것을 특징으로 하고, 상기 반도체칩상에 배치되어 상기 제3의 전원 리드에 접속된 제3의 전원 패드(43)와, 상기 반도체칩상에 배치되어 있는 상기 제4의 전원 리드에 접속된 제4의 전원 패드(48)와, 상기 반도체칩상에서 상기 제3의 전원 리드의 근방에 배치되어 상기 제3의 전원 리드에 접속된 상태나 그로부터 분리된 상태를 가지는 제3의 선택 패드(MS3)와, 상기 반도체칩상에서 상기 제4의 전원 리드의 근방에 배치되어 상기 제4의 전원 리드에 접속된 상태나 그로부터 분리된 상태를 가지는 제4의 선택 패드(MS4)와, 상기 제1의 선택 수단에 의해서 선택된 동작과 상기 제3 및 제4의 선택 패드의 접속/분리 상태에 응답하여 상기 복수의 제2의 소정 동작 중의 어느 것을 선택하는 제2의 선택 수단(7)을 부가하여 구비하는것을 특징으로 하는 반도체 집적 회로장치.
- 제1항에 있어서, 상기 복수의 리드의 각각의 일단부는 상기 반도체칩상에 걸쳐서 배치되는 구비하는 것을 특징으로 하는 반도체 집적 회로장치.
- 제1항에 있어서, 상기 반도체칩은 데이터의 판독/기록이 가능한 반도체 기억장치이고, 동시에 판독/기록된 데이터의 수는 상기 제1의 선택 수단에 의해서 선택된 동작에서 결정되는 것을 특징으로 하는 반도체 집적 회로장치.
- 패키지(1)와; 상기 패키지내에 수납되어 복수의 제1의 소정 동작 중의 어느 것과 복수의 제2의 소정 동작중의 어느 것을 선택적으로 수행하는 반도체칩(2)과; 각각이 상기 패키지의 외측에서 상기 반도체칩의 주변에 걸쳐 배치된 복수의 리드(3)와; 각각이 상기 반도체칩상에서 상기 복수의 리드중의 어느 것에 대응하여 배치되어 대응하는 리드에 접속된 상태나 그로부터 분리된 상태를 가지는 복수의 제1의 선택 패드(MS1, MS2)와; 상기 복수의 제1의 선택 패드에 의해서 선택된 동작에 응답하여 각각이 복수의 제1의 소정 동작 중의 어느 것을 선택하는 제1의 선택 수단과; 상기 반도체칩상에서 상기 복수의 리드중의 어느 것에 대응하여 배치되어 대응하는 리드에 접속된 상태나 그로부터 분리된 상태를 가지는 복수의 제2의 선택 패드(MS3, MS4)와; 상기 제1의 선택 수단에 의해서 선택된 동작과 상기 복수의 제2의 선택 패드의 접속/분리 상태에 응답하여 상기 복수의 제2의 소정 동작중의 어느 것을 선택하는 제2의 선택 수단(7)을 구비하는 것을 특징으로 하는 반도체 집적 회로장치.
- 제5항에 있어서, 상기 북수의 리드의 각각의 일단부는 상기 반도체칩상에 걸쳐서 배치되는 것을 특징으로 하는 반도체 집적 회로장치.
- 제5항에 있어서, 상기 반도체칩은 데이터의 판독/기록이 가능한 반도체 기억장치이고, 동시에 판독/기록된 데이터의 수는 상기 제1의 선택 수단에 의해서 선택된 동작에 결정되는 것을 특징으로 하는 반도체 집적 회로장치.
- 패키지(1)와; 상기 패키지내에 수납된 반도체칩(2)과; 상기 패키지의 2개의 대향하는 측벽에 따라 배치되어 각각이 상기 패키지의 외측에서부터 상기 반도체칩의 주변에 걸쳐 배치된 복수의 리드(3)와; 상기 반도체칩상에서 상기 2개의 대향하는 측벽과 평행하게 상기 복수의 리드에 대응하여 배치되고, 서로 대향하는 2개의 리드에 대응하는 2개의 패드중의 한편은 2개의 리드중의 한편에 접속하고, 2개의 피드의 다른편은 2개의 리드중의 다른편에 접속하고, 2개의 패드는 서로 인접하여 배치되는 복수의 패드(8)를 포함하는 것을 특징으로 하는 반도체 집적 회로장치.
- 제8항에 있어서, 상기 복수의 리드의 각각의 일단부는 상기 반도체칩상에 걸쳐서 배치되어 있는 것을 특징으로 하는 반도체 집적 회로장치.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22448193 | 1993-09-09 | ||
JP93-224481 | 1993-09-09 | ||
JP94-162087 | 1994-07-14 | ||
JP6162087A JPH07130788A (ja) | 1993-09-09 | 1994-07-14 | 半導体集積回路装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR950010089A true KR950010089A (ko) | 1995-04-26 |
KR0150489B1 KR0150489B1 (ko) | 1998-12-01 |
Family
ID=26487998
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019940022764A KR0150489B1 (ko) | 1993-09-09 | 1994-09-09 | 개선된 패드의 배치를 구비한 반도체 집적회로 장치 |
Country Status (3)
Country | Link |
---|---|
US (1) | US5587607A (ko) |
JP (1) | JPH07130788A (ko) |
KR (1) | KR0150489B1 (ko) |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5661082A (en) * | 1995-01-20 | 1997-08-26 | Motorola, Inc. | Process for forming a semiconductor device having a bond pad |
JP2679669B2 (ja) * | 1995-02-28 | 1997-11-19 | 日本電気株式会社 | 半導体装置 |
US6388314B1 (en) | 1995-08-17 | 2002-05-14 | Micron Technology, Inc. | Single deposition layer metal dynamic random access memory |
JP2795315B2 (ja) * | 1996-05-16 | 1998-09-10 | 日本電気株式会社 | 半導体装置 |
US5744870A (en) * | 1996-06-07 | 1998-04-28 | Micron Technology, Inc. | Memory device with multiple input/output connections |
JP2828056B2 (ja) * | 1996-08-20 | 1998-11-25 | 日本電気株式会社 | 半導体装置及びその製造方法 |
KR100499295B1 (ko) * | 1996-12-03 | 2006-04-21 | 텍사스 인스트루먼츠 인코포레이티드 | 메모리구성회로및방법 |
US5838072A (en) * | 1997-02-24 | 1998-11-17 | Mosel Vitalic Corporation | Intrachip power distribution package and method for semiconductors having a supply node electrically interconnected with one or more intermediate nodes |
US5903491A (en) | 1997-06-09 | 1999-05-11 | Micron Technology, Inc. | Single deposition layer metal dynamic random access memory |
US6008532A (en) * | 1997-10-23 | 1999-12-28 | Lsi Logic Corporation | Integrated circuit package having bond fingers with alternate bonding areas |
US6169331B1 (en) | 1998-08-28 | 2001-01-02 | Micron Technology, Inc. | Apparatus for electrically coupling bond pads of a microelectronic device |
JP2000100814A (ja) * | 1998-09-18 | 2000-04-07 | Hitachi Ltd | 半導体装置 |
US6356958B1 (en) | 1999-02-08 | 2002-03-12 | Mou-Shiung Lin | Integrated circuit module has common function known good integrated circuit die with multiple selectable functions |
US7247932B1 (en) * | 2000-05-19 | 2007-07-24 | Megica Corporation | Chip package with capacitor |
US6525560B1 (en) | 2001-12-12 | 2003-02-25 | Xilinx, Inc. | Method and structure for shipping a die as multiple products |
DE10232721A1 (de) | 2002-07-16 | 2004-02-12 | Siemens Ag | Druckgeber mit Drucksensor in mikromechanischer Bauweise |
JP4185721B2 (ja) * | 2002-07-17 | 2008-11-26 | アルプス電気株式会社 | 照明装置及び液晶表示装置 |
US7737553B2 (en) * | 2004-10-06 | 2010-06-15 | Panasonic Corporation | Semiconductor device |
JP5103245B2 (ja) * | 2008-03-31 | 2012-12-19 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP6580880B2 (ja) * | 2015-06-23 | 2019-09-25 | ローム株式会社 | 半導体集積回路 |
US10693468B2 (en) * | 2017-06-28 | 2020-06-23 | Texas Instruments Incorporated | Integrated circuit and process for family of digital logic functions |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4956811A (en) * | 1987-09-16 | 1990-09-11 | Hitachi, Ltd. | Semiconductor memory |
JP2762292B2 (ja) * | 1989-03-20 | 1998-06-04 | 株式会社日立製作所 | 半導体記憶装置 |
US5208782A (en) * | 1989-02-09 | 1993-05-04 | Hitachi, Ltd. | Semiconductor integrated circuit device having a plurality of memory blocks and a lead on chip (LOC) arrangement |
EP0454447A3 (en) * | 1990-04-26 | 1993-12-08 | Hitachi Ltd | Semiconductor device assembly |
JPH04348045A (ja) * | 1990-05-20 | 1992-12-03 | Hitachi Ltd | 半導体装置及びその製造方法 |
KR100276781B1 (ko) * | 1992-02-03 | 2001-01-15 | 비센트 비. 인그라시아 | 리드-온-칩 반도체장치 및 그 제조방법 |
-
1994
- 1994-07-14 JP JP6162087A patent/JPH07130788A/ja active Pending
- 1994-08-18 US US08/292,301 patent/US5587607A/en not_active Expired - Fee Related
- 1994-09-09 KR KR1019940022764A patent/KR0150489B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
US5587607A (en) | 1996-12-24 |
KR0150489B1 (ko) | 1998-12-01 |
JPH07130788A (ja) | 1995-05-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR950010089A (ko) | 개선된 패드의 배치를 구비한 반도체 집적회로 장치 | |
KR950002012A (ko) | 반도체 기억장치 | |
KR930020654A (ko) | 반도체 메모리 모듈 | |
KR960026780A (ko) | 단일/이중 인-라인 메모리 모듈에 패키징되는 동기식 메모리 및 제조 방법 | |
KR20040065176A (ko) | 반도체장치 | |
US6353549B1 (en) | Architecture and package orientation for high speed memory devices | |
JPS6033311B2 (ja) | 垂直半導体集積回路チツプ・パツケ−ジ | |
US6907486B1 (en) | Disk module of solid state | |
US5345412A (en) | Memory IC and memory device capable of expansion of storage capacity | |
JP2003051545A (ja) | 半導体メモリチップとそれを用いた半導体メモリ装置 | |
EP0533589B1 (en) | A semiconductor device | |
CN104681094A (zh) | 半导体存储器装置 | |
JPH1187640A (ja) | 半導体装置および電子装置 | |
KR910008836A (ko) | 반도체기억장치 | |
US5998869A (en) | High storage capacity, wide data input/output channel, static random access memory device | |
JP4754201B2 (ja) | 半導体装置 | |
CN113454719B (zh) | 命令和地址在存储器装置中的集中化放置 | |
KR100735527B1 (ko) | 2개의 패드 행을 포함하는 반도체 메모리 장치 | |
CN101008990A (zh) | 半导体存储卡 | |
EP1139208A1 (en) | Disk module of solid state | |
CN101577269B (zh) | 多芯片模块及选择衬垫共用方法 | |
JPS60240140A (ja) | チップへの信号供給方法 | |
KR0175022B1 (ko) | 반도체 기억장치의 데이터 입출력 모드 변환장치 | |
KR950020310A (ko) | 종합회로카드 | |
KR100228148B1 (ko) | 임피던스 정합 커패시터를 갖는 메모리 모듈 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20020610 Year of fee payment: 5 |
|
LAPS | Lapse due to unpaid annual fee |