JPS61113247A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

Info

Publication number
JPS61113247A
JPS61113247A JP59235855A JP23585584A JPS61113247A JP S61113247 A JPS61113247 A JP S61113247A JP 59235855 A JP59235855 A JP 59235855A JP 23585584 A JP23585584 A JP 23585584A JP S61113247 A JPS61113247 A JP S61113247A
Authority
JP
Japan
Prior art keywords
semiconductor element
solder
solder member
collet
backside
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59235855A
Other languages
English (en)
Inventor
Shigeo Okada
成夫 岡田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Original Assignee
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Semiconductor Manufacturing Co Ltd, Kansai Nippon Electric Co Ltd filed Critical Renesas Semiconductor Manufacturing Co Ltd
Priority to JP59235855A priority Critical patent/JPS61113247A/ja
Publication of JPS61113247A publication Critical patent/JPS61113247A/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L24/741—Apparatus for manufacturing means for bonding, e.g. connectors
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1182—Applying permanent coating, e.g. in-situ coating
    • H01L2224/11822—Applying permanent coating, e.g. in-situ coating by dipping, e.g. in a solder bath
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L2224/741—Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L2224/743—Apparatus for manufacturing layer connectors
    • H—ELECTRICITY
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 ［産業上の利用分野コ 本発明は半導体装置の製造方法に関し、特に半導体素子
のリードフレーム、ステムなどの基板へのマウント方法
の改良に関するものである。
［従来技術］ 一般にこの種半導体装置は例えば特公昭５７−５０５５
号公報に開示されているように、複数のリードを絶縁的
に植立されたステムに半導体素子を半田部材を用いて固
定すると共に、半導体素子の電極とリードとを金属細線
にて接続し、かつステムに金属キャップを、半導体素子
が気密的に被覆されるようにプロジェクション溶接して
構成されている。
ところで、半導体素子のステムへのマウントは例えば不
活性雰囲気において加熱されたステムの上面に半田片を
載置すると共に、この半田片上にフレットにて真空吸着
された半導体素子を位置させ、半田片に押しつけるよう
にして左右にスクラブ操作することによって行われてい
るのであるが、このスクラブ操作によって半田部材がス
テム上において必要以上に拡がる傾向にある。
［発明が解決しようとする問題点コ しかし乍ら、半導体素子をステムの極めて限られた狭い
部分にマウントしなければならない場合にはマウント時
に充分にスクラブ操作ができないために、半導体素子と
半田部材との充分ななじみ性が確保できず、半導体素子
のステムに対する固定性が損なわれ、パワーサイクル試
験などの過酷試験によって早期に不良となる。
一方、特公昭５７−２４９２８号公報に示すように、半
導体素子を樹脂材にてモールド被覆する半導体装置にあ
っては半導体素子のスクラブ操作時に必要以上に拡がる
半田部材によって耐湿性が損なわれ易いという問題があ
る。
それ故に、本発明の目的は簡単な構成によって半導体素
子の基板へのマウント時にスクラブ操作を行わなくても
確実にマウントできる半導体装置の製造方法を提供する
ことにある。
口問題を解決するための手段］ 従って、本発明は上述の目的を達成するために、半導体
素子の裏面に溶融状態の半田部材を被着し、この半導体
素子をステージ上においてスクラブ操作することにより
半導体素子に半田部材をなしませ、然る後、この半導体
素子を基板にマウントするものである。
［作用コ この発明によれば、半導体素子の基板へのマウントに先
立って、半導体素子の裏面に半田部材を被着させた状態
で加熱状態のステージ上でスクラブ操作させるので、半
田部材の半導体素子の裏面への充分ななじみ性を確保で
きる。従って、基板へのマウント時にスクラブ操作する
ことなく、単に載置するだけで半導体素子を基板に確実
にマウントできる。
［実施例コ 次に本発明の一実施例について第１図〜第４図を参照し
て説明する。
まず、第１図に示すように、半導体素子１をコレット２
にて真空吸着し、この状態でコレクト２を下降させて半
導体素子１の゛裏面を溶融半田槽３に接触させる。そし
て、引上げることによって、半導体素子１の裏面には半
田部材４が被着される。
次に、第２図に示すように、コレット２を加熱状態のス
テージ５上に移動させる。そして、コレ・ソト２を下降
させ、半田部材４をステージ５に押しつけ乍ら左右方向
にスクラブ操作する。これによって半導体素子１の裏面
には半田部材４が充分になじむ。次に、第３図に示すよ
うに、コレット２をステム（基板）６上に移動させる。
尚、このステム６には予め一定量の半田部材４が供給さ
れている。そして、コレット２を下降させ、半導体素子
１を半田部材４上に載置し若干押しつける。その後、コ
レット２のみを上昇させる。これによって、半導体素子
１はステム６にマウントされる。
次に、第４図に示すように、半導体素子１の電極とリー
ド７とを金属細線８にて接続し、半導体素子１を含む主
要部分巻樹脂材９にてモールド被覆することにより半導
体装置が得られる。
尚、上記実施例において、基板はステムの他、リードフ
レームなども包含する。又、基板６番こ半導体素子１を
マウントするに先立って、基板６に半田部材４を予め供
給しておくことが望まい）が、省略することもできる。
さらに半導体素子１の外装は金属キャップなどによって
行うこともできる。
［発明の効果コ 以上のように本発明によれば、半導体素子の基板へのマ
ウントに先立って、半導体素子の裏面４こ半田部材を被
着し、この状態でステージ上にスクラブ操作することに
よって半田部材の半導体素子へのなじみ性の確実化が図
られるために、基板（こ単に載置するだけで良好なマウ
ント状態を確保することができる。このために、基板上
での半田部材の不所望な拡がりを防止でき、これに伴う
トラブルも抑制できる。
【図面の簡単な説明】
図は本発明方法の説明図であって、第１図は半導体素子
の裏面への半田部材の被着状態を示す側断面図、第２図
はステージ上でのスクラブ状態を示す側断面図、第３図
は半導体素子の基板へのマウント前の状態を示す側断面
図、第４図は完成状態を示す側断面図である。 図中、１は半導体素子、４は半田部材、５はステージ、
６は基板である。 第１図 第２図

Claims (3)

    【特許請求の範囲】
  1. （１）半導体素子の裏面に溶融状態の半田部材を被着す
    る工程と、半導体素子をステージ上において半田部材が
    ステージ側となるようにしてスクラブする工程と、この
    半導体素子を基板にマウントする工程とを含むことを特
    徴とする半導体装置の製造方法。
  2. （２）半導体素子の基板へのマウント工程において基板
    に予め半田部材を供給しておくことを特徴とする特許請
    求の範囲第１項に記載の半導体装置の製造方法。
  3. （３）基板がステム又はリードフレームであることを特
    徴とする特許請求の範囲第１項ないし第２項に記載の半
    導体装置の製造方法。
JP59235855A 1984-11-07 1984-11-07 半導体装置の製造方法 Pending JPS61113247A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59235855A JPS61113247A (ja) 1984-11-07 1984-11-07 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59235855A JPS61113247A (ja) 1984-11-07 1984-11-07 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
JPS61113247A true JPS61113247A (ja) 1986-05-31

Family

ID=16992247

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59235855A Pending JPS61113247A (ja) 1984-11-07 1984-11-07 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPS61113247A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0606522A3 (en) * 1993-01-12 1996-04-10 Mitsubishi Electric Corp Semiconductor device and method of manufacturing and mounting semiconductor devices.

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0606522A3 (en) * 1993-01-12 1996-04-10 Mitsubishi Electric Corp Semiconductor device and method of manufacturing and mounting semiconductor devices.
EP0817254A2 (en) * 1993-01-12 1998-01-07 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and methods for producing and mounting the semiconductor device
EP0817254A3 (en) * 1993-01-12 1998-01-21 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and methods for producing and mounting the semiconductor device
US5770468A (en) * 1993-01-12 1998-06-23 Mitsubishi Denki Kabushiki Kaisha Process for mounting a semiconductor chip to a chip carrier by exposing a solder layer to a reducing atmosphere

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