JPS61102739A - パタ−ン形成方法 - Google Patents

パタ−ン形成方法

Info

Publication number
JPS61102739A
JPS61102739A JP59226361A JP22636184A JPS61102739A JP S61102739 A JPS61102739 A JP S61102739A JP 59226361 A JP59226361 A JP 59226361A JP 22636184 A JP22636184 A JP 22636184A JP S61102739 A JPS61102739 A JP S61102739A
Authority
JP
Japan
Prior art keywords
pattern
exposed
resist
exposure
opening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59226361A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0471331B2 (enrdf_load_stackoverflow
Inventor
Hiroshi Yamashita
山下　普
Yoshihiro Todokoro
義博 戸所
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP59226361A priority Critical patent/JPS61102739A/ja
Publication of JPS61102739A publication Critical patent/JPS61102739A/ja
Publication of JPH0471331B2 publication Critical patent/JPH0471331B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/7045—Hybrid exposures, i.e. multiple exposures of the same area using different types of exposure apparatus, e.g. combining projection, proximity, direct write, interferometric, UV, x-ray or particle beam
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
JP59226361A 1984-10-26 1984-10-26 パタ−ン形成方法 Granted JPS61102739A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59226361A JPS61102739A (ja) 1984-10-26 1984-10-26 パタ−ン形成方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59226361A JPS61102739A (ja) 1984-10-26 1984-10-26 パタ−ン形成方法

Publications (2)

Publication Number Publication Date
JPS61102739A true JPS61102739A (ja) 1986-05-21
JPH0471331B2 JPH0471331B2 (enrdf_load_stackoverflow) 1992-11-13

Family

ID=16843942

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59226361A Granted JPS61102739A (ja) 1984-10-26 1984-10-26 パタ−ン形成方法

Country Status (1)

Country Link
JP (1) JPS61102739A (enrdf_load_stackoverflow)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6373518A (ja) * 1986-09-16 1988-04-04 Matsushita Electronics Corp パタ−ン形成方法
JPH01191416A (ja) * 1988-01-27 1989-08-01 Nec Corp パターン形成方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58145125A (ja) * 1982-02-24 1983-08-29 Nec Corp レジスト・マスクの形成方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58145125A (ja) * 1982-02-24 1983-08-29 Nec Corp レジスト・マスクの形成方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6373518A (ja) * 1986-09-16 1988-04-04 Matsushita Electronics Corp パタ−ン形成方法
JPH01191416A (ja) * 1988-01-27 1989-08-01 Nec Corp パターン形成方法

Also Published As

Publication number Publication date
JPH0471331B2 (enrdf_load_stackoverflow) 1992-11-13

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