JPS6095927A - 半導体装置 - Google Patents
半導体装置Info
- Publication number
- JPS6095927A JPS6095927A JP58203984A JP20398483A JPS6095927A JP S6095927 A JPS6095927 A JP S6095927A JP 58203984 A JP58203984 A JP 58203984A JP 20398483 A JP20398483 A JP 20398483A JP S6095927 A JPS6095927 A JP S6095927A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- semiconductor chip
- chip
- grooves
- mesa
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 45
- 229910000679 solder Inorganic materials 0.000 claims abstract description 17
- 238000005219 brazing Methods 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 3
- 230000001681 protective effect Effects 0.000 abstract description 2
- 239000011521 glass Substances 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000009545 invasion Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000011253 protective coating Substances 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
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- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
め要約のデータは記録されません。
Description
【発明の詳細な説明】
(発明の技術分野)
本発明はメサ型半導体装置の製造方法に関するものであ
る。
る。
(従来技術)
従来、樹脂封止型半導体装置は、一般に次のように製造
されていた。
されていた。
即ち、先ず第1図(Al 、 (B) 、 (Qに示す
如く、金属板を所定の形状に加工したリードフレーム1
のアイランド部1′に半田3を載せ、その上方から半導
体チップ2をあて、半導体チップ2に適当表荷重を与え
ることによって半導体チップ2を半田3にてアイランド
部1′に固定させ、半導体チップ2上の電極とリードフ
レーム1のリードとの間に全組wM4等によシ必畳な電
気接続を行なう。しかる後に第3図に示す如く樹脂8で
半導体チップ2および金細線4等を封止し、リードフレ
ーム固定板9しかしながら、このような従来の半導体装
置では、半導体チップ21&:、リードフレーム1に半
田3を用い固定させる際、第1図(B) 、 (C)に
示すようにある程度の荷重をチップ2に加える為、半導
体チップ2の断面5−への半田塵シ上シは避けられない
ことであった。半導体チップ2のメサ溝部はガラス6に
よシ保護がなされているが、半田3の量のバラツキ及び
半導体チップ2のセンターズレ並びに半導体チップ2の
取付は時の傾きによシメサ溝部のガラス保護膜6を通シ
越し半導体“チップ2のシリコン基板露出断面5にまで
半田3が付着し、半導体素子の特性歩留及び信頼性を著
しく低下させる原因になっている。
如く、金属板を所定の形状に加工したリードフレーム1
のアイランド部1′に半田3を載せ、その上方から半導
体チップ2をあて、半導体チップ2に適当表荷重を与え
ることによって半導体チップ2を半田3にてアイランド
部1′に固定させ、半導体チップ2上の電極とリードフ
レーム1のリードとの間に全組wM4等によシ必畳な電
気接続を行なう。しかる後に第3図に示す如く樹脂8で
半導体チップ2および金細線4等を封止し、リードフレ
ーム固定板9しかしながら、このような従来の半導体装
置では、半導体チップ21&:、リードフレーム1に半
田3を用い固定させる際、第1図(B) 、 (C)に
示すようにある程度の荷重をチップ2に加える為、半導
体チップ2の断面5−への半田塵シ上シは避けられない
ことであった。半導体チップ2のメサ溝部はガラス6に
よシ保護がなされているが、半田3の量のバラツキ及び
半導体チップ2のセンターズレ並びに半導体チップ2の
取付は時の傾きによシメサ溝部のガラス保護膜6を通シ
越し半導体“チップ2のシリコン基板露出断面5にまで
半田3が付着し、半導体素子の特性歩留及び信頼性を著
しく低下させる原因になっている。
(本発明の目的)
従って、本発明の目的は、前記半導体チップのメサ溝へ
の半田盛上シを減少させ、特性歩留及び信頼性を大幅に
向上した半導体装置を提供することにある。
の半田盛上シを減少させ、特性歩留及び信頼性を大幅に
向上した半導体装置を提供することにある。
(発明の構成)
本発明によれば、リードフレームの半導体素子載置部に
は半導体素子の接触する部分の外周に溝を有し、この溝
内に囲まれた部分の#1#X全体に半導体素子を半田も
しくはロー材で取シ付けた半導体装置を得る。
は半導体素子の接触する部分の外周に溝を有し、この溝
内に囲まれた部分の#1#X全体に半導体素子を半田も
しくはロー材で取シ付けた半導体装置を得る。
(発明の実施例)
以下、本発明の一実施例について図面を用いて説明する
。第2図四、 (Bl 、 (Qおよび第3図、第4図
は本発明の一実施例の製造工程を示したもので、まず、
リードフレーム11が作られる。リードフレーム11は
金属板を打ち抜いて外部へ電極′fts出するリードと
半導体チップ12を取9付けるアイランド11′との組
を複数組固定板19で一体化するように形成される。ア
イランド11′では半導2図の)に示すように半田13
t−II状溝17の内側に載せその上に表裏両面がメサ
カットされメサカット部にガラスの保護被膜16のなさ
れた半導体チップ12を載せる。次に、第2図(CJに
示すように、半導体チップ12の上方から適当な荷重を
与えることによって、半導体チップ12を環状溝17の
内側に取シ付ける。この時、半田13は半導体チップ1
2の下から外側に逃けるが、溝17内に留る。このため
、半田17が半導体チップ12の側面にはい上ることは
ない。その後、第2図体)に示すように、半導体チップ
12表面の電極とリード間が金細線14等によって配線
がなされるの更に、第3図に示すよりに、半導体チップ
12と金細線14とを少くとも封止するように樹W!I
8がモールド等で暴君せられ、第4図に示すように、リ
ードフレーム11の固定板19が切断除去されて個々の
半導体装置10に分離される。
。第2図四、 (Bl 、 (Qおよび第3図、第4図
は本発明の一実施例の製造工程を示したもので、まず、
リードフレーム11が作られる。リードフレーム11は
金属板を打ち抜いて外部へ電極′fts出するリードと
半導体チップ12を取9付けるアイランド11′との組
を複数組固定板19で一体化するように形成される。ア
イランド11′では半導2図の)に示すように半田13
t−II状溝17の内側に載せその上に表裏両面がメサ
カットされメサカット部にガラスの保護被膜16のなさ
れた半導体チップ12を載せる。次に、第2図(CJに
示すように、半導体チップ12の上方から適当な荷重を
与えることによって、半導体チップ12を環状溝17の
内側に取シ付ける。この時、半田13は半導体チップ1
2の下から外側に逃けるが、溝17内に留る。このため
、半田17が半導体チップ12の側面にはい上ることは
ない。その後、第2図体)に示すように、半導体チップ
12表面の電極とリード間が金細線14等によって配線
がなされるの更に、第3図に示すよりに、半導体チップ
12と金細線14とを少くとも封止するように樹W!I
8がモールド等で暴君せられ、第4図に示すように、リ
ードフレーム11の固定板19が切断除去されて個々の
半導体装置10に分離される。
このように、本実施例によれば、半導体チップ12を取
シ付ける半田13は溝17内に逃げるので、半導体チッ
プ12の側面には一上ることはなく素子特性の劣化がな
く信頼性の高い半導体装置を得ることができる。
シ付ける半田13は溝17内に逃げるので、半導体チッ
プ12の側面には一上ることはなく素子特性の劣化がな
く信頼性の高い半導体装置を得ることができる。
第1口内は、従来のメサ型半導体装置の平面図、同図の
)および(C)は半導体チップを取シ付ける工程を示す
断面図である0第2図囚は、本発明の一実施例による半
導体装置の平面図、同図■)および(qは半導体チップ
を取シ付ける工程を示す断面図である。第3図社樹脂封
止工程後を示す平面図、第4口拡固定板切断後を示す平
面図である。 1.11・・・・・・リードフレーム、”1’、11’
・・・・・・アイランド、2,12・・・・・・半導体
チップ、3.13・・・・・・半田、4.14・・・・
・・金細線、5・・・・・・半導体チップ側面、ら−1
g・・・・・・ガラス侵S魔、7・・・・・・溝、8・
・・・・・樹脂、9・・・・・・フレーム固定板、10
・・・・・・半導体装置O1、〜−−二′ 乃を閃 (A) 第2国 v、lγ
)および(C)は半導体チップを取シ付ける工程を示す
断面図である0第2図囚は、本発明の一実施例による半
導体装置の平面図、同図■)および(qは半導体チップ
を取シ付ける工程を示す断面図である。第3図社樹脂封
止工程後を示す平面図、第4口拡固定板切断後を示す平
面図である。 1.11・・・・・・リードフレーム、”1’、11’
・・・・・・アイランド、2,12・・・・・・半導体
チップ、3.13・・・・・・半田、4.14・・・・
・・金細線、5・・・・・・半導体チップ側面、ら−1
g・・・・・・ガラス侵S魔、7・・・・・・溝、8・
・・・・・樹脂、9・・・・・・フレーム固定板、10
・・・・・・半導体装置O1、〜−−二′ 乃を閃 (A) 第2国 v、lγ
Claims (1)
- 半導体素子載置部には半導体素子の接触する部分の外周
に溝を有し、この溝内に囲まれた部分に半導体素子を半
田もしくはロー材で取シ付けたことを特徴とする半導体
装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58203984A JPS6095927A (ja) | 1983-10-31 | 1983-10-31 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58203984A JPS6095927A (ja) | 1983-10-31 | 1983-10-31 | 半導体装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6095927A true JPS6095927A (ja) | 1985-05-29 |
Family
ID=16482861
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58203984A Pending JPS6095927A (ja) | 1983-10-31 | 1983-10-31 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6095927A (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2019145743A (ja) * | 2018-02-23 | 2019-08-29 | 日立オートモティブシステムズ株式会社 | イグナイタ |
-
1983
- 1983-10-31 JP JP58203984A patent/JPS6095927A/ja active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2019145743A (ja) * | 2018-02-23 | 2019-08-29 | 日立オートモティブシステムズ株式会社 | イグナイタ |
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