JPS6083250U - 半導体装置 - Google Patents
半導体装置Info
- Publication number
- JPS6083250U JPS6083250U JP1983177118U JP17711883U JPS6083250U JP S6083250 U JPS6083250 U JP S6083250U JP 1983177118 U JP1983177118 U JP 1983177118U JP 17711883 U JP17711883 U JP 17711883U JP S6083250 U JPS6083250 U JP S6083250U
- Authority
- JP
- Japan
- Prior art keywords
- groove
- semiconductor element
- heat sink
- leads
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
め要約のデータは記録されません。
Description
第１図は本案の一実施例を示す横断面図、第２図は溝部
の拡大断面図、第３図は凹部の拡大断面である。 図中、１は放熱板、４は溝部、４′は凹部、５は半導体
素子、６はリード、７は金属細線、８は樹脂材である。
の拡大断面図、第３図は凹部の拡大断面である。 図中、１は放熱板、４は溝部、４′は凹部、５は半導体
素子、６はリード、７は金属細線、８は樹脂材である。
Claims (2)
- （１）入口が内部より狭い溝部を有する放熱板に半導体
素子を固定すると共に、半導体素子の電極とリードとを
金属細線にて接続し、かつ半導体素子、溝部を含む主要
部分を樹脂材にてモールド被覆したものにおいて、上記
溝部を、■字形に押圧形成した凹部の頂部を押圧変形す
ることによって構成したことを特徴とする半導体装置。 - （２）放熱板の両側部分に複数の溝部をリードの導出方
向に直角に形成したことを特徴とする実用新案登録請求
の範囲第１項に記載の半導体装置。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1983177118U JPS6083250U (ja) | 1983-11-15 | 1983-11-15 | 半導体装置 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1983177118U JPS6083250U (ja) | 1983-11-15 | 1983-11-15 | 半導体装置 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6083250U true JPS6083250U (ja) | 1985-06-08 |
Family
ID=30384878
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1983177118U Pending JPS6083250U (ja) | 1983-11-15 | 1983-11-15 | 半導体装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6083250U (ja) |
-
1983
- 1983-11-15 JP JP1983177118U patent/JPS6083250U/ja active Pending
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