JPS6075955A - チヤネル制御方式 - Google Patents

チヤネル制御方式

Info

Publication number
JPS6075955A
JPS6075955A JP18400183A JP18400183A JPS6075955A JP S6075955 A JPS6075955 A JP S6075955A JP 18400183 A JP18400183 A JP 18400183A JP 18400183 A JP18400183 A JP 18400183A JP S6075955 A JPS6075955 A JP S6075955A
Authority
JP
Japan
Prior art keywords
channel
ccw
processing
main
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18400183A
Other languages
English (en)
Japanese (ja)
Other versions
JPH023216B2 (enrdf_load_stackoverflow
Inventor
Morihiro Kamidachi
神館　盛弘
Noboru Yamamoto
昇 山本
Shigeru Hashimoto
繁 橋本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18400183A priority Critical patent/JPS6075955A/ja
Publication of JPS6075955A publication Critical patent/JPS6075955A/ja
Publication of JPH023216B2 publication Critical patent/JPH023216B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
JP18400183A 1983-09-30 1983-09-30 チヤネル制御方式 Granted JPS6075955A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18400183A JPS6075955A (ja) 1983-09-30 1983-09-30 チヤネル制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18400183A JPS6075955A (ja) 1983-09-30 1983-09-30 チヤネル制御方式

Publications (2)

Publication Number Publication Date
JPS6075955A true JPS6075955A (ja) 1985-04-30
JPH023216B2 JPH023216B2 (enrdf_load_stackoverflow) 1990-01-22

Family

ID=16145581

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18400183A Granted JPS6075955A (ja) 1983-09-30 1983-09-30 チヤネル制御方式

Country Status (1)

Country Link
JP (1) JPS6075955A (enrdf_load_stackoverflow)

Also Published As

Publication number Publication date
JPH023216B2 (enrdf_load_stackoverflow) 1990-01-22

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