JPS6062119A - Semiconductor wafer - Google Patents

Abstract

PURPOSE:To position a wafer with high accuracy by constituting both parallel contour sections in positioning marks by grooves. CONSTITUTION:Both left and right contour sections of a mark center A-A' in a semiconductor wafer 10 are constituted by grooves with recessed sections. When both width W and depth D of each groove are set to a proper small value at that time, the upper surface of a photo-resist layer 18 is flattened approximately on the formation of the layer 18, and the thickness of the layer 18 is equalized approximately in left and righ groove sections regarding the center A-A'. Consequently, the width of sections corresponding to left and right stepped sections is equalized approximately, the end edge section of a mark image is not divided, and width itself of the section can be reduced sufficiently. Accordingly, accuracy on a mark alignment can be improved largely.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor wafers used in manufacturing various semiconductor devices, and the parallel outline portions of the A☆1h' alignment marks are all formed with grooves, thereby achieving highly accurate positioning. This makes it possible to combine

Generally, alignment between a semiconductor wafer and a reticle (or photomask) is performed by comparing alignment marks provided on the wafer with alignment marks provided on the reticle or the like. Various types of alignment marks have been proposed to be provided on the wafer surface m1, such as elongated ones, rectangular ones, cross-shaped ones, and inverted C-shaped ones, but all of them are simple convex ones. It has a shaped or concave pattern, and its contour portion has a step-like cross section.

il Figures (-1 to (d) show cross-sectional structures of various conventional wafer marks; An example in which a concave pattern is formed by depositing a polysilicon layer 14 on it,
) is an example in which a convex pattern is formed on the surface of the wafer 100 by the insulating film 12 and the polysilicon layer 14 in the same manner as in the case of (, );
A metal layer 16 such as AA is placed thereon selectively.
In an example where a concave pattern is formed by depositing (di), (c
This is an example in which a convex pattern is formed on the insulating film 12 and the metal layer 16 in the same manner as in the case of ).

In any of the examples of (al to (dl) described above, the parallel outline portions of the wafer marks have a step-like cross section. When manufacturing integrated circuit devices etc. using such wafers, the top surface of the wafer After forming a photoresist layer 18 by applying photoresist by spin coating, the marks on the wafer and the marks on the reticle are compared and aligned, and then exposed to form the circuit pattern on the reticle. is transferred to the photoresist layer 18.

In such a process, it is required to align the wafer and reticle (or photomask) with high precision, but the conventional wafer mark structure described above has the disadvantage that sufficient alignment accuracy cannot be obtained. . That is, when the photoresist layer 18 is spin-coated, the photoresist layer 18 does not cover the irregularities of the base with a uniform thickness, but the thickness changes gradually over a wide area. In particular, at the mark installation location, as shown in FIG. 1, the thickness of the photoresist layer 18 changes depending on the coating conditions, the mark position and direction on the wafer, etc. May exhibit asymmetrical changes.

If the thickness of the photoresist layer exhibits an asymmetrical change like this, the light reflected from the interface between the photoresist layer and the thin film of polysilicon, silicon nitride, silicon oxide, etc. on the wafer will interfere with each other. A good mark image cannot be obtained in the alignment observation window, and the mark alignment accuracy decreases. For example, when trying to align the mark on the wafer with the mark n on the reticle using a type of reduction exposure device as shown in Figure 2, there is a difference in level between the left and right sides as shown in Figure 2(a). If the corresponding portions 2OA and 20B have different widths d1 and dl, the portions 2OA and 20B corresponding to the left and right steps may be divided into a plurality of parts, as shown in FIG. Furthermore, the values of dl and dl themselves are not small enough to obtain the required alignment accuracy.An object of the present invention is to develop an effective alignment mark structure that can solve the problems of the prior art described above. Our goal is to provide semiconductor wafers with

The semiconductor wafer according to the present invention is characterized in that the parallel contour portions of the alignment marks are all formed by grooves. That is, to explain this with reference to FIG. 3, conventionally, as shown in FIG.
Whereas the left and right contours of the mark were both formed by steps, in this invention, the left and right contours of the mark center A-A' are both grooves with a concave cross section, as shown in the same figure (t and l). The composition is disgusting.

In this case, if the width W and depth of each port are set appropriately small, when the photoresist layer 18 is formed as described above, its upper surface will be almost flat, and the mark center A-A' The thickness of the photoresist layer 18 is approximately equal in the left and right groove portions.

Therefore, the values of dl and dl shown in FIG. can. Therefore, the accuracy of mark alignment can be greatly improved.

Figures 4(a) to (d) all show examples that embody the structure of Figure 3(b), and Figures 4(a) to (b)
Figures (e) and (d) are examples in which the width W and depth DY of the groove are reduced by 1. FIGS.

In Figure 4, (a) is a half-faced 110 made of silicon, etc.
An insulating film 12 made of conoxide is formed, and a polysilicon layer 14 is deposited on it using chemical vapor deposition (CVD).
(b) shows an example in which multi-sectional V-shaped grooves are formed on the surface of the wafer film 10 by anisotropic etching using KOH or the like, and then the insulating film 12 is deposited on the surface. In (C), an insulating film 12 is formed on one surface of the wafer 10, a groove with a concave cross section is formed by anisotropic etching, and a polysilicon layer 14''a?cVD is formed on the insulating film 12.
(d) is an example in which an insulating film 12 is formed on the surface of a wafer 100, and then grooves with a concave cross section are formed by anisotropic etching, and a metal layer 16 such as Ad is deposited on the insulating film 12.
This is an example of coating by the Y sputter method.

In any of the examples (a) to (d) described above, the outline portion of the wafer mark has a concave cross section, and when the photoresist layer 18Y is formed covering the mark by the spin coating method, the upper surface thereof is as shown in FIG. (b) As mentioned for K, it is almost flat.

As described above, according to the present invention, since the parallel outline portions of the wafer mark are all formed by grooves, when the photoresist (Y) is applied, the upper surface is almost flattened, and a good mark image can be obtained. It will be done. Therefore, highly accurate wafer alignment can be achieved.

[Brief explanation of the drawing]

FIGS. 1(a) to (dl) are wafer cross-sectional views showing various conventional alignment mark structures. FIGS. 2(&) and (b) are wafer cross-sectional views showing various conventional alignment mark structures.
Plan view showing the mark alignment situation of tickle and wafer, 3rd
Figures (a) and (b) are wafer cross-sectional views showing the conventional structure and the structure of the present invention for alignment marks of the same shape. 10 is a cross-sectional view of a wafer showing an alignment mark structure. 10... Semiconductor wafer, 12... Insulating film, 14...
- Polysilicon layer, 16...metal layer, 18... photoresist layer. Applicant Nippon Musical Instruments Co., Ltd. Agent Patent Attorney Toshiaki Izawa Figure 1 Figure 1 Figure 2 Figure 3 A Figure 4

Claims (1)

[Claims] A semiconductor wafer having an alignment mark provided on its surface, wherein all parallel contour portions of the alignment mark are constituted by grooves.