JPH05291292A - Manufacture of thin film transistor - Google Patents

Abstract

PURPOSE:To easily obtain a fine and high precision off-set length in a thin film transistor having an off-set gate structure. CONSTITUTION:A side wall 5a is formed at a gate electrode 4 by plasma CVD method and a source/drain region 6 is formed to a poly-silicon layer 2 by ion implantation with this side wall 5a and the gate electrode 4 used as the mask. The source/drain region 6 is formed on the poly-silicon layer 2 at the outside of the side wall 5a and the length of the channel region 7 projected to the outside of the gate electrode 4, namely the off-set length is determined by the width of the side wall 5a. The fine side wall 5a by plasma CVD method can be formed with excellent uniformity and reproducibility by forming a film on the entire surface by the plasma CVD method and thereafter etching this film with anisotropic dry etching method. Accordingly, a fine offset length can easily be formed with high accuracy on the self-alignment basis.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor having an offset gate structure.

[0002]

2. Description of the Related Art A polysilicon thin film transistor is characterized in that a large leak current is generated when the gate voltage is reverse biased, and an offset gate structure is considered as one method of reducing this leak current.
The offset gate structure is a structure in which the gate electrode is smaller than the channel region between the source and drain regions,
The length of the channel region portion protruding outward from both side ends of the gate electrode is called an offset length.

A thin film transistor having such an offset gate structure is conventionally manufactured as follows. First, a polysilicon layer is patterned on an insulating substrate such as ceramic or glass, and a gate insulating layer is formed thereon.
Further, a photoresist pattern is formed on the gate insulating layer by a photolithography method, and ions are implanted using the photoresist pattern as a mask to form source / drain regions in the polysilicon layer. Next, after removing the photoresist pattern, a gate electrode forming layer made of aluminum or the like is formed on the gate insulating layer, and a photoresist pattern is formed again on the gate electrode forming layer by photolithography. At this time, the photoresist pattern is made smaller than the channel region between the source / drain regions.
Then, the gate electrode forming layer is etched by using this photoresist pattern as a mask to form the gate electrode smaller than the channel region, thereby completing the thin film transistor having the offset gate structure.

[0004]

However, in the conventional manufacturing method as described above, a photolithography process is required twice in total to form the source / drain regions and the gate electrode in order to obtain the offset gate structure. Therefore, there is a problem that the process is complicated and long. Further, usually, if the offset length is too long, the on-current of the transistor decreases, so 1 μm or less is desirable. However, in the above-described conventional manufacturing method, the offset length is determined in relation to the two photolithography steps. In order to obtain a fine offset length, there is a drawback that high alignment accuracy and processing accuracy are required in each photolithography process. An object of the present invention is to provide a method of manufacturing a thin film transistor that can easily form a fine offset length with high accuracy and can reduce the number of photolithography steps.

[0005]

According to the present invention, a semiconductor layer is covered with a gate insulating layer, a gate electrode is formed on the gate insulating layer, sidewalls are formed on both side walls of the gate electrode, and then the gate electrode is formed. Ion implantation is performed using the sidewalls and the gate electrode as a mask to form source / drain regions in the semiconductor layer outside the sidewalls.

[0006]

According to the present invention, since the source / drain regions are formed in the semiconductor layer outside the sidewalls, the length of the channel region between the source / drain regions protruding outward from both side ends of the gate electrode, that is, The offset length is
Determined by the width of the sidewalls. Here, the sidewalls are formed on the entire surface by a plasma CVD film method that faithfully reproduces the shape of the underlying step, and then this film is etched by a dry etching method with excellent anisotropy to obtain a fine uniformity.・ Can be formed with good reproducibility. Therefore, according to the present invention, it is possible to easily form a fine offset length with high accuracy by using the sidewall in a self-aligning manner. Further, according to the present invention, the photolithography process is performed only once when the gate electrode is formed, so that the manufacturing process is simple and short.

[0007]

1 to 4 are sectional views showing an embodiment of the present invention in the order of manufacturing steps. An embodiment will be described below with reference to these drawings. First, as shown in FIG. 1, a polysilicon layer 2 is patterned on an upper surface of an insulating substrate 1 made of ceramic or glass. Next, as shown in FIG. 2, a gate insulating layer 3 made of silicon oxide or the like is formed on the entire surface, and the polysilicon layer 2 is formed by the gate insulating layer 3.
Cover. Next, aluminum is deposited on the entire surface as a gate electrode forming layer, and the aluminum is patterned by a photolithography process to form the gate electrode 4 on the gate insulating layer 3. After that, as shown in FIG. 3, a nitride film 5 is formed on the entire surface by a plasma CVD film. The thin film formation by plasma CVD is excellent in step coverage and faithfully reproduces the shape of the underlying step.
Therefore, when it is formed on the entire surface as shown in FIG. 3, the nitride film 5 becomes thick at the side wall step portion of the gate electrode 4. Therefore, when this nitride film 5 is next etched by a dry etching method having excellent anisotropy, the nitride film 5 remains only on the side wall portion of the gate electrode 4, and the side wall 5a is formed.

Next, the sidewall 5a and the gate electrode 4
As shown in FIG. 3, ion implantation of impurities is performed by using the mask as a mask and activation heat treatment is performed to form source / drain regions 6 in the polysilicon layer 2. At this time, the source / drain regions 6 are formed in the polysilicon layer 2 outside the sidewalls 5a by using the sidewalls 5a and the gate electrodes 4 as a mask. Therefore, the channel region 7, which is the portion of the polysilicon layer 2 between the source / drain regions 6, projects to the outside of the gate electrode 4 by the width of the sidewall 5a, and the gate electrode 4 is smaller than the channel region 7. The offset gate structure is completed. The length of the channel region 7 projecting outward from both side ends of the gate electrode 4, that is, the offset length is substantially equal to the width of the sidewall 5a. Here, the sidewall 5a is formed by the plasma CV as described above.
By forming a thin film by D and anisotropic dry etching, it can be finely formed with good uniformity and reproducibility. Therefore, according to this method, the side wall 5a can be utilized to easily and precisely form a fine offset length in a self-aligning manner.

After the offset gate structure is formed in this way, an interlayer insulating film 8 is then formed on the entire surface as shown in FIG. At this time, the sidewall 5a may be removed or may be left. If left, the sidewall 5a also becomes part of the interlayer insulating film. Then, a contact hole 9 is formed in the interlayer insulating film 8 and the gate insulating layer 3 so as to reach the source / drain region 6 of the polysilicon layer 2, and the contact hole 9 is further formed.
Source connected to the source / drain region 6 through
The drain electrode 10 is formed. Thus, a thin film transistor having an offset gate structure is completed.

[0010]

As described above, according to the present invention, the side wall of the gate electrode is finely formed with good uniformity and reproducibility, and the fine offset length is self-aligned with the side wall. It can be easily formed with high precision. Therefore, the thin film transistor formed by the method of the present invention can suppress a leak current when a reverse bias is applied and can have a large ON current, and can be used for a driver of a liquid crystal display or the like. Further, according to the present invention, the photolithography process is performed only once when the gate electrode is formed, and the manufacturing process can be simplified and shortened.

[Brief description of drawings]

FIG. 1 is a sectional view showing a first step in one embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a step that follows FIG. 1 in one embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a step that follows FIG. 2 in one embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a step that follows FIG. 3 in one embodiment of the present invention.

[Explanation of symbols]

 2 polysilicon layer 3 gate insulating layer 4 gate electrode 5 nitride film 5a sidewall 6 source / drain region

Claims (2)

[Claims] 1. A semiconductor layer is covered with a gate insulating layer, a gate electrode is formed on the gate insulating layer, sidewalls are formed on both side walls of the gate electrode, and then the sidewall and the gate electrode are masked. A method of manufacturing a thin film transistor, wherein source / drain regions are formed in the semiconductor layer outside the sidewalls by ion implantation as described above. 2. The method of manufacturing a thin film transistor according to claim 1, wherein the side wall is formed by plasma CVD, and then an unnecessary portion is etched by anisotropic etching.