JPS6059599A - 不揮発性半導体メモリ - Google Patents

不揮発性半導体メモリ

Info

Publication number
JPS6059599A
JPS6059599A JP58168689A JP16868983A JPS6059599A JP S6059599 A JPS6059599 A JP S6059599A JP 58168689 A JP58168689 A JP 58168689A JP 16868983 A JP16868983 A JP 16868983A JP S6059599 A JPS6059599 A JP S6059599A
Authority
JP
Japan
Prior art keywords
column
row
dummy
dummy cell
cell group
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58168689A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0313680B2 (ko
Inventor
Misao Higuchi
樋口 三佐男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58168689A priority Critical patent/JPS6059599A/ja
Publication of JPS6059599A publication Critical patent/JPS6059599A/ja
Publication of JPH0313680B2 publication Critical patent/JPH0313680B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • Read Only Memory (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
JP58168689A 1983-09-13 1983-09-13 不揮発性半導体メモリ Granted JPS6059599A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58168689A JPS6059599A (ja) 1983-09-13 1983-09-13 不揮発性半導体メモリ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58168689A JPS6059599A (ja) 1983-09-13 1983-09-13 不揮発性半導体メモリ

Publications (2)

Publication Number Publication Date
JPS6059599A true JPS6059599A (ja) 1985-04-05
JPH0313680B2 JPH0313680B2 (ko) 1991-02-25

Family

ID=15872637

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58168689A Granted JPS6059599A (ja) 1983-09-13 1983-09-13 不揮発性半導体メモリ

Country Status (1)

Country Link
JP (1) JPS6059599A (ko)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6251319A (ja) * 1985-08-28 1987-03-06 インターナショナル ビジネス マシーンズ コーポレーション モデム受信機における利得調節方法
JPS6254900A (ja) * 1985-04-26 1987-03-10 エステーミクロエレクトロニクス ソシエテ アノニム プログラム可能な読出し専用メモリ
JPS62177799A (ja) * 1986-01-30 1987-08-04 Toshiba Corp 半導体記憶装置
EP0239968A2 (en) * 1986-03-31 1987-10-07 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device
JPS6334800A (ja) * 1986-07-28 1988-02-15 Nec Ic Microcomput Syst Ltd 半導体メモリ
US4749947A (en) * 1986-03-10 1988-06-07 Cross-Check Systems, Inc. Grid-based, "cross-check" test structure for testing integrated circuits
JPS6467797A (en) * 1987-09-09 1989-03-14 Toshiba Corp Semiconductor memory device
US5065090A (en) * 1988-07-13 1991-11-12 Cross-Check Technology, Inc. Method for testing integrated circuits having a grid-based, "cross-check" te
JP2007080477A (ja) * 2005-09-09 2007-03-29 Samsung Electronics Co Ltd セルストリングに配置されるダミーセルを持つ不揮発性半導体メモリ装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5585957A (en) * 1978-11-25 1980-06-28 Fujitsu Ltd Logic circuit for test bit selection

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5585957A (en) * 1978-11-25 1980-06-28 Fujitsu Ltd Logic circuit for test bit selection

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6254900A (ja) * 1985-04-26 1987-03-10 エステーミクロエレクトロニクス ソシエテ アノニム プログラム可能な読出し専用メモリ
JPS6251319A (ja) * 1985-08-28 1987-03-06 インターナショナル ビジネス マシーンズ コーポレーション モデム受信機における利得調節方法
JPH0556693B2 (ko) * 1985-08-28 1993-08-20 Ibm
JPS62177799A (ja) * 1986-01-30 1987-08-04 Toshiba Corp 半導体記憶装置
JPH0468720B2 (ko) * 1986-01-30 1992-11-04 Tokyo Shibaura Electric Co
US4749947A (en) * 1986-03-10 1988-06-07 Cross-Check Systems, Inc. Grid-based, "cross-check" test structure for testing integrated circuits
JPS62229600A (ja) * 1986-03-31 1987-10-08 Toshiba Corp 不揮発性半導体記憶装置
JPH0530000B2 (ko) * 1986-03-31 1993-05-06 Tokyo Shibaura Electric Co
EP0239968A2 (en) * 1986-03-31 1987-10-07 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device
JPS6334800A (ja) * 1986-07-28 1988-02-15 Nec Ic Microcomput Syst Ltd 半導体メモリ
JPS6467797A (en) * 1987-09-09 1989-03-14 Toshiba Corp Semiconductor memory device
US5065090A (en) * 1988-07-13 1991-11-12 Cross-Check Technology, Inc. Method for testing integrated circuits having a grid-based, "cross-check" te
JP2007080477A (ja) * 2005-09-09 2007-03-29 Samsung Electronics Co Ltd セルストリングに配置されるダミーセルを持つ不揮発性半導体メモリ装置

Also Published As

Publication number Publication date
JPH0313680B2 (ko) 1991-02-25

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