JPS6027060B2 - リツプル・レジスタ装置 - Google Patents

リツプル・レジスタ装置

Info

Publication number
JPS6027060B2
JPS6027060B2 JP55121832A JP12183280A JPS6027060B2 JP S6027060 B2 JPS6027060 B2 JP S6027060B2 JP 55121832 A JP55121832 A JP 55121832A JP 12183280 A JP12183280 A JP 12183280A JP S6027060 B2 JPS6027060 B2 JP S6027060B2
Authority
JP
Japan
Prior art keywords
data
register
stage
ripple
full
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55121832A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5674731A (en
Inventor
モ−リス・レロン・ハツトソン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Control Data Corp
Original Assignee
Control Data Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Control Data Corp filed Critical Control Data Corp
Publication of JPS5674731A publication Critical patent/JPS5674731A/ja
Publication of JPS6027060B2 publication Critical patent/JPS6027060B2/ja
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/08—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/05—Electric or magnetic storage of signals before transmitting or retransmitting for changing the transmission rate

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Communication Control (AREA)
  • Shift Register Type Memory (AREA)
  • Information Transfer Systems (AREA)
JP55121832A 1979-11-19 1980-09-04 リツプル・レジスタ装置 Expired JPS6027060B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/095,698 US4296477A (en) 1979-11-19 1979-11-19 Register device for transmission of data having two data ranks one of which receives data only when the other is full
US95698 1993-07-22

Publications (2)

Publication Number Publication Date
JPS5674731A JPS5674731A (en) 1981-06-20
JPS6027060B2 true JPS6027060B2 (ja) 1985-06-27

Family

ID=22253203

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55121832A Expired JPS6027060B2 (ja) 1979-11-19 1980-09-04 リツプル・レジスタ装置

Country Status (7)

Country Link
US (1) US4296477A (en, 2012)
JP (1) JPS6027060B2 (en, 2012)
AU (1) AU537192B2 (en, 2012)
CA (1) CA1125406A (en, 2012)
DE (1) DE3042105A1 (en, 2012)
FR (1) FR2470496B1 (en, 2012)
GB (2) GB2064180B (en, 2012)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019026369A1 (ja) 2017-08-02 2019-02-07 株式会社明電舎 インバータ装置

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4433391A (en) * 1981-08-17 1984-02-21 Burroughs Corporation Buffered handshake bus with transmission and response counters for avoiding receiver overflow
JPS62211725A (ja) * 1986-03-12 1987-09-17 Sanyo Electric Co Ltd デ−タ伝送路制御装置
US4833655A (en) * 1985-06-28 1989-05-23 Wang Laboratories, Inc. FIFO memory with decreased fall-through delay
JPH0823807B2 (ja) * 1987-08-26 1996-03-06 松下電器産業株式会社 Ｆｉｆｏメモリ
US5095462A (en) * 1990-05-25 1992-03-10 Advanced Micro Devices, Inc. Fifo information storage apparatus including status and logic modules for each cell
US5418910A (en) * 1992-05-05 1995-05-23 Tandy Corporation Dual buffer cache system for transferring audio compact disk subchannel information to a computer
CA2106271C (en) * 1993-01-11 2004-11-30 Joseph H. Steinmetz Single and multistage stage fifo designs for data transfer synchronizers
IT1293652B1 (it) * 1997-07-25 1999-03-08 Alsthom Cge Alcatel Sistema di implementazione di una memoria elastica
TWI560552B (en) * 2015-01-30 2016-12-01 Via Tech Inc Interface chip and control method therefor
CN114816319B (zh) * 2022-04-21 2023-02-17 中国人民解放军32802部队 一种fifo存储器的多级流水读写方法和装置

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1259397A (fr) * 1960-02-19 1961-04-28 Alsthom Cgee Bascule binaire logique
BE636474A (en, 2012) * 1962-09-06
US3460098A (en) * 1967-03-15 1969-08-05 Sperry Rand Corp Non-synchronous design for digital device control
DE1933907A1 (de) * 1969-07-03 1971-03-11 Siemens Ag Pufferspeicher
NL7014737A (en, 2012) * 1970-10-08 1972-04-11
US3704452A (en) * 1970-12-31 1972-11-28 Ibm Shift register storage unit
NL7105512A (en, 2012) * 1971-04-23 1972-10-25
US3742466A (en) * 1971-11-24 1973-06-26 Honeywell Inf Systems Memory system for receiving and transmitting information over a plurality of communication lines
US3781821A (en) * 1972-06-02 1973-12-25 Ibm Selective shift register
FR2231295A1 (en) * 1973-05-25 1974-12-20 Cit Alcatel Buffer memory between data input and processor - supplies input data to processor with different priority
US3992699A (en) * 1974-11-13 1976-11-16 Communication Mfg. Co. First-in/first-out data storage system
US3988601A (en) * 1974-12-23 1976-10-26 Rca Corporation Data processor reorder shift register memory
US4051353A (en) * 1976-06-30 1977-09-27 International Business Machines Corporation Accordion shift register and its application in the implementation of level sensitive logic system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019026369A1 (ja) 2017-08-02 2019-02-07 株式会社明電舎 インバータ装置
KR20200020895A (ko) 2017-08-02 2020-02-26 메이덴샤 코포레이션 인버터 장치
US10985672B2 (en) 2017-08-02 2021-04-20 Meidensha Corporation Inverter device having three phase sections

Also Published As

Publication number Publication date
JPS5674731A (en) 1981-06-20
GB2132456B (en) 1985-01-09
DE3042105A1 (de) 1981-05-21
AU537192B2 (en) 1984-06-14
GB8314578D0 (en) 1983-06-29
DE3042105C2 (en, 2012) 1990-04-26
GB2064180B (en) 1984-07-25
FR2470496B1 (fr) 1986-05-09
FR2470496A1 (fr) 1981-05-29
AU6291380A (en) 1981-05-28
GB2064180A (en) 1981-06-10
US4296477A (en) 1981-10-20
CA1125406A (en) 1982-06-08
GB2132456A (en) 1984-07-04

Similar Documents

Publication Publication Date Title
US5195185A (en) Dynamic bus arbitration with concurrent same bus granting every cycle
KR0145321B1 (ko) 2방향 데이타 전송장치
US4965793A (en) Method and apparatus for interfacing a system control unit for a multi-processor
US5140680A (en) Method and apparatus for self-timed digital data transfer and bus arbitration
JPH036534B2 (en, 2012)
JPS5847050B2 (ja) 入出力割込みシステム
JPS6027060B2 (ja) リツプル・レジスタ装置
JPS599926B2 (ja) Ｎｒｚ／２相マイクロコンピユ−タ直列通信論理装置
JPH0574111B2 (en, 2012)
US5473755A (en) System for controlling data stream by changing fall through FIFO last cell state of first component whenever data read out of second component last latch
US6289065B1 (en) FIFO status indicator
US6823413B2 (en) Interrupt signal processing apparatus
JPH0650496B2 (ja) 中央処理装置の性能を向上させる方法および装置
US4333176A (en) Data extraction means for use in a data transmission system
JP2570847B2 (ja) データ転送方式
US3766530A (en) Communications between central unit and peripheral units
JPS6048785B2 (ja) 主記憶制御方式
JPH0226242B2 (en, 2012)
EP0378422A3 (en) Look ahead bus transfer request
KR100593787B1 (ko) 통신 버스에서의 차동 스트로빙 방법 및 장치
US3247492A (en) Automatic memory start circuit for asynchronous data processing system
JP3444933B2 (ja) バスウェイト機構を備えるデジタルコンピュータ装置
US5999742A (en) Dual latch data transfer pacing logic using a timer to maintain a data transfer interval
US7296176B1 (en) Method and apparatus for limiting the number of asynchronous events that occur during a clock cycle
SU1238088A1 (ru) Устройство дл сопр жени электронно-вычислительной машины с абонентом