FR2231295A1 - Buffer memory between data input and processor - supplies input data to processor with different priority - Google Patents

Buffer memory between data input and processor - supplies input data to processor with different priority

Info

Publication number
FR2231295A1
FR2231295A1 FR7319131A FR7319131A FR2231295A1 FR 2231295 A1 FR2231295 A1 FR 2231295A1 FR 7319131 A FR7319131 A FR 7319131A FR 7319131 A FR7319131 A FR 7319131A FR 2231295 A1 FR2231295 A1 FR 2231295A1
Authority
FR
France
Prior art keywords
data
processor
stage
input
buffer memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
FR7319131A
Other languages
French (fr)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alcatel CIT SA
Original Assignee
Alcatel CIT SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel CIT SA filed Critical Alcatel CIT SA
Priority to FR7319131A priority Critical patent/FR2231295A1/en
Publication of FR2231295A1 publication Critical patent/FR2231295A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/08—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

The buffer memory, between a data input and a consynchronous processor, transfers the data continuously from the register stage to the following (n+1)th stage, and is conditioned solely by the absence of information in the latter stage, independent of the occupation of the other stages, where n varies between 1 and the total number of register stages minus 1. The transfer of data can also be controlled by a clock pulse. Pref. each stage (3, 5, 6, 7, 4) has a number of flip-flops, all but one used to store a data word having a similar number of bits, the last flip-flop (23-27) set to 1 when the stage contains a data word and O when it is free.
FR7319131A 1973-05-25 1973-05-25 Buffer memory between data input and processor - supplies input data to processor with different priority Withdrawn FR2231295A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR7319131A FR2231295A1 (en) 1973-05-25 1973-05-25 Buffer memory between data input and processor - supplies input data to processor with different priority

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7319131A FR2231295A1 (en) 1973-05-25 1973-05-25 Buffer memory between data input and processor - supplies input data to processor with different priority

Publications (1)

Publication Number Publication Date
FR2231295A1 true FR2231295A1 (en) 1974-12-20

Family

ID=9120017

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7319131A Withdrawn FR2231295A1 (en) 1973-05-25 1973-05-25 Buffer memory between data input and processor - supplies input data to processor with different priority

Country Status (1)

Country Link
FR (1) FR2231295A1 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2410338A1 (en) * 1977-11-24 1979-06-22 Hochiki Co MEMORY CIRCUIT FOR LOSS PREVENTION SYSTEM
FR2470496A1 (en) * 1979-11-19 1981-05-29 Control Data Corp REGISTER
EP0084425A2 (en) * 1982-01-18 1983-07-27 M/A-Com Linkabit, Inc. Self-shifting LIFO stack
FR2601491A1 (en) * 1986-07-10 1988-01-15 Cit Alcatel WAITING MEMORY
EP2515226A1 (en) * 2011-04-21 2012-10-24 STMicroelectronics SA An arrangement

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2410338A1 (en) * 1977-11-24 1979-06-22 Hochiki Co MEMORY CIRCUIT FOR LOSS PREVENTION SYSTEM
FR2470496A1 (en) * 1979-11-19 1981-05-29 Control Data Corp REGISTER
EP0084425A2 (en) * 1982-01-18 1983-07-27 M/A-Com Linkabit, Inc. Self-shifting LIFO stack
EP0084425A3 (en) * 1982-01-18 1984-09-26 M/A-Com Linkabit, Inc. Self-shifting lifo stack
FR2601491A1 (en) * 1986-07-10 1988-01-15 Cit Alcatel WAITING MEMORY
EP0254123A1 (en) * 1986-07-10 1988-01-27 Alcatel Cit Queue-memory
EP2515226A1 (en) * 2011-04-21 2012-10-24 STMicroelectronics SA An arrangement

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Legal Events

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