JPS5251843A - Detector - Google Patents

Detector

Info

Publication number
JPS5251843A
JPS5251843A JP12814275A JP12814275A JPS5251843A JP S5251843 A JPS5251843 A JP S5251843A JP 12814275 A JP12814275 A JP 12814275A JP 12814275 A JP12814275 A JP 12814275A JP S5251843 A JPS5251843 A JP S5251843A
Authority
JP
Japan
Prior art keywords
output
information
detector
input
deteriorating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12814275A
Other languages
Japanese (ja)
Inventor
Masao Kodera
Matatoyo Hinachi
Takeshi Matsui
Yoshiyuki Kago
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soken Inc
Original Assignee
Nippon Soken Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Soken Inc filed Critical Nippon Soken Inc
Priority to JP12814275A priority Critical patent/JPS5251843A/en
Publication of JPS5251843A publication Critical patent/JPS5251843A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/02Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Control Of Motors That Do Not Use Commutators (AREA)

Abstract

PURPOSE:The information is input and output based on 1st and 2nd clock signals against memory selecting the time during which no information transfer is performed. In this way, data input/output can be simplified without deteriorating the processing operation of controlling computer.
JP12814275A 1975-10-23 1975-10-23 Detector Pending JPS5251843A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12814275A JPS5251843A (en) 1975-10-23 1975-10-23 Detector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12814275A JPS5251843A (en) 1975-10-23 1975-10-23 Detector

Publications (1)

Publication Number Publication Date
JPS5251843A true JPS5251843A (en) 1977-04-26

Family

ID=14977425

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12814275A Pending JPS5251843A (en) 1975-10-23 1975-10-23 Detector

Country Status (1)

Country Link
JP (1) JPS5251843A (en)

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