JPS60246457A - メモリアクセス制御回路 - Google Patents

メモリアクセス制御回路

Info

Publication number
JPS60246457A
JPS60246457A JP59101991A JP10199184A JPS60246457A JP S60246457 A JPS60246457 A JP S60246457A JP 59101991 A JP59101991 A JP 59101991A JP 10199184 A JP10199184 A JP 10199184A JP S60246457 A JPS60246457 A JP S60246457A
Authority
JP
Japan
Prior art keywords
access
channel
chb
data
msu
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59101991A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0347542B2 (enExample
Inventor
Takashi Chiba
隆 千葉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59101991A priority Critical patent/JPS60246457A/ja
Publication of JPS60246457A publication Critical patent/JPS60246457A/ja
Publication of JPH0347542B2 publication Critical patent/JPH0347542B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP59101991A 1984-05-21 1984-05-21 メモリアクセス制御回路 Granted JPS60246457A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59101991A JPS60246457A (ja) 1984-05-21 1984-05-21 メモリアクセス制御回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59101991A JPS60246457A (ja) 1984-05-21 1984-05-21 メモリアクセス制御回路

Publications (2)

Publication Number Publication Date
JPS60246457A true JPS60246457A (ja) 1985-12-06
JPH0347542B2 JPH0347542B2 (enExample) 1991-07-19

Family

ID=14315297

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59101991A Granted JPS60246457A (ja) 1984-05-21 1984-05-21 メモリアクセス制御回路

Country Status (1)

Country Link
JP (1) JPS60246457A (enExample)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54128635A (en) * 1978-03-30 1979-10-05 Toshiba Corp Control system for cash memory
JPS563485A (en) * 1979-06-20 1981-01-14 Nec Corp Buffer memory device
JPS57205885A (en) * 1981-06-15 1982-12-17 Fujitsu Ltd Channel buffer controlling system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54128635A (en) * 1978-03-30 1979-10-05 Toshiba Corp Control system for cash memory
JPS563485A (en) * 1979-06-20 1981-01-14 Nec Corp Buffer memory device
JPS57205885A (en) * 1981-06-15 1982-12-17 Fujitsu Ltd Channel buffer controlling system

Also Published As

Publication number Publication date
JPH0347542B2 (enExample) 1991-07-19

Similar Documents

Publication Publication Date Title
US7620789B2 (en) Out of order DRAM sequencer
US6378041B2 (en) Shared instruction cache for multiple processors
US5155832A (en) Method to increase performance in a multi-level cache system by the use of forced cache misses
KR960035270A (ko) 순서에 따르지 않고 판독 및 기입 명령을 실행하는 메모리 제어기
JPS6297036A (ja) 計算機システム
US5293622A (en) Computer system with input/output cache
JPS60246457A (ja) メモリアクセス制御回路
US4628450A (en) Data processing system having a local memory which does not use a directory device with distributed resident programs and a method therefor
JP2000207203A (ja) マイクロコントロ―ラ
US5933856A (en) System and method for processing of memory data and communication system comprising such system
JPS6398749A (ja) デ−タ処理装置
JP3161422B2 (ja) マイクロコンピュータ
JPS63240651A (ja) キヤツシユメモリ
JPH05257807A (ja) キャッシュメモリ制御装置
JPH03225452A (ja) ビットエンコードデータ処理システム及びデータワードにおいてダグビットをそう入／抽出する処理方法
JPH0447350A (ja) 主記憶読み出し応答制御方式
JPS60183652A (ja) キヤツシユメモリ制御方法
JPH01290052A (ja) キャッシュメモリ
JPH03271859A (ja) 情報処理装置
EP0400851A2 (en) Efficient cache utilizing a store buffer
JPS63286959A (ja) メモリアクセス方式
JPS635432A (ja) マイクロプロセツサ
JPH0412858B2 (enExample)
JPS6222165A (ja) 主記憶装置アクセス制御方式
JPH0652045A (ja) マイクロプロセッサ