JPS60206053A - リ−ドフレ−ム - Google Patents

リ−ドフレ−ム

Info

Publication number
JPS60206053A
JPS60206053A JP59059455A JP5945584A JPS60206053A JP S60206053 A JPS60206053 A JP S60206053A JP 59059455 A JP59059455 A JP 59059455A JP 5945584 A JP5945584 A JP 5945584A JP S60206053 A JPS60206053 A JP S60206053A
Authority
JP
Japan
Prior art keywords
alloy
lead frame
plate
bendability
cladding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59059455A
Other languages
English (en)
Other versions
JPH061800B2 (ja
Inventor
Takeshi Yasui
安井　毅
Shigemi Yamane
山根　茂美
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP59059455A priority Critical patent/JPH061800B2/ja
Publication of JPS60206053A publication Critical patent/JPS60206053A/ja
Publication of JPH061800B2 publication Critical patent/JPH061800B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 ［発明の技術分野］ 本発明は半導体用のリードフレームに関する。
［発明の技術的背景とその問題点］ 従来から、半導体のリードフレームとしては、４２アロ
イ（４２％Ｎｉ−Ｆｅ合金）のようなＦｅ−Ｎｉ系合金
で形成されたものが知られている。
しかしながら、このようなリードフレームは、硬度が高
く折曲げ性に優れている反面、半導体の高集積化に伴っ
て要求されてきている熱放散性が充分でなく、また材料
価格が高いという欠点があった。
近年、このようなＦｅ−Ｎｉ系合金に代って値段の安価
なＣｕ合金でリードフレームを形成することが検討され
ているが、Ａｌ１線とのボンディング性、硬度、折曲げ
性、耐酸化性等のリードフレームに要求されるすべての
特性を満足させるものは得られていない。
［発明の目的１ 本発明者らはこのような点に対処して鋭意研究を進めた
結果、従来のｌ”ｅ−Ｎｉ系合金にＣｕまたはＣｕ合金
、特に析出硬化形のＣｕ合金をクラッドすることにより
前述の特性をすべて満足させるリードフレームが得られ
ることを見出した。
本発明はこのような知見に基づいてなされたもので、Ａ
ｌ１線とのボンディング性、硬度、折曲げ性、耐酸化性
および半田付は性に優れ、熱放散性の高いリードフレー
ムを提供することを目的とする。
［発明の概要］ ずなわち本発明は、Ｆｅ合金からなる板状体の両面に、
ＣｕまたはＣｔ１合金からなる薄板をクラッドしてなる
クラツド材で形成したことを特徴とするリードフレーム
である。
本発明に用いるクラツド材の一例を第１図に示ず。同図
において符号１はＦｅ合金からなる板状体、符号２はそ
の両面にクラッドされたＱｕまたはＣｕ合金からなる薄
板を示す。
ここで板状体１を構成するＦｅ合金としては、例えば４
２アロイやコバール（Ｆ’ｅ　−Ｎｉ　−Ｃ。
合金）を使用することができる。また、これらの板状体
の両面にクラッドする薄板２は、２０μｍ以上の厚さの
ものを使用するのが望ましく、特に析出硬化形のＣｕ合
金で構成した薄板を使用するのが望ましい。
このような析出硬化形Ｃｕ合金は、ｃｒ　ｓ　Ｚｒのよ
うな析出硬化成分元素とＣｕを高温で溶解し、連続鋳造
法により鋳造し、さらに熱間圧延、冷間圧延し、溶体化
熱処理を行なった後、冷間加工を施し、次いで析出硬化
処理を行なうことにより得ることができる。
特にＣＩ’０．１〜１重量％とＺｒ０．０５〜０゜５重
量％を含むＣｕ合金を４００〜５００℃の温度で析出硬
化処理し、１０００〜１００００個／−の密度で０．５
〜５０μ操の析出物を析出させたＣｕ合金は、硬度、折
曲げ性、耐熱性、！電性に優れているので使用すること
が望ましい。
また、上記割合のＣｒ　５７−ｒ以外にＭａ、Ｓｉ、３
ｎ、Ｎｉ％Ｚｎ、Ｍｎ、Ｐ、ＡＵから選ばれた１種また
は２種以上の元素を合計量で１重量％以下含有させ、同
様に析出硬化処理を施したＣｕ合金を用いることもでき
る。
本発明のリードフレームは、このようなＣｕ合金または
Ｃｕからなる薄板２を、前述のＦｅ合金からなる板状体
１の両面に全体の厚さが０．１５〜０，２５ｎになるよ
うに常法により冷間でクラッドしてなるクラッド材料を
４００〜５００℃の温度で析出硬化処理した後、打抜き
加工等の方法で所定形状に成形することにより得られ、
折曲げ性を始めとする種々の特性に極めて優れている。
［発明の実施例〕 以下本発明の実施例について記載する。
次表に示す組成のＣｕ合金を連続鋳造し、熱間圧延後、
溶体化熱処理を行なった。次いで冷間圧延により厚さ０
．２ｕの板状に仕上げた。
こうして得られた薄板を、４２７０イからなる厚さ０．
１１ｍｍの板状体の両面に常法によりクラッドし、４５
０℃で析出硬化処理を施し、これを打抜き加工し、第２
図に示す形状のリードフレーム３を製造した。
次に得られたリードフレームの折曲げ性、表面硬［ｆお
よＵＡＬＩ線とのボンディング性を試験した。
結果は同表に示す通りであった。なお、同表中ボンディ
ング性は第３図に示すように、実施例のリードフレーム
３のチップ搭載部３ａにダイ接着剤４を介してシリコン
ウェハー５を接着し、さらにその上にＡｕ蒸着膜６を形
成した後、このＡｕ蒸＠Ｍ６とこれに対応するリードフ
レームの接続部３ｂをＡｉＪめっきを施すことなく、Ａ
ｌｌｌ子線直接接続したときＡＬＩ線７のＡ部で破断し
たものをＯ印とした。符号８は樹脂モールド部を示ず。
なお、８部で破断したものはなかった。
（以下余白） ＊９０℃繰り返し曲げ試験、規格４回以上［発明の効果
］ 以上の説明から明らかなように本発明のリードフレーム
は、Ａｌ１線とのボンディング性、表面硬度、折曲げ性
に優れ、しかも耐酸化性、半田付は性および熱放散性が
良好で安価である。
また、クラッドされたＦｅ合金からなる板状体をＣＬＩ
またはＣｕ合金の薄板とは完全な金属結合により接合さ
れており剥離することがない。
【図面の簡単な説明】
第１図は本発明に用いるクラツド材の一例を示す横断面
図、第２図は本発明の一実施例のリードフレームの平面
図、第３図は実施例のり−ドフレームのＡｕ線とのボン
ディング性の試験方法を示す拡大断面図である。 １・・・・・・・・・・・・Ｆｅ合金からなる板状体２
・・・・・・・・・・・・ＣｕまたはＣｕ合金からなる
薄板 ３・・・・・・・・・・・・リードフレーム４・・・・
・・・・・・・・ダイ接着剤５・・・・・・・・・・・
・シリコンウェハー６・・・・・・・・・・・・Ａｕ蒸
着膜７・・・・・・・・・・・・Ａｕ線 代理人弁理士　則　近　憲　佑 （ほか１名） 第１図 第２図

Claims (5)

    【特許請求の範囲】
  1. （１）Ｆｅ合金からなる板状体の両面に、ＣｕまたはＣ
    ｕ合金からなる薄板をクラッドしてなるクラツド材で形
    成したことを特徴とするリードフレーム。
  2. （２）Ｃｕ合金は、析出硬化形のＣｕ合金である特許請
    求の範囲第１項記載のリードフレーム。
  3. （３）析出硬化形Ｃｕ合金は、析出硬化元素としてＱｒ
    とＺｒを含有するＣｕ合金である特許請求の範囲第２項
    記載のリードフレーム。
  4. （４）析出硬化形Ｃｕ合金は、Ｃ「０．１〜１重量％と
    Ｚｒ　０．０５〜０．５！ｆｆｉ％とを含有したもので
    ある特許請求の範囲第３項記載のリードフレーム。
  5. （５）クラッド合金は、４００〜５００℃の温度で析出
    硬化処理がなされたものである特許請求の範囲第１項な
    いし第４項のいずれかに族記載のリードフレーム。
JP59059455A 1984-03-29 1984-03-29 リ−ドフレ−ム Expired - Lifetime JPH061800B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59059455A JPH061800B2 (ja) 1984-03-29 1984-03-29 リ−ドフレ−ム

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59059455A JPH061800B2 (ja) 1984-03-29 1984-03-29 リ−ドフレ−ム

Publications (2)

Publication Number Publication Date
JPS60206053A true JPS60206053A (ja) 1985-10-17
JPH061800B2 JPH061800B2 (ja) 1994-01-05

Family

ID=13113791

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59059455A Expired - Lifetime JPH061800B2 (ja) 1984-03-29 1984-03-29 リ−ドフレ−ム

Country Status (1)

Country Link
JP (1) JPH061800B2 (ja)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02161711A (ja) * 1988-12-15 1990-06-21 Hitachi Cable Ltd セラミックコンデンサに半田接合される板状のリード線
FR2733354A1 (fr) * 1995-04-24 1996-10-25 Samsung Electronics Co Ltd Appareil de soudage de connexions interieures comportant un moyen de dissipation de chaleur, et procede de soudage utilisant cet appareil
WO2014136824A1 (ja) * 2013-03-05 2014-09-12 日亜化学工業株式会社 リードフレーム及び半導体装置
JP2014175321A (ja) * 2013-03-05 2014-09-22 Nichia Chem Ind Ltd リードフレーム及び発光装置

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02161711A (ja) * 1988-12-15 1990-06-21 Hitachi Cable Ltd セラミックコンデンサに半田接合される板状のリード線
FR2733354A1 (fr) * 1995-04-24 1996-10-25 Samsung Electronics Co Ltd Appareil de soudage de connexions interieures comportant un moyen de dissipation de chaleur, et procede de soudage utilisant cet appareil
WO2014136824A1 (ja) * 2013-03-05 2014-09-12 日亜化学工業株式会社 リードフレーム及び半導体装置
JP2014175321A (ja) * 2013-03-05 2014-09-22 Nichia Chem Ind Ltd リードフレーム及び発光装置
JPWO2014136824A1 (ja) * 2013-03-05 2017-02-16 日亜化学工業株式会社 リードフレーム及び半導体装置
US9748164B2 (en) 2013-03-05 2017-08-29 Nichia Corporation Semiconductor device
US9887335B2 (en) 2013-03-05 2018-02-06 Nichia Corporation Light emitting device including a resin package having a cavity
US10096758B2 (en) 2013-03-05 2018-10-09 Nichia Corporation Lead frame including a plurality of units connected together and semiconductor device including the lead frame

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