JPS60144957A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS60144957A
JPS60144957A JP59000164A JP16484A JPS60144957A JP S60144957 A JPS60144957 A JP S60144957A JP 59000164 A JP59000164 A JP 59000164A JP 16484 A JP16484 A JP 16484A JP S60144957 A JPS60144957 A JP S60144957A
Authority
JP
Japan
Prior art keywords
wiring
junction
protective film
bonding
corrosion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59000164A
Other languages
English (en)
Inventor
Isayuki Yoshioka
芳岡　勇行
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP59000164A priority Critical patent/JPS60144957A/ja
Publication of JPS60144957A publication Critical patent/JPS60144957A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49872—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials the conductive materials containing semiconductor material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05073—Single internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05551—Shape comprising apertures or cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05563—Only on parts of the surface of the internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔技術分野〕 本発明は特に半導体装置におけるいわゆるポンディング
パッド部の構造に関するものである。
〔発明の背景〕
半導体装置のチップの配線には一般にアルミニウムが用
いられているが、外部から浸入した水分により腐蝕する
という欠点がある０％に樹脂封止パッケージの耐湿性は
キャンケースやセラミ、クバ、ケージ品に比較して劣っ
ている。その為、アルミニウムの腐蝕を防止する為にチ
ップ表面に保護膜を施す方法がある。この保護膜にはＣ
ＶＤ法による酸化族、ポリイミド系樹脂等が用いられて
いる。
しかし、いずれＶ場合でもボンディング領域においては
、アルミニウムとボンディングワイヤを電気的に導通さ
せる為に保護膜はなく、アルミニウムは裏山されている
。従って、保護膜で被われた配線部分は腐蝕が生じなく
ても、ボンディング領域は保護されていない為に腐蝕さ
れ、断線による不良が生ずる。
〔発明の目的〕
不発明の目的は、ボンディング領域部の腐蝕による断線
不良を防止した半導体装置を提供することにある。
不発明による半導体装置は、ポンディングパッドとそれ
につながる引き出し配線の下部に高濃度の多結晶牛導体
層を形成し、保護膜に被われている部分および被われて
いない部分で、ポンディングパッドとそれにつながる引
き出し配線にコンタクトをとることを特徴とし、これに
よって、水分が侵入し保護膜に被われていない部分のア
ルミニウム腐蝕が生じても、ボンディングワイヤ下部の
アルミニウムから、高濃度ポリシリコンを経て。
保護膜に被われた部分にあるボンディングパッドもしく
は、それにつながる引き出し配縁との電気的導通が保た
れ、耐湿性を同上出来る。
以下に図面を用いて不発明の詳細な説明する。
〔従来技術〕
第１図（ａ）および（ｂ）は従来リボンディング領域部
の上面図と断面図である。ボンディング領域１以外の部
分は斜線で図示した保護膜２が施されていてボンディン
グ領域１から内部回路への配線３はその表面が保護膜２
で保護されている°。一方、ボンディング領域１はワイ
ヤー５との接続のために表面保護されていない、このた
め、水分や不純物イオンの作用で保護膜２が施されてい
る配線３よシも先にＡで示した部分、つまシボンテイン
グ領域１の中で、ワイヤ５がボンディングされる部分４
を除く領域が、金属間接触電位との関係も手伝りて腐蝕
する。この為にボンディングワイヤー５は島状に分離し
、配線３と電気的導通が得られなくなって断線不良とな
る。つまシ、保護膜２によシ配線３は保護されているに
もかかわらず、断線不良を発生するのであシ、保護膜２
による保護対策が充分には効果金現わしていない。
〔実施例〕
かかる欠点を防止するのが本発明であり、その一実施例
を第２図（ａ）、　（ｂ）に上面図と断面図とで示す、
すなわち、ポンディングパッド部１およびパッド引き出
し配＃３と絶縁膜６０間の層に高濃度ポリシリコン層７
ｔ−設ける。配線３と高濃度ポリシリコン層７の接触面
は全面的にコンタクトラとっている。よって、水分や不
純物の作用でＡでボした部分が腐蝕し、ボンディングワ
イヤー５が島状になっても、ポリシリコンの腐蝕は生じ
ていない、ボンディングワイヤー５から高濃度ポリシリ
コン層７ｔ−経由し、保護膜２で保護されている配線３
への電気的導通は保たれる。Ａで示した部分が腐蝕され
ても高濃度ポリシリコン層７の周囲のすぐ近傍に保護膜
２で被われた配ＷＭａを設け、コンタクトを広くとるこ
とにより、高濃度ポリシリコン層７の布線インピーダン
スが十分小さくなる構造にしている。
第３図は不発明の他の実施例である。これは。
ポリシリコン層７を酸化膜９で部分的におおったもので
ある。この例では、配線３と高濃度ポリシリコン層７と
のコンタクト部分８０面積が小さくなって、布線インピ
ーダンスが大きくなり、第２図に比べ特性悪化の度合は
大きくなるが、断線不良のような致命的不良には致らな
い。
なお配線にアルミニウムを用いた場合について説明した
が、他の物質による配線でもボンディング領域が他より
先に水分等で腐蝕する場合には、本発明に同様な効果が
あるのは当然である。
以上のように、不発明によれば、ボンディング領域部の
腐蝕による断線不良が防止され得る半導体装置を提供で
きる。
【図面の簡単な説明】
第１図（ａ）、　（ｂ）は夫々従来の半導体装置の特に
ボンディング領域部の一例を示す平面図および断面図、
第２図（ａ）、　（ｂ）は夫々不発明の一実施例を示す
平面図および断面図、第３図（ａ）、　（ｂ）は夫々他
の実施例を示す平面図および断面図である。 ｌ・・・・・・ボンディング領域、２・・・・・・保護
膜、３・・・・・・配線層、４・・・・・・ボンディン
グされる部分、５・・・・・・ボンティングワイヤー、
６・・・・・・絶縁層１．７・・・・・・高濃度ポリシ
リコン層、８・・・・・・配腺層−高濃度ポリシリコン
層コンタクト、９・・・・・・絶縁層。

Claims (1)

    【特許請求の範囲】
  1. ポンディングパッドとこれにつながる引き出し配線との
    下にこれらと接触して牛導体層が形成されていることを
    特徴とする半導体装置。
JP59000164A 1984-01-04 1984-01-04 半導体装置 Pending JPS60144957A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59000164A JPS60144957A (ja) 1984-01-04 1984-01-04 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59000164A JPS60144957A (ja) 1984-01-04 1984-01-04 半導体装置

Publications (1)

Publication Number Publication Date
JPS60144957A true JPS60144957A (ja) 1985-07-31

Family

ID=11466389

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59000164A Pending JPS60144957A (ja) 1984-01-04 1984-01-04 半導体装置

Country Status (1)

Country Link
JP (1) JPS60144957A (ja)

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