JPS60140725A - パタ−ン形成方法 - Google Patents

パタ−ン形成方法

Info

Publication number
JPS60140725A
JPS60140725A JP24528783A JP24528783A JPS60140725A JP S60140725 A JPS60140725 A JP S60140725A JP 24528783 A JP24528783 A JP 24528783A JP 24528783 A JP24528783 A JP 24528783A JP S60140725 A JPS60140725 A JP S60140725A
Authority
JP
Japan
Prior art keywords
pattern
mask
turn
layer
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP24528783A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0469418B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html
Inventor
Hiromichi Watanabe
渡辺　広道
Niwaji Majima
庭司 間島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP24528783A priority Critical patent/JPS60140725A/ja
Priority to CA000470553A priority patent/CA1260754A/en
Priority to DE8484402694T priority patent/DE3484677D1/de
Priority to EP84402694A priority patent/EP0147322B1/en
Priority to US06/686,521 priority patent/US4597826A/en
Publication of JPS60140725A publication Critical patent/JPS60140725A/ja
Publication of JPH0469418B2 publication Critical patent/JPH0469418B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F41/00—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties
    • H01F41/32—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for applying conductive, insulating or magnetic material on a magnetic film, specially adapted for a thin magnetic film
    • H01F41/34—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for applying conductive, insulating or magnetic material on a magnetic film, specially adapted for a thin magnetic film in patterns, e.g. by lithography
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0335—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Drying Of Semiconductors (AREA)
JP24528783A 1983-12-26 1983-12-28 パタ−ン形成方法 Granted JPS60140725A (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP24528783A JPS60140725A (ja) 1983-12-28 1983-12-28 パタ−ン形成方法
CA000470553A CA1260754A (en) 1983-12-26 1984-12-19 Method for forming patterns and apparatus used for carrying out the same
DE8484402694T DE3484677D1 (de) 1983-12-26 1984-12-21 Verfahren zum herstellen von einem muster mit feinen zwischenraeumen.
EP84402694A EP0147322B1 (en) 1983-12-26 1984-12-21 Method for forming a pattern having a fine gap.
US06/686,521 US4597826A (en) 1983-12-26 1984-12-26 Method for forming patterns

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24528783A JPS60140725A (ja) 1983-12-28 1983-12-28 パタ−ン形成方法

Publications (2)

Publication Number Publication Date
JPS60140725A true JPS60140725A (ja) 1985-07-25
JPH0469418B2 JPH0469418B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1992-11-06

Family

ID=17131417

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24528783A Granted JPS60140725A (ja) 1983-12-26 1983-12-28 パタ−ン形成方法

Country Status (1)

Country Link
JP (1) JPS60140725A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53105982A (en) * 1977-02-28 1978-09-14 Nec Corp Micropattern formation method
JPS58158928A (ja) * 1982-03-17 1983-09-21 Agency Of Ind Science & Technol 絶縁基板上半導体装置の製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53105982A (en) * 1977-02-28 1978-09-14 Nec Corp Micropattern formation method
JPS58158928A (ja) * 1982-03-17 1983-09-21 Agency Of Ind Science & Technol 絶縁基板上半導体装置の製造方法

Also Published As

Publication number Publication date
JPH0469418B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1992-11-06

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