JPS60140725A - Pattern forming method - Google Patents
Pattern forming methodInfo
- Publication number
- JPS60140725A JPS60140725A JP24528783A JP24528783A JPS60140725A JP S60140725 A JPS60140725 A JP S60140725A JP 24528783 A JP24528783 A JP 24528783A JP 24528783 A JP24528783 A JP 24528783A JP S60140725 A JPS60140725 A JP S60140725A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- layer
- mask
- film
- turn
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F41/00—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties
- H01F41/32—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for applying conductive, insulating or magnetic material on a magnetic film, specially adapted for a thin magnetic film
- H01F41/34—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for applying conductive, insulating or magnetic material on a magnetic film, specially adapted for a thin magnetic film in patterns, e.g. by lithography
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0335—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】 一発明の技術分野 本発明は、例えば磁気バブルメモリデバイス。[Detailed description of the invention] Technical field of invention The present invention relates to, for example, a magnetic bubble memory device.
半導体デバイス、表面弾性波デバイス、ジョセフソンデ
バイスなどのような各種デバイスの製作に適用される・
やターン形成方法に関し、特にパターンの断面形状を制
御可能とする方法に関するものである。Applied to the production of various devices such as semiconductor devices, surface acoustic wave devices, Josephson devices, etc.
The present invention relates to a turn forming method, and particularly to a method that allows control of the cross-sectional shape of a pattern.
技術の背景
上記のようなデバイスにおいては、その基板上に導体や
磁性体などからなるパターンが多層に重ねて形成される
ことが多い。この場合、上層ノやターンの切断などの不
良を防止するために、下層パターン形成後に樹脂などを
塗布して平坦化（７°レナー化）処理を行う必要がある
。しかし従来のパターン形成方法には後述するような問
題があり、パターンの平坦化処理が容易でなく、その対
策が課題となっている。Background of the Technology In devices such as those described above, patterns made of conductors, magnetic materials, etc. are often formed in multiple layers on the substrate. In this case, in order to prevent defects such as cutting of the upper layer or turns, it is necessary to apply a resin or the like after forming the lower layer pattern and perform a flattening process (7° lensing). However, the conventional pattern forming method has problems as described below, in which it is difficult to flatten the pattern, and countermeasures have been a challenge.
従来技術と問題点
従来のノやターン形成方法には一般にホ） ＩＪングラ
フィ技術が用いられ、まずＩ？パターン形成する材料の
層を基板表面上に形成し、次にこの／ぐターン材料層上
にホトリングラフィ技術を用いてホトレジスト材料によ
シマスクノクターンを形成し、しかる後にノやターン材
料層をエツチングしてノぐターンを形成するものである
。しかしこの方法では、・ぐタニン断面形状がエツチン
グ方法によって一義的に決定され、断面形状の制御を行
うことができない。このためノ４ターン断面形状はパタ
ーン側面が急峻な形状となり、パターン平坦化処理が容
易でない。Prior Art and Problems The conventional method for forming grooves and turns generally uses IJ printing technology, which first involves forming I? A layer of material to be patterned is formed on the surface of the substrate, and then a patterned nocturne is formed in the photoresist material using photolithographic techniques on the layer of material to be patterned, followed by a layer of patterned material. It is etched to form a groove. However, in this method, the cross-sectional shape of .gtanine is uniquely determined by the etching method, and the cross-sectional shape cannot be controlled. Therefore, the four-turn cross-sectional shape has a steep pattern side surface, making it difficult to flatten the pattern.
発明の目的
本発明は、上記従来技術に鑑み、Ａ？ターン平坦化を容
易に行うことができるようにパターン側面を緩やかにな
し得る如＜ツクターン断面形状を制御可能なパターン形
成方法を提供することを目的とするものである。Purpose of the Invention The present invention has been made in view of the above-mentioned prior art. It is an object of the present invention to provide a pattern forming method that can control the cross-sectional shape of a turn so that the side surfaces of the pattern can be made gentle so that the turn can be easily flattened.
発明の構成
本発明は、概略的には、加速粒子を利用するエツチング
技術、例えばイオンミリングによるエツチング技術にお
ける／４’ターン太シ効果を利用することによって上記
目的の達成を図ったものである。DESCRIPTION OF THE INVENTION The present invention generally aims to achieve the above object by utilizing the /4' turn thick effect in etching techniques using accelerated particles, such as etching techniques by ion milling.
すなわち、加速粒子によるエツチング技術では、被エツ
チング材料層から除去された材料の一部がマスクツ４タ
ーンや被エツチング材料層に再付着する現像があり、こ
のためにノ臂ターンが太るという効果がある。That is, in the etching technique using accelerated particles, there is a development in which a part of the material removed from the material layer to be etched re-attaches to the mask 4 turns and the material layer to be etched, and this has the effect of thickening the arm turns. .
すなわち本発明によるｉ４ターン形成方法は、まずパタ
ーンを形成する材料の層を基板表面上に形成し、該ノ９
ターン材料層上に前記被形成Ａ？パターンほぼ相当する
部分を被覆するマスクツリーンを形成し、次にパターン
材料層およびマスクパターンの露出表面上にエツチング
レートがマスク／４ターンの材料よシ大きな材料の被膜
をマスクツぐターンの起伏形状がほぼ維持される如く形
成し、しかる後に加速粒子を利用するエツチング技術を
用いて前記被膜及びＡ’ターン材料層をエツチングして
ノやターン材料層から前記ノ母ターンを形成し、そして
前記マスクパターンを除去するものである。That is, in the i4 turn forming method according to the present invention, a layer of a pattern-forming material is first formed on the substrate surface, and the
The formed material A? on the turn material layer? A mask tree is formed to cover a portion approximately corresponding to the pattern, and then a film of material having an etching rate higher than that of the material of the mask/4 turns is formed on the pattern material layer and the exposed surface of the mask pattern. is formed such that the A'-turn material layer is substantially maintained, and then etching the coating and the A'-turn material layer using an etching technique utilizing accelerated particles to form the A'-turn material layer from the A'-turn material layer; It removes patterns.
かかる方法によれば、エツチング工程中、被膜がエツチ
ング除去される段階で被膜材料がマスクパターンの側面
に再付着することによってエツチングレートの異なる異
種材料からなる２重構造の幅太のマスクツ母ターンが形
成されることに表るｇそして次のＡＩパターン料層のエ
ツチング段階では、マスクパターンの被膜材料層はエツ
チングレートがマスクツ母ターンよシも大きいことから
エツチング途中で除去され、そのため・母ターン材料層
は２段にエツチングされることになる。従って被膜の材
料及び膜厚を適宜選定することによってパターン断面形
状を制御し得る。According to this method, during the etching process, when the film is removed by etching, the film material re-adheres to the side surfaces of the mask pattern, resulting in a thick mother turn of the mask with a double structure made of different materials with different etching rates. In the etching step of the next AI pattern material layer, the film material layer of the mask pattern is removed during etching because the etching rate is higher than that of the mask mother turn material. The layer will be etched in two stages. Therefore, the cross-sectional shape of the pattern can be controlled by appropriately selecting the material and thickness of the coating.
発明の実施例
以下、本発明の実施例につき図面を参照して詳細に説明
する。Embodiments of the Invention Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
第１図から第５図は本発明方法によって磁気バブルメモ
リデバイスの７４−マロイノ々プル転送パターンを形成
する場合の主要工程を示す。図中、符号１は、非磁性ガ
ーネット（ガドリニウム・ガリウム・ガーネット）の基
板にバブル移動層である磁性ガーネット薄膜を形成し、
更に５ｉ０２や樹脂などの絶縁層を介してコンダクタ／
母ターンヲ、ソの上にまたｓ ｔｏ２や樹脂などの絶縁
層を形成したものであシ、以下これを総括して単に「基
板」と称する。基板１上へのパーマロイパターンの形成
工程は以下の如くである。1 to 5 illustrate the main steps in forming a 74-malloinople transfer pattern of a magnetic bubble memory device according to the method of the present invention. In the figure, reference numeral 1 indicates that a magnetic garnet thin film, which is a bubble moving layer, is formed on a non-magnetic garnet (gadolinium gallium garnet) substrate.
Furthermore, the conductor/
An insulating layer such as sto2 or resin is formed on the mother turns 1 and 2, and hereinafter these will be collectively referred to simply as a "substrate." The process of forming a permalloy pattern on the substrate 1 is as follows.
α）まず第１図に示すように、基板ｌ上に７４タ一ン材
料層であるパーマロイ（ＮｉＦｅ ）の層Ａを蒸着によ
シ膜厚３０００Ｘで形成する。そしてこのパーマロイ層
Ａ上に、ホトリソグラフィ技術によシ例えばｒ Ａ Ｚ
１３５０ Ｊ ｊ （５ｈｉｐｌｅｙ社）などのポジ
型ホトレゾスト材料からマスクツクターンＢを膜厚７０
００Ｘで形成する。更に％バーマロイ層Ａ及びマスクパ
ターンＢの露出表面上に被膜（４−マスクパターンＢの
起伏形状がほぼ維持される如く形成する。被膜Ｃは、マ
スクパターンＢの材料よシもエツチングレートの大きい
材料、例えばＡｕ ｓ Ｃｕ 、 ＮｉＦｅ （〕ｅ
−−ｒ ａイ）などを用い、蒸着またはスノ’？ ツタ
リングによって形成する。尚、蒸着による場合は、マス
クパターンＢの変形ヲ防ぐために低＠（例えば１５０℃
以下）に維持することが望ましい。本実施例では被膜Ｃ
をＡｕで２０００１の膜厚に形成した。α) First, as shown in FIG. 1, a layer A of permalloy (NiFe), which is a 74 tan material layer, is formed by vapor deposition to a thickness of 3000× on a substrate I. Then, on this permalloy layer A, for example r A Z
1350 J j (5hipley) or other positive photoresist material to a film thickness of 70 mm.
Formed with 00X. Further, a coating (4) is formed on the exposed surfaces of the Vermalloy layer A and the mask pattern B so that the undulating shape of the mask pattern B is almost maintained.The coating C is made of a material having a higher etching rate than the material of the mask pattern B. , for example, AusCu, NiFe(]e
--r a), etc., by vapor deposition or snow'? Formed by ivy. In addition, in the case of vapor deposition, the temperature is low (for example, 150°C) to prevent deformation of the mask pattern B.
(below) is desirable. In this example, the coating C
was formed with Au to a thickness of 20,001 mm.
（２）次に、例えばＮｅ 、 Ａｒ ＋ Ｘｓ等の不活
性ガスを用いたイオンミリングによって被膜Ｃ及びノや
−マロイ層ＡＩＤｆ：ッテングを行う。この場合、第２
図に示すようにパーマロイ層Ａの表面上の被膜Ｃが除去
されてパーマロイ層Ａの表面が露出した段階では、被膜
Ｃの材料（Ａｕ ）がマスクツクターンＢの側面に符号
Ｃ′で示す如く再付着し、従ってエツチングレートの異
なるレジスト／９ターンＢと被膜材料層Ｃ′とからなる
２重構造の幅太なマスクパターンが形成されることにな
る。(2) Next, the coating C and the malloy layer AIDf are etched by ion milling using an inert gas such as Ne or Ar + Xs. In this case, the second
As shown in the figure, at the stage where the coating C on the surface of the permalloy layer A is removed and the surface of the permalloy layer A is exposed, the material (Au) of the coating C is coated on the side surface of the mask turn B as shown by the symbol C'. As a result, a thick mask pattern with a double structure consisting of the resist/9 turns B and the coating material layer C' having different etching rates is formed.
（３）更にイオンミリングを行うと、パーマロイ。(3) Further ion milling produces permalloy.
Ａｕ 、ホトレジストのエツチングレートの比は加速粒
子としてＡｒを用い且つ基板法線に対する加速粒子の入
射角度をＯｏとした場合に１，３〜４゜ｌであるため、
被膜材料層Ｃ’（Ａｕ）は４−マロイ層Ａおよびマスク
・母ターンＢよりも速くエツチングされ、エツチングの
途中段階で第３図に示すような状態となる。Since the etching rate ratio of Au and photoresist is 1.3 to 4°l when Ar is used as the accelerated particle and the incident angle of the accelerated particle with respect to the normal to the substrate is Oo,
The coating material layer C' (Au) is etched faster than the 4-malloy layer A and the mask/mother turn B, and reaches the state shown in FIG. 3 in the middle of the etching process.
（４）引ぎ続きイオンミリングを行うと第４図に示す状
態となってバーマロイノｆターンＡＰが形成され、マス
クパターンＢを除去すると第５図に示す状態となる。(4) If ion milling is subsequently performed, the state shown in FIG. 4 will be obtained, and a vermaloino f-turn AP will be formed, and when the mask pattern B is removed, the state shown in FIG. 5 will be obtained.
以上から明らかなように、パターンＡＰの断面形状は、
パターン側面が被膜材料層Ｃ′をマスクとしてエツチン
グされた部分Ａ１と、レジストパターンＢをマスクとし
てエツチングされた部分Ａ２とからなる２段構造となる
。かかるノ臂ターンＡＰの断面形状は、被膜Ｃを形成せ
ずにレジストノやターンＢのみをマスクとしてエツチン
グした場合のパターン断面形状ＡＰ’（点線で示す）に
比較し、部分Ａｌの分だけパターン幅が太く且つ２段状
になっていて傾きが緩やかなものとなる。従って、樹脂
などの塗布による平坦化が容易となる。As is clear from the above, the cross-sectional shape of pattern AP is
The side surface of the pattern has a two-stage structure consisting of a portion A1 etched using the coating material layer C' as a mask and a portion A2 etched using the resist pattern B as a mask. The cross-sectional shape of the arm turn AP is compared to the pattern cross-sectional shape AP' (indicated by a dotted line) when etching is performed using only the resist layer and the turn B as a mask without forming the film C, and the pattern width is reduced by the portion of Al. is thick and has a two-step shape, and has a gentle slope. Therefore, flattening by applying resin or the like becomes easy.
Ａ？ターン側面の傾き角は、被膜Ｃの材料（っまシはエ
ツチングレート）及び膜厚ならびにエツチング時の基板
法線に対する入射角によって変わる。A? The angle of inclination of the side surface of the turn varies depending on the material (the etching rate) and film thickness of the coating C, as well as the angle of incidence relative to the normal to the substrate during etching.
−例として、被膜Ｃをパーマロイで２０００Ｘの厚さに
形成し、加速粒子を基板法線に対し斜めに入射させた場
合、従来方法では６０〜６５度程度であった／４’ター
ン側面の傾きを４５〜５０度程度緩やかにすることがで
きる。- As an example, when coating C is formed with permalloy to a thickness of 2000X and the accelerated particles are incident obliquely to the normal line of the substrate, the inclination of the side surface of the /4' turn was about 60 to 65 degrees in the conventional method. can be made gentler by about 45 to 50 degrees.
発明の効果
以上のように本発明によれば、マスクツリーン上に被膜
を形成し且つ加速粒子を利用するエツチング技術を用い
ることによってパターン断面形状を制御できるノｆター
ン形成方法が得られ、かがる方法を適用することにより
ｓターン側面の傾斜が緩やかで平坦化処理の容易なノぐ
ターンを形成できるので、磁気バブルメモリデバイスな
どの各種デバイスの信頼性向上を図ることが可能となる
。Effects of the Invention As described above, according to the present invention, a no-f turn forming method is provided in which the cross-sectional shape of a pattern can be controlled by forming a film on a mask tree and using an etching technique that utilizes accelerated particles. By applying the s-turn method, it is possible to form a nog turn with a gentle slope of the s-turn side surface and easy flattening, thereby making it possible to improve the reliability of various devices such as magnetic bubble memory devices.
尚、上記実施例ではノ４−マロイノ？ターン形成につい
て述べたが、バブルメモリのコンダクタパターン形成に
も等しく適用可能である。In addition, in the above example, No4-Maroino? Although turn formation has been described, it is equally applicable to conductor pattern formation for bubble memories.
第１図から第５図は本発明のパターン形成方法の一実施
例の主要工程を示す図である。
１・・・基板、Ａ・・りやターン材料層、Ｂ・・・マス
ク・臂ターフ、Ｃ・・・被膜、ＡＰ・・・パターン。
特許出願人
富士通株式会社
特許出願代理人
弁理士 青 木 朗
弁理士西舘和之
弁理士 内 １）幸 男
弁理士 山 口 昭 之
第１図
１１Ｊ！ＪＪＪ
第３図
第４図1 to 5 are diagrams showing the main steps of an embodiment of the pattern forming method of the present invention. 1...Substrate, A...Riya turn material layer, B...mask/arm turf, C...coat, AP...pattern. Patent applicant Fujitsu Limited Patent agent Akira Aoki Patent attorney Kazuyuki Nishidate Patent attorney 1) Yukio Patent attorney Akira Yamaguchi Figure 1 11J! JJJ Figure 3 Figure 4
Claims (1)
、 （イ）前記ツクターン形成材料の層（Ａ）を基板表面上
に形成し、 ←）該パターン材料層（４）上に前記被形成パターンに
ほぼ相当する部分を被覆するマスクパターン（Ｂ）を形
成し、 ＋Ｓ パターン材料層（５）およびマスクパターン（Ｂ
）の露出表面上にエツチングレートがマスクパターン（
Ｂ）の材料よシ大きな材料の被膜（Ｃ）をマスクツ４タ
ーンの起伏形状がほぼ維持される如く形成し、に）加速
粒子を利用するエツチング技術を用いて前記被膜（Ｃ）
及びパターン材料層（４）をエツチングしてノｊターン
材料層（５）から前記パターン（ＡＰ）を形成し、そし
て （ホ）前記マスクツ４ターン（Ｂ）を除去する、ことを
特徴とするパターン形成方法。 ２、特許請求の範囲第１項記載のパターン形成方法にお
いて、前記マスクパターン（Ｂ）をホトリソグラフィ技
術によシホトレジスト材料から形成するパターン形成方
法。 ３、特許請求の範囲第１項記載のパターン形成方法にお
いて、前記加速粒子を利用するエツチング技術としてイ
オンミリング技術を用いるノやターン形成方法。 ４、特許請求の範囲第１項記載のパターン形成方法にお
いて、前記加速粒子源として不活性ガスを用いるパター
ン形成方法。[Scope of Claims] 1. A method of forming a pattern of a material forming a substrate, comprising: (a) forming the layer (A) of the pattern-forming material on the surface of the substrate; ), a mask pattern (B) covering a portion substantially corresponding to the pattern to be formed is formed on the +S pattern material layer (5) and the mask pattern (B).
) on the exposed surface of the mask pattern (
A film (C) made of a material larger than the material of B) is formed so that the undulating shape of the four turns of the mask is substantially maintained, and (B) the film (C) is formed using an etching technique using accelerated particles.
and etching the pattern material layer (4) to form the pattern (AP) from the no-j turn material layer (5), and (e) removing the mask 4 turns (B). Formation method. 2. The pattern forming method according to claim 1, wherein the mask pattern (B) is formed from a photoresist material by photolithography. 3. A pattern forming method according to claim 1, in which an ion milling technique is used as the etching technique using the accelerated particles. 4. A pattern forming method according to claim 1, in which an inert gas is used as the accelerated particle source.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24528783A JPS60140725A (en) | 1983-12-28 | 1983-12-28 | Pattern forming method |
| CA000470553A CA1260754A (en) | 1983-12-26 | 1984-12-19 | Method for forming patterns and apparatus used for carrying out the same |
| EP84402694A EP0147322B1 (en) | 1983-12-26 | 1984-12-21 | Method for forming a pattern having a fine gap. |
| DE8484402694T DE3484677D1 (en) | 1983-12-26 | 1984-12-21 | METHOD FOR PRODUCING A PATTERN WITH FINE SPACES. |
| US06/686,521 US4597826A (en) | 1983-12-26 | 1984-12-26 | Method for forming patterns |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24528783A JPS60140725A (en) | 1983-12-28 | 1983-12-28 | Pattern forming method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60140725A true JPS60140725A (en) | 1985-07-25 |
| JPH0469418B2 JPH0469418B2 (en) | 1992-11-06 |
Family
ID=17131417
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24528783A Granted JPS60140725A (en) | 1983-12-26 | 1983-12-28 | Pattern forming method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60140725A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53105982A (en) * | 1977-02-28 | 1978-09-14 | Nec Corp | Micropattern formation method |
| JPS58158928A (en) * | 1982-03-17 | 1983-09-21 | Agency Of Ind Science & Technol | Manufacture of semiconductor device on insulating substrate |
-
1983
- 1983-12-28 JP JP24528783A patent/JPS60140725A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53105982A (en) * | 1977-02-28 | 1978-09-14 | Nec Corp | Micropattern formation method |
| JPS58158928A (en) * | 1982-03-17 | 1983-09-21 | Agency Of Ind Science & Technol | Manufacture of semiconductor device on insulating substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0469418B2 (en) | 1992-11-06 |
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