JPS58158928A - Manufacture of semiconductor device on insulating substrate - Google Patents
Manufacture of semiconductor device on insulating substrateInfo
- Publication number
- JPS58158928A JPS58158928A JP4088982A JP4088982A JPS58158928A JP S58158928 A JPS58158928 A JP S58158928A JP 4088982 A JP4088982 A JP 4088982A JP 4088982 A JP4088982 A JP 4088982A JP S58158928 A JPS58158928 A JP S58158928A
- Authority
- JP
- Japan
- Prior art keywords
- island
- resist
- sio2
- film
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 239000000758 substrate Substances 0.000 title claims abstract description 10
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 238000005530 etching Methods 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims abstract description 7
- 239000000463 material Substances 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 2
- 239000004020 conductor Substances 0.000 claims 1
- 230000001590 oxidative effect Effects 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 11
- 229910052594 sapphire Inorganic materials 0.000 abstract description 6
- 239000010980 sapphire Substances 0.000 abstract description 6
- LDDQLRUQCUTJBB-UHFFFAOYSA-N ammonium fluoride Chemical compound [NH4+].[F-] LDDQLRUQCUTJBB-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052681 coesite Inorganic materials 0.000 abstract 5
- 229910052906 cristobalite Inorganic materials 0.000 abstract 5
- 239000000377 silicon dioxide Substances 0.000 abstract 5
- 235000012239 silicon dioxide Nutrition 0.000 abstract 5
- 229910052682 stishovite Inorganic materials 0.000 abstract 5
- 229910052905 tridymite Inorganic materials 0.000 abstract 5
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000005056 compaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000005022 packaging material Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229920003229 poly(methyl methacrylate) Polymers 0.000 description 1
- 239000004926 polymethyl methacrylate Substances 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 239000011029 spinel Substances 0.000 description 1
- 229910052596 spinel Inorganic materials 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Weting (AREA)
Abstract
Description
【発明の詳細な説明】 〈発明の分野〉 本発明は、絶縁基板上半導体装置の製造方法に関する。[Detailed description of the invention] <Field of invention> The present invention relates to a method of manufacturing a semiconductor device on an insulating substrate.
〈従来技術〉
（ＩＥ、シリコン・オンのサファイア半導体装置に於い
て高耐圧化を図るため、窒化膜と裏面露光法を用い九製
造方法が、特開昭５６−６１１６８号公報により知られ
ている。<Prior art> (IE, 9 manufacturing methods using a nitride film and back exposure method in order to achieve high breakdown voltage in silicon-on sapphire semiconductor devices are known from Japanese Patent Laid-Open No. 56-61168. .
〈従来技術の間聴点〉
この従来技術においては、８ｉ島＠面は酸化膜とともに
、それ以上大きい誘電率をもつ窒化膜で覆われるため、
側面の寄生トランジスタの好ましくない影響が大きくな
る事、窒化ＩＩＩ／酸化膜の二重層構造に起因するスト
レスが発生する事、を九、窒化膜／酸化膜の二重層のパ
ターニシグは、８１島裏面からの露光を用いる丸め、同
公報図面中の例えばＦｉｇ、３ｇ図でも明らかなよう罠
、光の１ｇｌり込みにより、島鄭上面へはみ出して８１
Ｎが形成され、実際にＳｌ島上ＩＩ全面の利用が不可能
と凍り、素子の４微細化にとって障害となる。<Intermediate point of the prior art> In this prior art, the 8i island@plane is covered with an oxide film as well as a nitride film with an even larger dielectric constant.
The undesirable effects of parasitic transistors on the side surfaces will increase, and stress due to the double layer structure of nitride III/oxide film will occur. As is clear from the drawings in the publication, for example, Fig. 3g, the trap, 1 gl of light penetrates and protrudes onto the upper surface of Shimazheng.
N is formed, making it impossible to actually utilize the entire surface of the Sl island II, which becomes an obstacle to the miniaturization of elements.
〈発明の目的ン
本発明は、前項の欠点を除去でき、良好なゲート耐圧を
得ることができ、しかも高速化に向いた８Ｏ８のＨ１微
細化に適し丸製造方法を提供するととを目的としている
。<Purpose of the Invention> The present invention aims to provide a round manufacturing method that can eliminate the drawbacks mentioned above, can obtain a good gate breakdown voltage, and is suitable for H1 miniaturization of 8O8, which is suitable for higher speeds. .
〈発明の要点〉
絶轍基板上半導体装置の製造方法において、その素子分
離方法のうち、８ム島工ツチング方式の欠点であるＳ１
島すそで酸化膜厚が薄くな９、ゲート耐圧が低下すると
いう点を改善するため、８１島を熱酸化した優、ＣＶＤ
・８１０□ を堆積し、さらにレジス）（ＰＭＭＡ）を
塗布して、ａｔｇで平担部のレジストが除去されるまで
エツチングする。<Summary of the Invention> In a method for manufacturing a semiconductor device on an absolute substrate, among the device isolation methods, S1, which is a drawback of the 8-millimeter cutting method, has been solved.
In order to improve the problem that the oxide film thickness is thinner at the island base 9 and the gate withstand voltage is lowered, 81 islands were thermally oxidized using CVD.
・Deposit 810□, apply resist (PMMA), and etch with atg until the resist on the flat part is removed.
このとき、８１島すそでは、レジストが４＜塗布されて
いる丸め残存し、それをマスクとしてＮＦＩ４Ｆ等でｃ
ｖｎ−ｓム０２及び熱酸化膜をエツチングした浸、レジ
ストを除去する。その麦再びゲート酸化すると、Ｓｉ島
すそは厚い８ ＋ ０２ で覆われる状１１に＆Ｄ、
ゲート耐圧が改善される。しさも、この際Ｓｉ島上面が
１００％素子嬢域として活用出来るため、余裕度を兇積
る必要がなく集積度が上がる。At this time, at the base of the 81 island, a rounded portion of the resist coated with 4<4 remains, and this is used as a mask for curing with NFI4F, etc.
The vn-sm 02 and thermal oxide film are etched and the resist is removed. When the gate is oxidized again, the Si island base is covered with a thick 8 + 02 and becomes 11 &D,
Gate breakdown voltage is improved. In addition, since the upper surface of the Si island can be used 100% as an element storage area, there is no need to increase the margin, increasing the degree of integration.
〈発明の実施例ン Ｊｌ１図により１本発明の一３１！廁例を説明する。<Embodiments of the invention 131 of the present invention according to Jl1 diagram! Let me explain an example.
サファイア単結晶基ＷａＳ上に、シリコン層が設けられ
た例えば、 ｓ＋ ＜ １００ ＞ ／／ｕ２ｏ、 ＜
ｔｉｏｚ ＞の８ｉ１１厚０．６ ｓａｎのＳＯＳウ
ェー八にへいて、ＣＶＤ−８ｉ０．をマスクとしてシリ
コン（−を選択的に１例えばＫＯＨでエツチングし、８
ム島（至）を形成した。For example, a silicon layer is provided on a sapphire single crystal base WaS: s+ < 100 > //u2o, <
CVD-8i0. Using 1 as a mask, selectively etch silicon (- with 1, for example, KOH, and 8
The island of Mu was formed.
８１島側面はこのとき約６０度の傾斜をもっている０次
にドライ０２雰囲気中、１０００℃で約３０分酸化し、
第１の酸化膜を、第１図（１）に示す如く形成した。こ
れによつて厚さ約６００人の熱酸化膜（２０で８１島（
至）が覆われる。しかし、Ｓｉ島（至）のすそ即ち、側
面Ｙ部近傍（至）には、第１図（１）のように６０ＯＡ
よりも比較的薄い酸化膜しか形成されない。At this time, the side surface of island 81 was oxidized for about 30 minutes at 1000°C in a zero-order dry 02 atmosphere with an inclination of about 60 degrees.
A first oxide film was formed as shown in FIG. 1(1). This results in a thermal oxide film with a thickness of about 600 people (81 islands in 20
) is covered. However, as shown in Figure 1 (1), there is a 60OA
Only a relatively thin oxide film is formed.
次に例えば、ＣＶＤ法によって別０．＠を約１００ＯＡ
厚さで堆積し友後、マスク材料例えば、レジスト（ＰＭ
ＭＡ）Ｑ４をｌ ｐｍの厚さに、第１図（ｂ）の如く塗
布した。Next, for example, by CVD method, another 0. @ about 100OA
After depositing a thick layer of mask material, e.g. resist (PM
MA) Q4 was applied to a thickness of 1 pm as shown in Figure 1(b).
このとき８に島すそ領域（２）では、段差があるため、
レジストが平担部分即ち、島状上面、サファイア基板上
よ）厚く塗布される。この状態で、異方性エツチング例
えば１反応性イオンエツチング（ＲＩＥ）によってレジ
ストをエツチングし、平担部分のレジストを完全に除去
すると、第１図（ｃ）の如色構造が得られる。このとき
、エツチングゆ多少適正エツチング時間をオーバージて
も、８ｉ島すそにレジストが残存しておれば、本発明に
対しては充分である丸め、エツチング時間に対する余裕
度が充分にとれ１作業性が向上する。At this time, since there is a step in the island base area (2) at 8,
The resist is applied thickly to the flat areas (i.e., the top surface of the island, and the top of the sapphire substrate). In this state, the resist is etched by anisotropic etching, such as one-reactive ion etching (RIE), to completely remove the flat portion of the resist, resulting in the like-colored structure shown in FIG. 1(c). At this time, even if the etching exceeds the appropriate etching time, as long as the resist remains at the base of the 8i island, it is sufficient for the present invention. improves.
まえ、このときレジストの下地は、酸化膜であるため、
その下の８ｉ層へのＲＩＥによるダメージもない。次に
第１図（ｄ）のようにＮＨ４Ｆで露出しテイル酸化Ｈ（
ＣＶ Ｄ ８１０！＋２３、熱酸化’ｌ１ｍ） ）
ヲエッアング除去した。この段階で、Ｓｊ＠＠面の少な
くともシリコンとサファイアの接する部分近傍は、依然
として厚い熱酸化膜Ｑ１）、 ＣＶＤ−８ｉＯ□（至）
で覆われている。つづいて、レジメ） ＜１！４）を除
去した後、第１図（ｅ） Ｋ示す如くゲート酸化を行な
って所定のゲート酸化膜（ハ）を形成すればよい。この
場合、５００Ａのゲート稜化膜（至）を形成した。First, at this time, the base of the resist is an oxide film, so
There is no damage to the underlying 8i layer due to RIE. Next, as shown in Figure 1(d), it is exposed with NH4F and tail oxidized H (
CVD810! +23, thermal oxidation 'l1m))
Removed woetang. At this stage, at least the vicinity of the contact area between silicon and sapphire on the Sj@@ surface is still a thick thermal oxide film Q1), CVD-8iO□ (to)
covered with. Subsequently, after removing the pattern (regime) <1!4), gate oxidation is performed as shown in FIG. 1(e) K to form a predetermined gate oxide film (c). In this case, a gate edge-forming film (total) of 500A was formed.
〈発明の効果ン
本発明によると、まず、セルファラインで８ム島側面に
８４０．膜が形成でき、しかも、半導体島−上面全面が
１００％有効に活用出来るため、余デバイスのゲート配
線がこ・の上を遣った場合、段切れ等もなく、製造歩ｌ
Ｉ）が向上する。<Effects of the Invention> According to the present invention, first, the Selfa Line is installed on the side of the island at 840. In addition, the entire top surface of the semiconductor island can be used 100% effectively, so if the gate wiring of another device is placed over this area, there will be no disconnections and the manufacturing process will be shortened.
I) is improved.
勿論、島状物ａｍは、１！化膜のみで覆われ、余庁なス
トレス等も生じないため信頼性も鵬い。Of course, the island-like object am is 1! It is highly reliable because it is covered only with a chemical film and does not cause any additional stress.
更に、上＾己実ｍ例の如く１例えば８ｉ膜をＫＯＨ等の
異方性エツチングで島部形成すると、第２図に示すよう
に島状半導体層の肩部には、央起部が生じる場合が多い
ことが分つ九が、本発明の如く。Furthermore, if an island is formed on an 8i film by anisotropic etching using KOH or the like as in the example above, a central origin will appear at the shoulder of the island-shaped semiconductor layer, as shown in Figure 2. It turns out that there are many cases, such as in the present invention.
２度の酸化を行なうことで肩部は、なだらかな形状とな
プ、突起部は取り除かれる。これにより。By performing oxidation twice, the shoulders become gentle and smooth, and the protrusions are removed. Due to this.
−圧締状による信頼性低下も防ぐこと・が出来る。- It is possible to prevent a decrease in reliability due to compaction.
勿−１配線等の段切れ防止にも有効である。It is also effective in preventing disconnection of the -1 wiring, etc.
本発明はサファイアのみならず、スピネル、石英、ガラ
ス、Ｓ輸Ｎ４，８ＩＭＯＸ構造等の絶縁基板に対して有
効である。The present invention is effective not only for sapphire but also for insulating substrates such as spinel, quartz, glass, S-imported N4,8 IMOX structure, and the like.
第１図（ａ）〜（６）は、本発明の一実権例を説明する
ための工程断面図、第２図は、本発明の一実施例の効果
を説明するための断面図である。
図において、
１０・・・絶縁基板、 ２０・・・Ｓｉ島。
２３ ”・ＣＶ Ｄ Ｓ ＋Ｏｚ ３４ ”・Ｌ’
シＸ トｅ２５・・・ゲート酸化膜。FIGS. 1(a) to (6) are process cross-sectional views for explaining one practical example of the present invention, and FIG. 2 is a cross-sectional view for explaining the effects of one embodiment of the present invention. In the figure, 10...Insulating substrate, 20...Si island. 23"・CV D S +Oz 34"・L'
Sc.e25...Gate oxide film.
Claims (1)
島状半導体層表面を酸化し、第１の酸化膜を形成する工
程と、この全面上に第２の酸化膜層を堆積する工程と、
この全面にマスク材料膜を形成する工程と、このマスク
材料膜を異方性エツチングにより、前記島状半導体側面
にマスク材料が残存する如く除去する工程と、この残存
マスク材料をマスクとして、前記第１の酸化膜の島状半
導体層上ｒＭｓを、島状半導体層肩部まで除去する工程
とを具備してなることを特徴とする絶縁基板上手導体装
置の製造方法。A step of forming a semiconductor layer in an island shape on an insulating substrate, a step of oxidizing the surface of this island-shaped semiconductor layer to form a first oxide film, and depositing a second oxide film layer on the entire surface. process and
a step of forming a mask material film on the entire surface; a step of removing the mask material film by anisotropic etching so that the mask material remains on the side surface of the island-shaped semiconductor; 1. A method for manufacturing an insulating substrate top conductor device, comprising the step of removing rMs on the island-shaped semiconductor layer of the oxide film No. 1 up to the shoulder portion of the island-shaped semiconductor layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4088982A JPS58158928A (en) | 1982-03-17 | 1982-03-17 | Manufacture of semiconductor device on insulating substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4088982A JPS58158928A (en) | 1982-03-17 | 1982-03-17 | Manufacture of semiconductor device on insulating substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58158928A true JPS58158928A (en) | 1983-09-21 |
| JPH0313742B2 JPH0313742B2 (en) | 1991-02-25 |
Family
ID=12593076
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4088982A Granted JPS58158928A (en) | 1982-03-17 | 1982-03-17 | Manufacture of semiconductor device on insulating substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58158928A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60140725A (en) * | 1983-12-28 | 1985-07-25 | Fujitsu Ltd | Pattern forming method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5558374A (en) * | 1978-10-25 | 1980-05-01 | Hitachi Ltd | Etching method |
| JPS5715423A (en) * | 1980-07-01 | 1982-01-26 | Fujitsu Ltd | Manufacture of semiconductor device |
-
1982
- 1982-03-17 JP JP4088982A patent/JPS58158928A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5558374A (en) * | 1978-10-25 | 1980-05-01 | Hitachi Ltd | Etching method |
| JPS5715423A (en) * | 1980-07-01 | 1982-01-26 | Fujitsu Ltd | Manufacture of semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60140725A (en) * | 1983-12-28 | 1985-07-25 | Fujitsu Ltd | Pattern forming method |
| JPH0469418B2 (en) * | 1983-12-28 | 1992-11-06 | Fujitsu Ltd |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0313742B2 (en) | 1991-02-25 |
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