KR100244397B1 - Method of forming an element isolation region in a semiconductor device - Google Patents
Method of forming an element isolation region in a semiconductor device Download PDFInfo
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- KR100244397B1 KR100244397B1 KR1019930030780A KR930030780A KR100244397B1 KR 100244397 B1 KR100244397 B1 KR 100244397B1 KR 1019930030780 A KR1019930030780 A KR 1019930030780A KR 930030780 A KR930030780 A KR 930030780A KR 100244397 B1 KR100244397 B1 KR 100244397B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
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Abstract
본 발명은 반도체 소자 제조공정중 소자와 소자를 전기적으로 격리시키는 분리막 형성방법에 관한 것으로, 특히 반도체기판(1)을 열산화시켜 제 1 패드산화막(2)을 형성하고, 적층구조 절연막(10)을 형성하는 단계; 상기 적층구조 절연막(10)을 선택식각하여 제 1 패드산화막(2)을 소정부위 노출시키는 단계; 필드영역의 패드산화막(2)을 열산화시켜 두꺼운 제 2 패드 산화막(20)을 형성하는 단계; 전체구조 상부에 질화막(5)을 형성한 후, 상기 질화막(5), 적층구조 절연막(10)을 소정부위 스페이서 식각하여 질화막 스페이서(5')를 형성하는 단계; 필드산화막(6)을 형성하는 단계; 상기 잔류 적층구조 절연막(10)과 질화막스페이서(5') 및 패드산화막(2)을 제거하는 단계를 포함하여 이루어지는 것을 특징으로 함으로써 본 발명은 질화막스페이서를 사용할 경우 흔히 발생되는 스페이서에 의한 결정결함이 생기는 문제를 극복함으로써 접합 누설전류(junction leakage current)를 줄일 수 있고, 또한 필드산화막의 두께가 얇아지는 (field thinning) 현상을 방지하고, 부피비(volume ratio)도 증대시키는 효과를 얻을 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a separator that electrically isolates a device from a device in a semiconductor device manufacturing process. In particular, the semiconductor substrate 1 is thermally oxidized to form a first pad oxide film 2, and the laminated structure insulating film 10 Forming a; Selectively etching the multilayer insulating film 10 to expose a first pad oxide film 2 at a predetermined portion; Thermally oxidizing the pad oxide film 2 in the field region to form a thick second pad oxide film 20; Forming a nitride film spacer (5 ') by forming a nitride film (5) over the entire structure, and etching the spacer film (5) and the stacked structure insulating film (10) by a predetermined portion of the spacer; Forming a field oxide film 6; And removing the residual layered structure insulating film 10, the nitride film spacer 5 ', and the pad oxide film 2, and thus the present invention provides crystal defects caused by spacers that are commonly generated when the nitride film spacer is used. By overcoming the problem, the junction leakage current can be reduced, the field thinning of the field oxide film can be prevented, and the volume ratio can be increased.
Description
제1도는 종래 방법에 따른 필드산화막 형성 공정 단면도.1 is a cross-sectional view of a field oxide film forming process according to a conventional method.
제2도는 본 발명에 따른 일실시예의 필드산화막 형성 공정 단면도.Figure 2 is a cross-sectional view of the field oxide film formation process of an embodiment according to the present invention.
제3도는 본 발명의 다른 실시예에 따른 필드산화막 형성 공정 단면도.3 is a cross-sectional view of a field oxide film forming process according to another embodiment of the present invention.
〈도면의 주요부분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>
1 : 반도체 기판 2, 20 : 패드산화막1 semiconductor substrate 2, 20 pad oxide film
3, 5 : 질화막 4 : CVD산화막3, 5: nitride film 4: CVD oxide film
5' : 질화막스페이서 6 : 필드산화막5 ': nitride film spacer 6: field oxide film
10 : 적층구조 절연막10: laminated structure insulating film
본 발명은 반도체 소자 제조공정중 소자와 소자를 전기적으로 격리시키는 분리막 형성방법에 관한 것으로, 특히 질화막 스페이서를 이용하는 필드산화막 제조시 스페이서에 의한 스트레스를 감소시키는 반도체 소자의 분리막 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a separator that electrically isolates a device from a device during a semiconductor device manufacturing process. More particularly, the present invention relates to a method of forming a separator of a semiconductor device which reduces stress caused by a spacer in manufacturing a field oxide film using a nitride film spacer.
종래 LOCOS기술에서 주로 사용되는 필드산화막 형성 공정은 제 1 도에 도시되어 있는 바, 이를 참조하여 종래 기술을 개략적으로 설명하면 다음과 같다.The field oxide film forming process mainly used in the conventional LOCOS technology is illustrated in FIG. 1, and the prior art will be described with reference to the following.
참고로, 도면에서 부호 1은 반도체 기판, 2는 패드산화막, 3은 질화막, 5'은 스페이서 질화막, A는 결정결함 발생부위를 각각 나타낸다.For reference, 1 denotes a semiconductor substrate, 2 denotes a pad oxide film, 3 denotes a nitride film, 5 ′ denotes a spacer nitride film, and A denotes a crystal defect generating portion, respectively.
도면에 도시된 바와 같이 버즈빅(bird's beak) 형상의 길이를 감소시키기 위해 질화막 스페이서(nitride spacer, 5')를 사용하고 있으나, 다음과 같은 2가지 문제점이 따른다.As shown in the figure, a nitride spacer 5 'is used to reduce the length of a bird's beak shape. However, two problems follow.
첫째는 스페이서에 의해 필드산화막 형성시에 반도체기판의 소정 부위(제 1b 도의 A)에 결정결함을 유발시켜 접합누설전류가 증대하는 등 전기적 특성열화를 초래하게 된다.First, when the field oxide film is formed by the spacer, crystal defects are caused at predetermined portions (A in FIG. 1B) of the semiconductor substrate, resulting in deterioration of electrical characteristics such as an increase in the junction leakage current.
둘째는 스페이서에 의해 필드산화막이 형성될 공간이 좁아져서 필드산화막의 두께가 얇아지는(field thinning) 현상이 심화되며, 특히 반도체기판 아래로 형성되는 필드산화막의 깊이가 줄어들어 펀치스루(punch through) 특성이 열화되는 문제점이 따랐다.Second, the space where the field oxide film is formed by the spacer is narrowed, so that the thickness of the field oxide film is increased. In particular, the depth of the field oxide film formed under the semiconductor substrate is reduced so that the punch through characteristics are reduced. This deteriorating problem was followed.
따라서 상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은 질화막스페이서를 사용하더라도 필드산화막 형성시 기판에 발생되는 결정결함을 최소화 하는 반도체 소자의 분리막 형성방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of forming a separator of a semiconductor device which minimizes crystal defects generated in a substrate when forming a field oxide film even when a nitride film spacer is used.
상기 목적을 달성하기 위하여 본 발명은 반도체 소자의 분리막 형성방법에 있어서, 반도체기판을 열산화시켜 제 1 패드산화막을 형성하고, 적층구조 절연막을 형성하는 단계; 상기 적층구조 절연막을 선택식각하여 제 1 패드산화막을 소정부위 노출시키는 단계; 필드영역의 패드산화막을 열산화시켜 두꺼운 제 2 패드 산화막을 형성하는 단계; 전체구조 상부에 질화막을 형성한 후, 상기 질화막, 적층구조 절연막을 소정부위 스페이서 식각하여 질화막 스페이서를 형성하는 단계; 필드산화막을 형성하는 단계; 상기 잔류 적층구조 절연막과 질화막스페이서 및 패드산화막을 제거하는 단계를 포함하여 이루어지는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a method for forming a separator of a semiconductor device, comprising: thermally oxidizing a semiconductor substrate to form a first pad oxide film, and forming a laminated structure insulating film; Selectively etching the multilayer insulating film to expose a first pad oxide film at a predetermined portion; Thermally oxidizing the pad oxide film in the field region to form a thick second pad oxide film; Forming a nitride film spacer by forming a nitride film on the entire structure, and etching the nitride film and the stacked structure insulating film by a predetermined portion of the spacer; Forming a field oxide film; And removing the residual stacked structure insulating film, the nitride film spacer, and the pad oxide film.
이하, 첨부된 도면을 참조하여 본 발명을 상술한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
본 발명은 반도체 기판에 발생되는 결정결함을 최소화 하기 위해, 질화막스페이서를 형성하기 전에 필드영역의 패드산화막 두께를 산화에 의해 증가시켜 이 산화막이 질화막의 스트레스를 완충하도록한 기술이다.In order to minimize crystal defects generated in the semiconductor substrate, the thickness of the pad oxide film in the field region is increased by oxidation before forming the nitride film spacer so that the oxide film buffers the stress of the nitride film.
또한, 질화막스페이서를 마스크로 해서 두꺼워진 패드산화막을 일부 또는 전부 식각한 후 필드산화막을 형성함으로써 필드산화막의 두께가 얇아지는 현상을 방지하고 동시에 실리콘 기판 아래로 성장한 필드산화막의 부피 비율을 나타내는 이른바 부피비(volume ratio)를 증대시킨다.In addition, by forming a field oxide film after etching part or all of the thickened pad oxide film using a nitride film spacer as a mask, the thickness of the field oxide film is prevented from being thin and at the same time, the volume ratio of the field oxide film grown under the silicon substrate is expressed. Increase the volume ratio.
그러면, 상기 기술을 구현하는 공정방법을 제 2 도 및 제 3 도를 통하여 구체적으로 살펴보자.Next, a process method of implementing the technique will be described in detail with reference to FIGS. 2 and 3.
우선, 제 2a 도 내지 제 2g 도는 본 발명의 일실시예에 따른 필드산화막 형성 공정 단면도이다.First, FIGS. 2A to 2G are cross-sectional views of a field oxide film forming process according to an embodiment of the present invention.
먼저, 제 2a 도는 반도체기판(1)을 열적으로 산화시켜 패드산화막(2)을 50 내지 200Å 형성한 후, 질화막(3)을 1500 내지 3000Å, CVD 산화막(4)을 500 내지 1000Å 차례로 형성한 상태의 단면도이다.First, the semiconductor substrate 1 is thermally oxidized to form the pad oxide film 2 at 50 to 200 microseconds, and then the nitride film 3 is formed at 1500 to 3000 microns and the CVD oxide film 4 is formed at 500 to 1000 microseconds. It is a cross section of.
제 2b 도는 마스크를 이용하여 상기 CVD산화막(4)과 질화막(3)을 이방성 식각해서 패드산화막(2)을 노출시킨 상태의 단면도이다.2B is a cross-sectional view of the CVD oxide film 4 and the nitride film 3 being anisotropically etched using a mask to expose the pad oxide film 2.
제 2c 도는 필드영역의 패드산화막(2)이 500 내지 1500Å으로 두껍게 되도록 열산화시켜 두꺼운 제 2 패드 산화막(20)을 형성한 상태의 단면도이다.FIG. 2C is a cross-sectional view of a state in which a thick second pad oxide film 20 is formed by thermally oxidizing the pad oxide film 2 in the field region to a thickness of 500 to 1500 kPa.
제 2d 도는 전체구조 상부에 질화막(5)을 300 내지 1000Å 증착한 상태의 단면도이다.FIG. 2D is a cross-sectional view of the nitride film 5 deposited at 300 to 1000 300 on the entire structure.
제 2e 도는 마스크 없이 상기 질화막(5), CVD산화막(4)을 스페이서 식각하여 질화막 스페이서(5')를 형성한 상태의 단면도이다. 이때, CVD산화막(4)은 스페이서 식각시 제거됨으로서 질화막(3)의 손실을 방지하게 된다.FIG. 2E is a cross-sectional view of the nitride film spacer 5 'formed by spacer etching the nitride film 5 and the CVD oxide film 4 without a mask. At this time, the CVD oxide film 4 is removed during the etching of the spacer, thereby preventing the loss of the nitride film 3.
제 2f 도는 필드산화막(6)을 형성한 상태의 단면도이다. 이때, 제 2 패드 산화막(20)이 두껍기 때문에 질화막스페이서(5')의 스트레스를 완충하여 질화막스페이서 아래의 기판영역(A)에 결정결함이 생기지 않는다.2F is a cross-sectional view of a state in which a field oxide film 6 is formed. At this time, since the second pad oxide film 20 is thick, the stress of the nitride film spacer 5 'is buffered to prevent crystal defects in the substrate region A under the nitride film spacer.
끝으로, 제 2g 도는 상기 질화막(3)과 질화막스페이서(5') 및 패드산화막(2)을 습식식각으로 제거하여 최종 필드산화막(6)을 얻은 단면도이다.2G is a cross-sectional view of the final field oxide film 6 obtained by wet etching the nitride film 3, the nitride film spacer 5 'and the pad oxide film 2 by wet etching.
이어서, 제 3a 도 내지 제 3c 도는 본 발명의 다른 실시예에 따른 공정 단면도이다.3A to 3C are cross-sectional views of a process according to another embodiment of the present invention.
제 3a 도는 상기 제 2d 도의 공정까지 완료 후, 제 2 패드 산화막(20)의 중간위치까지 건식식각한 상태의 단면도이다. 이때, 3a' 도 처럼 반도체기판(1)이 노출될때까지 제 2 패드산화막(20)을 식각할 수도 있다.3A is a cross-sectional view of a state in which dry etching is performed to the intermediate position of the second pad oxide film 20 after completion of the process of FIG. In this case, the second pad oxide layer 20 may be etched until the semiconductor substrate 1 is exposed as shown in 3a '.
계속해서, 제 3b 도에서와 같이 필드산화막(6)을 형성하고, 제 3c 도에 도시된 바와 같이 상기 질화막(3), 질화막스페이서(5'), 패드산화막(2)을 습식으로 제거한 후 최종필드산화막(6)을 얻는다.Subsequently, as shown in FIG. 3B, the field oxide film 6 is formed, and as shown in FIG. 3C, the nitride film 3, the nitride film spacer 5 ', and the pad oxide film 2 are wet-removed, and finally, The field oxide film 6 is obtained.
상기와 같이 이루어지는 본 발명은 질화막스페이서를 사용할 경우 흔히 발생되는 스페이서에 의한 결정결합이 생기는 문제를 극복함으로써 접합 누설전류(junction leakage current)를 줄일 수 있고, 또한 필드산화막의 두께가 얇아지는 (field thinning) 현상을 방지하고, 부피비(volume ratio)도 증대시키는 효과를 얻을 수 있다.According to the present invention, the junction leakage current can be reduced and the thickness of the field oxide film can be reduced by overcoming the problem of crystal coupling caused by spacers, which are often generated when the nitride film spacer is used. ) Effect can be prevented and the volume ratio is also increased.
Claims (5)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930030780A KR100244397B1 (en) | 1993-12-29 | 1993-12-29 | Method of forming an element isolation region in a semiconductor device |
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| KR1019930030780A KR100244397B1 (en) | 1993-12-29 | 1993-12-29 | Method of forming an element isolation region in a semiconductor device |
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| KR950021374A KR950021374A (en) | 1995-07-26 |
| KR100244397B1 true KR100244397B1 (en) | 2000-03-02 |
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