JPS60132355A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS60132355A JPS60132355A JP24121883A JP24121883A JPS60132355A JP S60132355 A JPS60132355 A JP S60132355A JP 24121883 A JP24121883 A JP 24121883A JP 24121883 A JP24121883 A JP 24121883A JP S60132355 A JPS60132355 A JP S60132355A
- Authority
- JP
- Japan
- Prior art keywords
- region
- resistor
- type
- transistor
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 7
- 239000010410 layer Substances 0.000 abstract description 25
- 239000002344 surface layer Substances 0.000 abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract description 4
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 2
- 239000000377 silicon dioxide Substances 0.000 abstract description 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 108091006146 Channels Proteins 0.000 description 8
- 238000010586 diagram Methods 0.000 description 5
- 238000002955 isolation Methods 0.000 description 2
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Bipolar Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は、電圧スイッチング回路等に用いられる半導体
装置に関する。DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a semiconductor device used in voltage switching circuits and the like.
く口〉 従来技術
従来の電圧スイッチング回路を備えたパワーアンプに用
いられる過電圧保護回路としては、第５図に示すような
ものがある。３個のトランジスタ（Ｔｒｉ）（Ｔｒ２＞
（Ｔｒ３）と５個の抵抗（Ｒ１）−＝＜Ｒ５）とで電、
圧スイッチング回路（２０）を構成する。そして、この
スイッチング回路（２０〉の動作により、ドライバトラ
ンジスタ（Ｔｒ４＞を制御し、スピーカ等に信号を出力
する出力トランジスタ（Ｔｒｙ）を動作せしめ、過電圧
に対して装置を保護するものである。すなわち、電源電
圧（Ｖｃｃ）が、所定電圧値より上昇すると、抵抗（ｉ
３）および抵抗（Ｒ４）に流れる電流が所定値を越え、
そのため、抵抗（Ｒ４）の両端にかかる電圧が閾値電圧
より上昇し、トランジスタ（Ｔｒ２）がＯＮする。トラ
ンジスタ（Ｔｒ２）がＯＮすると、抵抗（Ｒ５）に電流
が流れ、その両端の電位差が大きくなりトランジスタ（
Ｔｒｉ）のベースにバイアスがかかり、トランジスタ（
Ｔｒｉ）がＯＮする。トランジスタ（Ｔｒｉ）がＯＮす
ることにより、抵抗（Ｒ２〉に電流が流れ、その両端に
電位差が生じ、トランジスタ（Ｔｒ３）がＯＮする。ト
ランジスタ（Ｔｒ３）がＯＮすると、ドライバトランジ
スタ（Ｔｒ４）のベースが接地し、ドライバＩ・ランジ
スタ（Ｔｒ４）を強制的にＯＦＦさせ、出力トランジス
タ（Ｔｒ５）のベース電流の供給を停止せしめ、出力ト
ランジスタ（Ｔｒ５）がＯＦＦするように構成されてい
る。Prior Art An overvoltage protection circuit used in a power amplifier equipped with a conventional voltage switching circuit is shown in FIG. Three transistors (Tri) (Tr2>
(Tr3) and five resistors (R1)-=<R5),
A pressure switching circuit (20) is configured. The operation of this switching circuit (20) controls the driver transistor (Tr4), operates the output transistor (Try) that outputs a signal to a speaker, etc., and protects the device against overvoltage. , when the power supply voltage (Vcc) rises above a predetermined voltage value, the resistance (i
3) and the current flowing through the resistor (R4) exceeds a predetermined value,
Therefore, the voltage applied across the resistor (R4) rises above the threshold voltage, and the transistor (Tr2) turns on. When the transistor (Tr2) is turned on, current flows through the resistor (R5), and the potential difference between both ends of the resistor (R5) increases, causing the transistor (Tr2) to turn on.
A bias is applied to the base of the transistor (Tri), and the transistor (
Tri) is turned on. When the transistor (Tri) turns on, a current flows through the resistor (R2), and a potential difference is generated across the resistor (R2), turning the transistor (Tr3) on. When the transistor (Tr3) turns on, the base of the driver transistor (Tr4) turns on. It is configured so that it is grounded, the driver I transistor (Tr4) is forcibly turned off, the supply of base current to the output transistor (Tr5) is stopped, and the output transistor (Tr5) is turned off.
しかしながら、この従来装置では、電圧スイッチング回
路として、３個のトランジスタ（Ｔｒｉ＞・・（ＴＲ３
）と５個の抵抗（Ｒ１）・・（Ｒ５）の計８個の素子を
必要とし、装置が複雑になる。However, in this conventional device, three transistors (Tri>...(TR3
) and five resistors (R1)...(R5), making a total of eight elements necessary, making the device complicated.
（ハ）発明の目的
本発明は、上述した知恵を解消すへくなされたもので、
電圧スイッチング回路を少ない素子数で確実に動作せし
めることのできる装置を提供することを目的とする。(c) Purpose of the invention The present invention has been made to solve the above-mentioned wisdom, and
It is an object of the present invention to provide a device that can reliably operate a voltage switching circuit with a small number of elements.
（ニ）発明の構成
抵抗領域近傍に位置する第１領域との上に絶縁層を介し
て配設きれる電極層とを備え、前記第１領域と電極層に
印加される電圧値の応じて、前記抵抗領域の近傍に位置
する第１領域にて伝導チヘ・ンネルを形成し、前記抵抗
領域の少なくとも一部を実質的に短絡することを特徴と
する半導体装置である。(d) comprising an electrode layer disposed via an insulating layer over a first region located near the constituent resistance region of the invention, and depending on a voltage value applied to the first region and the electrode layer, The semiconductor device is characterized in that a conductive channel is formed in a first region located near the resistance region to substantially short-circuit at least a portion of the resistance region.
（ホ〉 実施例
以下、本発明の一実施例を、第１図ないし第４図を参照
して説明する。第１図は本発明の要部を示す平面図、第
２図は第１図の■−■線断面図である。第１図および第
２図において、く１）はＰ型シリコン基板、（２）は基
板（１〉表面に形成きれたＮ−型のエピタキシャル層で
ある。（３）が濃度の低いＰ−型の第１領域で、イオン
注入法や拡散法などによりエピタキシャル層（２）の表
面部分に形成移れている。（４）はＮ゛型の抵抗領域で
、本実施例では、第１領域（３）に第１図に示すように
、蛇行する如く複数回屈曲し王形成されている。（５）
は二酸化シリコン（Ｓｉｆｔ）からなる絶縁層で、前記
表面部を熱酸化するなどして形成される。（６）は第１
の電極層で、抵抗領域（４）および抵抗領域（４）の近
傍に位置する第１領域（３）との上に絶縁層（５）を介
して配置される。く７）は伝導チャンネルで、第１の電
極層（６）と第１領域（３）とに印加きれる電圧価に応
じて前記抵抗領域（４〉の近傍に位置する第１領域（３
）の表面層部分に形成される。(E) Example Hereinafter, an example of the present invention will be explained with reference to FIGS. 1 to 4. FIG. 1 is a plan view showing the main part of the present invention, and FIG. 1 and 2, 1) is a P-type silicon substrate, and (2) is an N-type epitaxial layer completely formed on the surface of the substrate (1). (3) is a low concentration P- type first region, which is formed on the surface of the epitaxial layer (2) by ion implantation or diffusion. (4) is an N-type resistance region, In this embodiment, as shown in FIG. 1, the first region (3) is bent multiple times in a meandering manner to form a king. (5)
is an insulating layer made of silicon dioxide (Sift), and is formed by thermally oxidizing the surface portion. (6) is the first
The electrode layer is disposed on the resistance region (4) and the first region (3) located near the resistance region (4) with an insulating layer (5) interposed therebetween. 7) is a conduction channel, and the first region (3) located near the resistance region (4) changes depending on the voltage value that can be applied to the first electrode layer (6) and the first region (3).
) is formed on the surface layer.
（８）は第１領域（３）に配設された第２の電極層で、
この電極層（８）により、第１領域（３）の電極取り出
しと配線が行われる。（９）はＰ゛型の分離領域で、複
数個の素子（例えは、トランジスタや涯抗など）を分離
する。(8) is a second electrode layer disposed in the first region (3),
This electrode layer (8) performs electrode extraction and wiring in the first region (3). (9) is a P' type isolation region that isolates a plurality of elements (eg, transistors, resistors, etc.).
また、第１領域（３）には、第１の電ｉ層（６）Ｃｆに
位置する第１領域（３）の表面層部分の全てカＰ−型か
らＮ型へと反転するのを防止するためのＰ型のチャンネ
ルストッパ（１０）が形成いれて１７＼る。In addition, in the first region (3), all of the surface layer portions of the first region (3) located in the first electric i-layer (6) and Cf are prevented from inverting from P-type to N-type. A P-type channel stopper (10) is formed 17 for this purpose.
尚、図中（１１）（１２）は、他の素子、例えは後述−
４る第３図に示すトランジスタ（Ｔ ｒｌｌ）や抵抗（
Ｒ２２＞なとに配線される電極層である。Note that (11) and (12) in the figure indicate other elements, such as -
4 The transistor (T rll) and resistor (T rll) shown in Figure 3
This is an electrode layer wired to R22>.
而して、前記第１領域（３）と第１の電極層く６との間
に印加される電圧に応して、抵抗領域（４近傍に位置す
るＰ型の第１領域（３〉の表面層部うに電子が蓄えられ
、ついに前記表面層部分がＰｌからＮ型に反転して伝導
チャンネル（７）を形りし、抵抗領域（４）の少なくと
も一部分が実質的し短絡する。したがって、前記抵抗領
域（４）の抵を値を等測的に変えることができる。In response to the voltage applied between the first region (3) and the first electrode layer 6, the P-type first region (3) located near the resistance region (4) Electrons are stored in the surface layer portion, and finally said surface layer portion inverts from Pl to N type to form a conduction channel (7) and at least a portion of the resistive region (4) becomes substantially short-circuited. The resistance value of the resistance region (4) can be varied isometrically.
第３図は前述した素子を利用した電圧スイッチング回路
を示す回路図である。この図において、抵抗（Ｒ１１）
と（Ｒ１２＞との切換えを、前述したように、印加され
る電圧に応じて、抵抗領域（４）の近傍に位置するＰ型
の第１領域く３）の表面層部分かＰ型からＮ型へと反転
することにより形成される伝導チャンネル（７）によっ
て行うものである。すなわち、第１、第２の電極層（６
）（８）に、電源電圧が印加され、その印加きれた電圧
が、閾値（ＶＴ）を越えると、抵抗領域（４）の近傍に
位置するＰ型の第１領域く３）の表面層部分がＮ型に反
転し、伝導チヘ・ンネル（７）を形成することにより、
抵抗値） 域（４）の少なくとも一部分が実質的に短絡
する。FIG. 3 is a circuit diagram showing a voltage switching circuit using the above-described elements. In this figure, resistance (R11)
As mentioned above, switching between R12 and (R12>) is performed depending on the applied voltage, whether from the surface layer portion of the P-type first region (3) located near the resistance region (4) or from the P-type to the N-type. This is done by conducting channels (7) formed by inversion into a mould. That is, the first and second electrode layers (6
) (8), when a power supply voltage is applied and the applied voltage exceeds the threshold value (VT), the surface layer portion of the P-type first region (3) located near the resistance region (4) is inverted to N-type and forms a conductive channel (7),
Resistance Value) At least a portion of region (4) is substantially shorted.
） 従っ−Ｃ２抵抗値の大きな抵抗（Ｒ１１）から抵抗
値の小さい抵抗（Ｒ１２）へと切換わるので、トランジ
スＬ タ（Ｔｒｌｌ）のベースバイアスを変化上しめ、
トシと ンシスタ（Ｔ ｒｌｌ）のコレクタ電流を変化
させることができる。) Therefore, -C2 switches from the resistor (R11) with a large resistance value to the resistor (R12) with a small resistance value, so the base bias of the transistor (Trll) is changed,
The collector current of the transistor (T rll) can be changed.
℃ そして、このような回路は、閾値電圧（ＶＴ）をＰ
型の第１領域の表面濃度をコントロールすることにより
自在に設定できるので、電圧スイッチング回路として用
いることができる。°C and such a circuit sets the threshold voltage (VT) to P
Since it can be freely set by controlling the surface concentration of the first region of the mold, it can be used as a voltage switching circuit.
第４図は本発明をパワーアンプの過電圧保護回路に適用
した場合の回路図で、第３図で示した抵抗（Ｒ１１ン（
、Ｒ１２）（Ｒ２２＞およびトランジスタ（Ｔ ｒｌｌ
）が第４図の抵抗（Ｒ１１ン（Ｒ１２ン（Ｒ２２＞およ
びトランジスタ（Ｔｒｌｌ）に対応し、第１図の第１、
第２の電極層（６）（８）間に印加される電圧として、
第４図のＶｃｃ−ＧＮＤ間の電源電圧が印加される。つ
まり、Ｖｃｃ−ＧＮＤ間の電圧が抵抗領域（４）の近傍
に位置するＰ型の第１領域（３〉の表面肩部分がＰ型か
らＮ型へ反転し、伝導チヘ・ンネル（７）を形成する閾
値電圧を越えたとき、トランジスタ（Ｔｒｌｌ）のベー
ス・コレクタ間に挿入される抵抗が、抵抗（Ｒ１１）か
ら抵抗（Ｒ１２）へと切換わる。この抵抗（Ｒ１１）と
抵抗（Ｒ１２＞との関係は、抵抗（Ｒ１１）の抵抗（Ｒ
１１＞の抵抗領域（４）の一部が実質的に短絡して、抵
抗（Ｒ１２）となるので、抵抗（Ｒ１１）の抵抗値）抵
抗（Ｒ１２）の抵抗値となる。而して、トランジスタ（
Ｔ ｒｌｌ）にベースハイアスがかかり、トランジスタ
（Ｔｒｌｌ）がＯＮする。トランジスタ（Ｔｒｌｌ）が
ＯＮすることにより、ドライバトランジスタ（Ｔｒ２１
）のベースが接地し、ドライバトランジスタ（Ｔｒ２１
）を強制的にＯＦＦさせ、出力トランジスタ（Ｔ ｒ３
１）のベース電流の供給が停止し、出力トランジスタ（
Ｔｒ３１）がＯＦＦするように構成きれる。Figure 4 is a circuit diagram when the present invention is applied to an overvoltage protection circuit of a power amplifier, and shows the resistor (R11) shown in Figure 3.
, R12) (R22> and the transistor (T rll
) corresponds to the resistor (R11 (R12)) and the transistor (Trll) in FIG.
As the voltage applied between the second electrode layers (6) and (8),
A power supply voltage between Vcc and GND in FIG. 4 is applied. In other words, the surface shoulder portion of the P-type first region (3) located near the resistance region (4) where the voltage between Vcc and GND is reversed from P-type to N-type, and the conduction channel (7) is reversed from P-type to N-type. When the threshold voltage to be formed is exceeded, the resistor inserted between the base and collector of the transistor (Trll) switches from the resistor (R11) to the resistor (R12).This resistor (R11) and the resistor (R12> The relationship between the resistance (R11) and the resistance (R
11> is substantially short-circuited and becomes a resistor (R12), so that the resistance value of the resistor (R11) becomes the resistance value of the resistor (R12). Therefore, the transistor (
A base bias is applied to the transistor (Trll), and the transistor (Trll) is turned on. When the transistor (Trll) turns on, the driver transistor (Tr21)
) is grounded, and the driver transistor (Tr21
) is forcibly turned off, and the output transistor (T r3
1) base current supply is stopped, and the output transistor (
It can be configured so that Tr31) is turned off.
尚、抵抗（Ｒ２２）、トランジスタ（Ｔ ｒｌｌＨＴ
ｒ２１）（Ｔｒ３１）などを、第２図で示した分離領域
（９）で分離される他の領域に形成することにより、集
積化を図ることができる。In addition, a resistor (R22) and a transistor (T rllHT
By forming the transistors r21) (Tr31), etc. in other regions separated by the isolation region (9) shown in FIG. 2, integration can be achieved.
以上のように本発明を用いたパワーアンプの過電圧保護
回路は、トランジスタ（Ｔ ｒｌｌ）と抵抗（Ｒ２２＞
と抵抗（Ｒ１１）と（Ｒ１２）に変化する抵抗領域（４
）との計３素子で、電圧スイッチング回路（２１）を構
成することができ、素子数を従来例に比して大幅に削減
することができる。As described above, the power amplifier overvoltage protection circuit using the present invention consists of a transistor (T rll) and a resistor (R22>
The resistance region (4) changes to resistance (R11) and (R12).
), the voltage switching circuit (21) can be configured with a total of three elements, and the number of elements can be significantly reduced compared to the conventional example.
（へ） 発明の詳細
な説明したように、本発明は、印加される電圧に応して
、抵抗領域近傍に位置する第１領域にて伝導チャンネル
を形成し、前記抵抗領域の少なくとも一部分が短絡する
ことにより、抵抗値が大幅に変化するように構成したの
で、前記素子をトランジスタのベース・コレクタ間に挿
入するだけで、電圧スイッチング回路を構成できるため
、構造が簡単にしてｇｋ産性に優れた半導体装置が提供
できるなど、その工業的価値は大きい。(F) As described in detail, the present invention forms a conduction channel in a first region located near a resistive region in response to an applied voltage, and at least a portion of the resistive region is short-circuited. As a result, the resistance value can be changed significantly, and a voltage switching circuit can be constructed by simply inserting the element between the base and collector of a transistor, resulting in a simple structure and excellent GK productivity. Its industrial value is great, as it can provide semiconductor devices with improved performance.
第１図は本発明の要部を示す平面図、第２図は第１図の
■−■線断面図、第３図は本発明を用いた電圧スイッチ
ング回路を示す回路図、第４図は本発明をバソーアンプ
過電圧保護回路に用いた回路図である。第５図は従来の
過電圧保護回路を示す回路図である。
１・・基板、２・ エピタキシャル層、３ ・第１領域
、４ ・抵抗領域、５ 絶縁層、６ ・第１の電極層、
７・ 伝′４−ｆ〜ンネル、８・・第２の電極層。
第４図
ノー
第５図FIG. 1 is a plan view showing the main parts of the present invention, FIG. 2 is a sectional view taken along the line ■-■ in FIG. 1, FIG. 3 is a circuit diagram showing a voltage switching circuit using the present invention, and FIG. FIG. 2 is a circuit diagram in which the present invention is applied to a basso amplifier overvoltage protection circuit. FIG. 5 is a circuit diagram showing a conventional overvoltage protection circuit. 1. Substrate, 2. Epitaxial layer, 3. First region, 4. Resistance region, 5. Insulating layer, 6. First electrode layer.
7. Channel, 8. Second electrode layer. Figure 4 No Figure 5
Claims (1)
他導電型の抵抗領域、この抵抗領域と抵抗領域近傍に位
置する第１領域との一部に絶縁層を介して配設される電
極層とを備え、前記第１領域と電極層に印加跡れる電圧
値に応じて、前記抵抗領域近傍に位置する第１領域にて
伝導チャンネルを形成し、前記抵抗領域の少なくとも一
部を実質的に短絡せしめることを特徴とする半導体装置
。(1) - A first region of a conductive type, a resistive region of a different conductive type formed in this first region, and a part of this resistive region and a first region located near the resistive region arranged through an insulating layer. forming a conduction channel in a first region located near the resistive region according to a voltage value applied to the first region and the electrode layer; 1. A semiconductor device characterized in that a portion of the semiconductor device is substantially short-circuited.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24121883A JPS60132355A (en) | 1983-12-20 | 1983-12-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24121883A JPS60132355A (en) | 1983-12-20 | 1983-12-20 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60132355A true JPS60132355A (en) | 1985-07-15 |
Family
ID=17070950
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24121883A Pending JPS60132355A (en) | 1983-12-20 | 1983-12-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60132355A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005093763A (en) * | 2003-09-18 | 2005-04-07 | Matsushita Electric Ind Co Ltd | Semiconductor device |
-
1983
- 1983-12-20 JP JP24121883A patent/JPS60132355A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005093763A (en) * | 2003-09-18 | 2005-04-07 | Matsushita Electric Ind Co Ltd | Semiconductor device |
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