JPS63142848A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS63142848A JPS63142848A JP61291045A JP29104586A JPS63142848A JP S63142848 A JPS63142848 A JP S63142848A JP 61291045 A JP61291045 A JP 61291045A JP 29104586 A JP29104586 A JP 29104586A JP S63142848 A JPS63142848 A JP S63142848A
- Authority
- JP
- Japan
- Prior art keywords
- impurity region
- concentration
- type impurity
- low
- low concentration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 239000012535 impurity Substances 0.000 claims abstract description 88
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 230000005669 field effect Effects 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 abstract description 30
- 238000009792 diffusion process Methods 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract description 2
- 230000000694 effects Effects 0.000 description 3
- 230000005465 channeling Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000008267 milk Substances 0.000 description 1
- 210000004080 milk Anatomy 0.000 description 1
- 235000013336 milk Nutrition 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、ＭＯ８型半導体集積回路装置に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an MO8 type semiconductor integrated circuit device.
従来の技術
最近の半導体集積回路技術の進歩はめざましく、大集積
回路（以下ＬＳＩと称す。）が多くなってきた。ＬＳＩ
の場合は素子数が非常に多いために、１素子当りの消費
電力が大きいと発熱などの影響が出るため、消費電力の
小さい相補ＭＯＳ回路（以下ＣＭＯＳ，ＬＳＩと称す。2. Description of the Related Art Recent advances in semiconductor integrated circuit technology have been remarkable, and the number of large integrated circuits (hereinafter referred to as LSI) has increased. LSI
In the case of , the number of elements is very large, so if the power consumption per element is large, heat generation will occur, so a complementary MOS circuit (hereinafter referred to as CMOS or LSI) with low power consumption is used.
）が多く使われている。しかし、超ＣＭＯＳ−ＬＳＩに
なるとＭＯＳ）ランジスタのゲー長が１μｍ前後と短か
ぐなるためにショート・チャンネル効果によるしきい値
電圧の低下などの影響が現われ、これを改善するための
一つとして異なる導電型の二つの井戸形の不純物領域を
有する０ＭＯ８−ＬＳＩ（以下ＷウェルＣＭＯ９−ＬＩ
Ｉと称す。）が考案されている。第２図に従来のＷウェ
ルＣＭＯＳ，ＬＳＩの構造例を示す。) are often used. However, in the case of super CMOS-LSIs, the gate length of MOS transistors becomes short, around 1 μm, which causes effects such as a decrease in threshold voltage due to the short channel effect. 0MO8-LSI (hereinafter referred to as W-well CMO9-LI) having two well-shaped impurity regions of conductivity type.
It is called I. ) has been devised. FIG. 2 shows an example of the structure of a conventional W-well CMOS, LSI.
低濃度のＮ型半導体基板１上に低濃度Ｎ型不純物領域２
及び低濃度Ｐ型不純物領域３が形成され、前記低濃度Ｎ
型不純物領域２上に高濃度Ｐ型不純物領域であるＰチャ
ンネルトランジスタのソース領域６とドレイン領域４が
形成され、且つ、低濃度Ｐ型不純物領域３上に高濃度Ｎ
型不純物領域であるＮチャンネルトランジスタのソース
領域８とドレイン領域９が形成されている。Ｐチャンネ
ルトランジスタのソース領域６及びドレイン領域４を結
ぶ薄いゲート酸化膜１ｏ上にゲート電極１３が形成され
、且つ、Ｎチャンネルトランジスタのソース領域８及び
ドレイン領域９を結ぶ薄いゲート酸化膜１１上にゲート
電極１８が形成され、ゲート電極１３及びゲート電ｊ１
８は入力端子２３に接続されている。また、Ｐチャンネ
ルトランジスタのドレイン領域４上に導電性電極１２が
形成され、Ｎチャンネルトランジスタのドレイン領域９
上に導電性電極１９が形成されており、導電性電極１２
及び１９は出力端子２０に接続されている。Ｐチャンネ
ルトランジスタのソース領域５上に導電性電極１４が形
成され電源端子２１に接続されておシ、また、Ｎチャ／
ネルトランジスタのソース領域８上に導電性電極１７が
形成され接地端子２２に接続されている。さらに、低濃
度Ｎ型不純物領域２上に高濃度Ｎ型不純物領域６が形成
され、且つ、低濃度Ｐ型不純物領域３上に高濃度Ｐ型不
純物領域７が形成されている。高濃度Ｎ型不純物領域ｅ
上には導電性電極１６が形成され電源端子２１に接続さ
れると共に、高濃度Ｐ型不純物領域Ｔ上には導電性電極
１６が形成され接地端子２２に接続されている。Low concentration N type impurity region 2 on low concentration N type semiconductor substrate 1
and a low concentration P type impurity region 3 are formed, and the low concentration N
The source region 6 and drain region 4 of a P channel transistor, which are high concentration P type impurity regions, are formed on the type impurity region 2, and the high concentration N type impurity region 3 is formed on the low concentration P type impurity region 3.
A source region 8 and a drain region 9 of an N-channel transistor, which are type impurity regions, are formed. A gate electrode 13 is formed on a thin gate oxide film 1o connecting the source region 6 and drain region 4 of the P-channel transistor, and a gate electrode 13 is formed on the thin gate oxide film 11 connecting the source region 8 and drain region 9 of the N-channel transistor. Electrode 18 is formed, and gate electrode 13 and gate electrode j1
8 is connected to the input terminal 23. Further, a conductive electrode 12 is formed on the drain region 4 of the P-channel transistor, and a conductive electrode 12 is formed on the drain region 9 of the N-channel transistor.
A conductive electrode 19 is formed on the conductive electrode 12.
and 19 are connected to the output terminal 20. A conductive electrode 14 is formed on the source region 5 of the P-channel transistor and connected to the power supply terminal 21.
A conductive electrode 17 is formed on the source region 8 of the channel transistor and connected to a ground terminal 22. Further, a high concentration N type impurity region 6 is formed on the low concentration N type impurity region 2, and a high concentration P type impurity region 7 is formed on the low concentration P type impurity region 3. High concentration N type impurity region e
A conductive electrode 16 is formed thereon and connected to a power supply terminal 21, and a conductive electrode 16 is formed on the high concentration P-type impurity region T and connected to a ground terminal 22.
発明が解決しようとする問題点
前述の従来例では、その構造上の理由によりラッチアッ
プが起こ）易いという欠点がある。以下、ラッチアップ
現象を第３図を用いて説明する。すなわち、第３図は第
２図の電気的等価回路である。Problems to be Solved by the Invention The conventional example described above has the disadvantage that latch-up is likely to occur due to its structure. The latch-up phenomenon will be explained below with reference to FIG. That is, FIG. 3 is an electrical equivalent circuit of FIG. 2.
第３図において、寄生トランジスタＱ１ばＰチャンネル
トランジスタのソース領域６（エミッタ）、低濃度Ｎ型
不純物領域２及びＮ型半導体基板１（ベース）、低濃度
Ｐ型不純物領域３（コレクタ）によって形成され、寄生
トランジスタＱ２はＰチャンネルトランジスタのドレイ
ン領域４（エミッタ）、低濃度Ｎ型不純物領域２及びＮ
型半導体基板１（ベース）、低濃度Ｐ型不純物領域３（
コレクタ）によって形成されている。また、寄生トラン
ジスタＱ３はＮチャンネルトランジスタのソース領域８
（エミッタ）、低濃度Ｐ型不純物領域２（ベース）、Ｎ
型半導体基板１及び低濃度Ｎ型不純物領域２（コレクタ
）によって形成され、寄生トランジスタＱ４はＮチャン
ネルトランジスタのドレイン領域９（エミッタ）、低濃
度Ｐ型不純物領域２（ベース）、Ｎ型半導体基板１及び
低濃度Ｎ型不純物領域２（コレクタ）によって形成され
ている。また、抵抗Ｒ１，Ｒ３，Ｒ６，Ｒ７はＮ型半導
体基板１及び低濃度Ｎ型不純物領域２による抵抗であシ
、抵抗Ｒ２，Ｒ４，Ｒｅ、Ｒｓは低濃度Ｐ型不純物領域
３による抵抗である。前記構造において、出力端子２０
に電源端子２１より高い電圧が印加され、電流が寄生ト
ランジスタＱ２゜抵抗Ｒｅ、抵抗Ｒ４を流れて接地端子
２１へ抜ける場合、抵抗Ｒ４の両端に発生する電圧が寄
生トランジスタＱ３のベース−エミッタ間順方向電圧よ
りも大きければ寄生トランジスタＱ３がＯＮＩ、、抵抗
Ｒ１，抵抗Ｒ３及び寄生トランジスタＱ３を通って電源
端子２ｏから接地端子２１に電流が流れる。さらに、抵
抗Ｒ１，抵抗Ｒ３及び寄生トランジスタＱ３を通って流
れる電流により抵抗Ｒ１の両端に発生する電圧が寄生ト
ランジスタＱ１のエミッターベース間項方向電圧よりも
大きければ寄生トランジスタＱ１がＯＮし、寄生トラン
ジスタＱ３及び寄生トランジスタＱ１によって構成され
るサイリスタがＯＮ した状態になり、電源を○ＦＦ
するまで電流が流れ続は素子の破壊を起こしてしまう。In FIG. 3, a parasitic transistor Q1 is formed by a source region 6 (emitter) of a P-channel transistor, a low concentration N-type impurity region 2, an N-type semiconductor substrate 1 (base), and a low concentration P-type impurity region 3 (collector). , the parasitic transistor Q2 is connected to the drain region 4 (emitter) of the P channel transistor, the low concentration N type impurity region 2 and the N
type semiconductor substrate 1 (base), low concentration P type impurity region 3 (
collector). In addition, the parasitic transistor Q3 is the source region 8 of the N-channel transistor.
(emitter), low concentration P-type impurity region 2 (base), N
The parasitic transistor Q4 is formed by the drain region 9 (emitter) of the N-channel transistor, the low concentration P-type impurity region 2 (base), and the N-type semiconductor substrate 1. and a low concentration N-type impurity region 2 (collector). Further, resistors R1, R3, R6, and R7 are resistances due to the N-type semiconductor substrate 1 and low concentration N-type impurity region 2, and resistors R2, R4, Re, and Rs are resistances due to the low concentration P-type impurity region 3. . In the structure, the output terminal 20
When a voltage higher than the power supply terminal 21 is applied to the parasitic transistor Q2, the current flows through the parasitic transistor Q2, the resistor Re, the resistor R4, and exits to the ground terminal 21, the voltage generated across the resistor R4 is in the order between the base and emitter of the parasitic transistor Q3. If it is larger than the directional voltage, the parasitic transistor Q3 is ONI, and current flows from the power supply terminal 2o to the ground terminal 21 through the resistor R1, the resistor R3, and the parasitic transistor Q3. Furthermore, if the voltage generated across the resistor R1 due to the current flowing through the resistors R1, R3, and the parasitic transistor Q3 is larger than the emitter-base voltage of the parasitic transistor Q1, the parasitic transistor Q1 turns on, and the parasitic transistor Q3 The thyristor constituted by the parasitic transistor Q1 is turned ON, and the power supply is turned OFF.
If the current continues to flow until this happens, the device will be destroyed.
また、出力端子１９に接地端子２１よりも低い電圧が印
加され、電源端子２ｏから抵抗Ｒ１，抵抗Ｒ７，Ｗ生ト
ランジスタＱ４を通って出力端子１９へ電流が抜ける場
合、抵抗Ｒ１の両端に発生する電圧が寄生トランジスタ
Ｑ１のエミッターベース間電圧よりも大きければ寄生ト
ランジスタＱ１がＯＮし、寄生トランジスタＱ１゜抵抗
Ｒ２，抵抗Ｒ４を通って電源端子２ｏから接地端子２１
に電流が流れる。このとき、抵抗Ｒ４の両端に発生する
電圧が寄生トランジスタＱ３のベース−エミッタ間順方
向・電圧よりも大きければ寄生トランジスタＱ３がＯＮ
し、寄生トランジスタＱ３及び寄生トランジスタＱ１に
よって構成されるサイリスタがＯＮ した状態になり、
電源をＯＦＦ するまで電流が流れ続は素子の破壊を起
こしてしまう。従来は、Ｎ型半導体基板１及び低濃度Ｎ
型不純物領域２による抵抗Ｒ１，また、低濃度Ｐ型不純
物領域３による抵抗Ｒ４を小さくするように設計してい
るが、従来の抵抗値ではラッチアップを抑制するには不
十分であった。Furthermore, when a voltage lower than the ground terminal 21 is applied to the output terminal 19 and current flows from the power supply terminal 2o to the output terminal 19 through the resistor R1, resistor R7, and W transistor Q4, a voltage is generated across the resistor R1. If the voltage is larger than the emitter-base voltage of the parasitic transistor Q1, the parasitic transistor Q1 is turned on, and the voltage is passed from the power supply terminal 2o to the ground terminal 21 through the parasitic transistor Q1, resistor R2, and resistor R4.
A current flows through. At this time, if the voltage generated across the resistor R4 is larger than the base-emitter forward voltage of the parasitic transistor Q3, the parasitic transistor Q3 is turned on.
Then, the thyristor constituted by the parasitic transistor Q3 and the parasitic transistor Q1 is turned on,
If the current continues to flow until the power is turned off, the device will be destroyed. Conventionally, an N-type semiconductor substrate 1 and a low concentration N
Although it is designed to reduce the resistance R1 due to the type impurity region 2 and the resistance R4 due to the low concentration P type impurity region 3, the conventional resistance values were insufficient to suppress latch-up.
問題点を解決するための手段
本発明は、ＷウェルＣＭＯＳ，ＬＳＩの相異なる導電型
の低濃度不純物領域の少なくとも一方の導電型の低濃度
不純物領域の底面に接して、該低濃度不純物領域と同一
導電型の高濃度不純物領域を形成する構造の半導体集積
回路装置である。Means for Solving the Problems The present invention provides a structure in which a low concentration impurity region of at least one conductivity type of a W-well CMOS or LSI is in contact with the bottom surface of the low concentration impurity region of different conductivity types. This is a semiconductor integrated circuit device having a structure in which high concentration impurity regions of the same conductivity type are formed.
作 用
前記構成により、基板と同一導電型の高濃度不純物領域
による低抵抗が、半導体基板及び基板と同一導電型の低
濃度不純物領域による抵抗（第３図に示す抵抗Ｒ１）に
並列に加わり、寄生トランジスタＱ１のベース−エミッ
タ間の抵抗Ｒ１は小さくなり（Ｒ１′）、寄生トランジ
スタＱ１がＯＮしにくくなり、また、基板と反対導電型
の高濃度不純物領域による低抵抗が、基板と反対導電型
の低濃度不純物領域による抵抗（第３図に示す抵抗Ｒ４
）に並列に加わり、寄生トランジスタＱ３のベース−エ
ミッタ間の抵抗Ｒ４は小さくなり（Ｒ４’ ） 、寄生
トランジスタＱ３がＯＮ Ｌにくくなる。Operation With the above configuration, the low resistance due to the high concentration impurity region having the same conductivity type as the substrate is added in parallel to the resistance due to the semiconductor substrate and the low concentration impurity region having the same conductivity type as the substrate (resistance R1 shown in FIG. 3). The resistance R1 between the base and emitter of the parasitic transistor Q1 becomes small (R1'), making it difficult for the parasitic transistor Q1 to turn on. Resistance due to the low concentration impurity region (resistance R4 shown in Figure 3)
), the resistance R4 between the base and emitter of the parasitic transistor Q3 becomes small (R4'), and the parasitic transistor Q3 becomes difficult to turn on.
実施例
以下、本発明の一実施例を図面を用いて説明する。第１
図は本発明の一実施例を示す断面図である。低濃度のＮ
型半導体基板１上に低濃度Ｎ型不純物領域２及び、低濃
度Ｐ型不純物領域３を形成し、低濃度Ｎ型不純物領域２
の底面に接して高濃度Ｎ型不純物領域２４を形成すると
共に、低濃度Ｐ型不純物領域３の底面に接して高濃度Ｐ
型不純物領域２６を形成している。前記低濃度Ｎ型不純
物領域２上に高濃度Ｐ型不純物領域であるＰチャンネル
トランジスタのソース領域６とドレイン領域４が形成さ
れ、且つ、低濃度Ｐ型不純物領域３±に高濃度Ｎ型不純
物領域であるＮチャンネルトランジスタのソース領域８
とドレイン領域９力；形成されている。Ｐチャンネル−
トランジスタのソース領域５及びドレイン領域４を結ぶ
薄いゲート酸化膜１０上にゲート電極１３が形成され、
且つ、Ｎチャンネルトランジスタのソース領域８及びド
レイン領域９を結ぶ薄いゲート酸化膜１１上にゲート電
極１８が形成され、ゲート電極１３及びゲート電極１８
は入力端子２３に接続されている。EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings. 1st
The figure is a sectional view showing one embodiment of the present invention. low concentration of N
A low concentration N type impurity region 2 and a low concentration P type impurity region 3 are formed on a type semiconductor substrate 1.
A high-concentration N-type impurity region 24 is formed in contact with the bottom surface of
A type impurity region 26 is formed. A source region 6 and a drain region 4 of a P channel transistor, which are high concentration P type impurity regions, are formed on the low concentration N type impurity region 2, and a high concentration N type impurity region is formed on the low concentration P type impurity region 3±. The source region 8 of the N-channel transistor is
and a drain region are formed. P channel-
A gate electrode 13 is formed on a thin gate oxide film 10 connecting the source region 5 and drain region 4 of the transistor.
In addition, a gate electrode 18 is formed on a thin gate oxide film 11 connecting the source region 8 and drain region 9 of the N-channel transistor, and the gate electrode 13 and the gate electrode 18
is connected to the input terminal 23.
また、Ｐチャンネルトランジスタのドレイン領域４上に
導電性電極１２が形成され、Ｎチャンネルトランジスタ
のドレイン領域９上に導電性電極１９が形成されており
、導電性電極１２及び１９は出力端子２０に接続されて
いる。Ｐチャンネルトランジスタのソース領域Ｓ上に導
電性電極１４が形成され電源端子２１に接続されており
、また、Ｎチャンネルトランジスタのソース領域８上に
導電性電極１７が形成され接地端子２２に接続されてい
る。さらに、低濃度Ｎ型不純物領域２上に高濃度Ｎ型不
純物領域６が形成され、且つ、低濃度Ｐ型不純物領域３
上に高濃度Ｐ型不純物領域７が形成されている。高濃度
Ｎ型不純物領域６上には導電性電極１６が形成され電源
端子２１に接続されると共に、高濃度Ｐ型不純物領域Ｔ
上には゛導電性電極１６が形成され接地端子２２に接続
されている。前記高濃度Ｎ型不純物領域２４及び、高濃
度Ｐ型不純物領域２５を拡散、あるいはチャネリング現
象を利用したイオン注入、あるいは他の方法によって形
成することによって、第３図に示す低濃度Ｎ型不純物領
域及びＮ型半導体基板による抵抗Ｒ１に並列に高濃度Ｎ
型不純物領域２４による低抵抗が付は加わると共に、低
濃度Ｐ型不純物領域による抵抗Ｒ４に並列に高濃度Ｐ型
不純物領域２６による低抵抗が付は加わることになる。Further, a conductive electrode 12 is formed on the drain region 4 of the P-channel transistor, a conductive electrode 19 is formed on the drain region 9 of the N-channel transistor, and the conductive electrodes 12 and 19 are connected to the output terminal 20. has been done. A conductive electrode 14 is formed on the source region S of the P-channel transistor and connected to the power supply terminal 21, and a conductive electrode 17 is formed on the source region 8 of the N-channel transistor and connected to the ground terminal 22. There is. Further, a high concentration N type impurity region 6 is formed on the low concentration N type impurity region 2, and a high concentration N type impurity region 6 is formed on the low concentration N type impurity region 3.
A heavily doped P-type impurity region 7 is formed thereon. A conductive electrode 16 is formed on the high concentration N-type impurity region 6 and connected to the power supply terminal 21, and the high concentration P-type impurity region T
A conductive electrode 16 is formed on top and connected to a ground terminal 22. By forming the high-concentration N-type impurity region 24 and the high-concentration P-type impurity region 25 by diffusion, ion implantation using a channeling phenomenon, or other methods, the low-concentration N-type impurity region shown in FIG. 3 is formed. and a high concentration N in parallel with the resistor R1 formed by the N-type semiconductor substrate.
In addition to the low resistance due to the type impurity region 24, the low resistance due to the high concentration P type impurity region 26 is added in parallel to the resistance R4 due to the low concentration P type impurity region.
従って、寄生トランジスタＱ１のベースから電源端子２
１に至る抵抗Ｒ１及び、寄生トランジスタＱ３のベース
から接地端子２２に至る抵抗Ｒ４は小さくなり、寄生ト
ランジスタＱ１及び寄生トランジスタＱ３がＯＮするの
に必要な電流が大きくなるのでラッテアップ強度を向上
することができる。Therefore, from the base of the parasitic transistor Q1 to the power supply terminal 2
1 and the resistance R4 from the base of the parasitic transistor Q3 to the ground terminal 22 become smaller, and the current required to turn on the parasitic transistors Q1 and Q3 becomes larger, so that the ratte-up strength can be improved. I can do it.
以上の説明はＮ型半導体基板を例としたが、導電型を逆
にすることにより、Ｐ型基板のＷウェルＣＭＯ８，ＬＳ
Ｉにも適用されることは明白である。また、実施例では
低濃度Ｎ型不純物領域２及び低濃度Ｐ型不純物領域３の
底面に接して、それぞれ高濃度不純物領域２４．２５を
形成したが、低濃度不純物領域２，３の底面に接してい
ずれか一方の高濃度不純物領域を形成しても所期の目的
は達成できるものである。The above explanation took the N-type semiconductor substrate as an example, but by reversing the conductivity type, the W-well CMO8, LS of the P-type substrate
It is clear that this also applies to I. Further, in the embodiment, the high concentration impurity regions 24 and 25 were formed in contact with the bottom surfaces of the low concentration N-type impurity region 2 and the low concentration P-type impurity region 3, respectively, but the high concentration impurity regions 24 and 25 were formed in contact with the bottom surfaces of the low concentration impurity regions 2 and 3. Even if either one of the high concentration impurity regions is formed, the desired purpose can be achieved.
発明の効果
以上のように本発明は、半導体基板上に該半導体基板と
同−導電型及び反対導電型の低濃度不純物領域を形成し
、少なくとも一方の導電型の低濃度不純物領域の底面に
接して、該低濃度不純物領域と同一導電型の高濃度不純
物領域を形成した構成のＷウェルＣＭＯＳ−ＬＳＩとす
ることによって、寄生サイリスタのサージ耐圧を向上で
きラッチアップに強いＷウェルＣＭＯ８−ＬＳＩを提供
するものである。Effects of the Invention As described above, the present invention forms low concentration impurity regions of the same conductivity type and opposite conductivity type as the semiconductor substrate on a semiconductor substrate, and contacts the bottom surface of the low concentration impurity region of at least one conductivity type. By forming a W-well CMOS-LSI with a high-concentration impurity region of the same conductivity type as the low-concentration impurity region, we provide a W-well CMOS-LSI that can improve the surge withstand voltage of the parasitic thyristor and is resistant to latch-up. It is something to do.
第１図は本発明のＷウェルＣＭＯＳ，ＬＳＩの一実施例
を示す断面図、第２図はＷウェルＣＭＯＳ・ＬＳＩの従
来例を示す断面図、第３図はＷウェルＣＭＯＳ，ＬＳＩ
の従来例の電気的等価回路図である。
１・・・・・・低濃度Ｎ型半導体基板、２・・・・・・
低濃度Ｎ型不純物領域、３・・・・・・低濃度Ｐ型不純
物領域、４゜５．７，２１５・・・・・・高濃度Ｐ型不
純物領域、６，８゜９．２４・・・・・・高濃度Ｎ型不
純物領域、１０．１１・・・・・・ゲート酸化膜、１２
，１４，１５，１６゜１７．１９・・・・・・導電性電
極、１３．１８・・・・・・ゲート電極、２０・・・・
・・出力端子、２１・・・・・・電源端子、２２・・・
・・・接地端子、２３・・・・・・入力端子。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名ｆ・
一体膿凌Ｎ！千引様扱
２−−− ｑ ’／モ乳物領戚
３−−−、、 ｐ隻 ・
”−＜５凍Ｉ
２２−葎境・
２３−一一人カ ダ
第 ３ 図Fig. 1 is a sectional view showing an embodiment of the W-well CMOS/LSI of the present invention, Fig. 2 is a sectional view showing a conventional example of the W-well CMOS/LSI, and Fig. 3 is a sectional view of the W-well CMOS/LSI.
FIG. 2 is an electrical equivalent circuit diagram of a conventional example. 1...Low concentration N-type semiconductor substrate, 2...
Low concentration N type impurity region, 3...Low concentration P type impurity region, 4°5.7,215...High concentration P type impurity region, 6,8°9.24... ...High concentration N-type impurity region, 10.11... Gate oxide film, 12
, 14, 15, 16° 17.19... Conductive electrode, 13.18... Gate electrode, 20...
...Output terminal, 21...Power terminal, 22...
...Ground terminal, 23...Input terminal. Name of agent: Patent attorney Toshio Nakao and one other person f.
What the hell is this? Senbiki-sama treatment 2 --- q '/mo milk territory 3 ---,, p ship ・ ”-<5 frozen I 22- Ukyo ・ 23- 1 person Kada Fig. 3
Claims (1)
第一の低濃度不純物領域及び、前記半導体基板と反対導
電型の第二の低濃度不純物領域を形成し、前記第一及び
第二の低濃度不純物領域のうち少なくとも一方の導電型
の低濃度不純物領域の底面に接して、該低濃度不純物領
域と同一導電型の高濃度不純物領域を形成し、前記第一
の低濃度不純物領域及び第二の低濃度不純物領域上にＭ
ＯＳ型電界効果トランジスタを形成することを特徴とす
る半導体集積回路装置。A first low concentration impurity region of the same conductivity type as the semiconductor substrate and a second low concentration impurity region of the opposite conductivity type to the semiconductor substrate are formed on a semiconductor substrate of one conductivity type; A high concentration impurity region of the same conductivity type as the low concentration impurity region is formed in contact with the bottom surface of at least one of the low concentration impurity regions of the low concentration impurity region, and the first low concentration impurity region and M on the second low concentration impurity region
A semiconductor integrated circuit device characterized by forming an OS type field effect transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61291045A JPS63142848A (en) | 1986-12-05 | 1986-12-05 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61291045A JPS63142848A (en) | 1986-12-05 | 1986-12-05 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63142848A true JPS63142848A (en) | 1988-06-15 |
Family
ID=17763726
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61291045A Pending JPS63142848A (en) | 1986-12-05 | 1986-12-05 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63142848A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015076453A (en) * | 2013-10-07 | 2015-04-20 | キヤノン株式会社 | Solid-state imaging device, method of manufacturing the same, and imaging system |
-
1986
- 1986-12-05 JP JP61291045A patent/JPS63142848A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015076453A (en) * | 2013-10-07 | 2015-04-20 | キヤノン株式会社 | Solid-state imaging device, method of manufacturing the same, and imaging system |
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