JPS6388857A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS6388857A JPS6388857A JP61233528A JP23352886A JPS6388857A JP S6388857 A JPS6388857 A JP S6388857A JP 61233528 A JP61233528 A JP 61233528A JP 23352886 A JP23352886 A JP 23352886A JP S6388857 A JPS6388857 A JP S6388857A
- Authority
- JP
- Japan
- Prior art keywords
- region
- impurity region
- substrate
- type impurity
- high concentration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 239000012535 impurity Substances 0.000 claims abstract description 58
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 230000005669 field effect Effects 0.000 claims 2
- 230000003071 parasitic effect Effects 0.000 abstract description 9
- 239000004020 conductor Substances 0.000 abstract description 2
- 230000000694 effects Effects 0.000 description 2
- 239000003048 aphrodisiac agent Substances 0.000 description 1
- 230000002509 aphrodisiac effect Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、ＭｏＳ型半導体集積回路装置に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a MoS type semiconductor integrated circuit device.
従来の技術
２ ・・−１
近年、マイクロプロセッサを用いた制御回路に代表され
るディジタル回路の増加に伴−）で、ＭｏＳ型半導体集
積回路装置（以下ＭＯ８−ＬＳＩと称す。）が多く使わ
れるようになり、ＭＯＳ．ＬＳＩのなかでも消費電力が
少ない相補ＭｏＳ型半導体集積回路装置（以下ＣＭＯ８
，ＬＳＩと称す。）の占める割合が高くなっている。第
２図に従来の０ＭＯ８，ＬＳＩの構造例を示す。Conventional technology 2...-1 In recent years, with the increase in the number of digital circuits typified by control circuits using microprocessors, MoS type semiconductor integrated circuit devices (hereinafter referred to as MO8-LSI) are often used. Then, MOS. Complementary MoS semiconductor integrated circuit device (hereinafter CMO8) has low power consumption among LSIs.
, called LSI. ) account for a high proportion. FIG. 2 shows an example of the structure of a conventional 0MO8, LSI.
低濃度のＮ型半導体基板１」二に低濃度Ｐ型不純物領域
２及び高濃度Ｐ型不純物領域であるソース領域４とドレ
イン領域３が形成され、旧つ、低濃度Ｐ型不純物領域２
に高濃度Ｎ型不純物領域であるソース領域７とドレイン
領域８が形成されている。ソース領域４及びドレイン領
域３を結ぶ薄いゲート酸化膜ｅ上にゲート電極１２が形
成され、且つ、ソース領域７及びドレイン領域８を結ぶ
薄いゲート酸化膜１ｏ上にゲート電極１７が形成され、
ゲート電極１２及びゲート電極１７は入力端子２２に接
続されている。うまた、ドレイン領域３上に導電性電極
１１が形成され、ドレイン領域８３ ベー／
」二に導電性電極１８が形成されており、導電性電極１
１及び１８は出力端子１９に接続されている。A low concentration P type impurity region 2 and a source region 4 and a drain region 3 which are high concentration P type impurity regions are formed in a low concentration N type semiconductor substrate 1.
A source region 7 and a drain region 8, which are heavily doped N-type impurity regions, are formed in the region. A gate electrode 12 is formed on a thin gate oxide film e that connects the source region 4 and the drain region 3, and a gate electrode 17 is formed on the thin gate oxide film 1o that connects the source region 7 and the drain region 8.
Gate electrode 12 and gate electrode 17 are connected to input terminal 22 . Furthermore, a conductive electrode 11 is formed on the drain region 3, a conductive electrode 18 is formed on the drain region 83, and a conductive electrode 18 is formed on the drain region 83.
1 and 18 are connected to the output terminal 19.
ソース領域４上に導電性電極１３が形成され電源端子２
ｏに接続されており、壕だ、ソース領域７上に導電性電
極１６が形成され接地端子２１に接続されている。さら
に、Ｎ型半導体基板１上に高濃度Ｎ型不純物領域５が形
成され、且つ、低濃度Ｐ型不純物領域２」二に高濃度Ｐ
型不純物領域６が形成されている。高濃度Ｎ型不純物領
域５上には導電性電極１４が形成され電源端子２ｏに接
続されると共に、高濃度Ｐ型不純物領域６上には導電性
電極１６が形成され接地端子２１に接続されている。A conductive electrode 13 is formed on the source region 4 and the power terminal 2
In the trench, a conductive electrode 16 is formed on the source region 7 and connected to a ground terminal 21 . Further, a high concentration N type impurity region 5 is formed on the N type semiconductor substrate 1, and a high concentration P type impurity region 2 is formed on the low concentration P type impurity region 2.
A type impurity region 6 is formed. A conductive electrode 14 is formed on the high concentration N-type impurity region 5 and connected to the power supply terminal 2o, and a conductive electrode 16 is formed on the high concentration P-type impurity region 6 and connected to the ground terminal 21. There is.
発明が解決しようとする問題点
前述の従来例では、その構造上の理由によりラッチアッ
プが起こり易いという欠点がある。以下、ランチアップ
現象を第３図を用いて説明する。すなわち、第３図は第
２図の電気的等価回路である。Problems to be Solved by the Invention The conventional example described above has the disadvantage that latch-up is likely to occur due to its structure. The launch-up phenomenon will be explained below using FIG. 3. That is, FIG. 3 is an electrical equivalent circuit of FIG. 2.
第３図において、寄生トランジスタＱ１はソース領域４
と基板１及び低濃度Ｐ型不純物領域２によって形成され
、寄生トランジスタＱ２はドレイン領域３と基板１及び
低濃度Ｐ型不純物領域２によって形成されている。寸だ
、寄生トランジスタＱ３はソース領域７と低濃度Ｐ型不
純物領域２及び基板１によって形成され、寄生トランジ
スタＱ４はドレイン領域８と低濃度Ｐ型不純物領域２及
び基板１によって形成されている。また、抵抗Ｒ１゜Ｒ
３、Ｒ５、Ｒ７はＮ型基板１による抵抗であり、抵抗Ｒ
２，Ｒ４，Ｒ６，Ｒ８は低濃度のＰ型不純物領域２によ
る抵抗である。前記構造に」・・いて、出力端子１９に
過電流が流入すると電流はトランジスタＱ２．抵抗Ｒ６
，Ｒ４を通り接地端子２１へ抜ける。この時に抵抗Ｒ４
の両端に発生する電圧がトランジスタＱ３のベース−エ
ミッタ間順方向電圧よりも大きければトランジスタＱ３
がＯＮし、抵抗Ｒ１，Ｒ３及びトランジスタＱ３を通−
）で電源端子２０から接地端子２１に電流が流れる。In FIG. 3, the parasitic transistor Q1 is located in the source region 4.
The parasitic transistor Q2 is formed by the drain region 3, the substrate 1, and the lightly doped P-type impurity region 2. In other words, the parasitic transistor Q3 is formed by the source region 7, the low concentration P type impurity region 2, and the substrate 1, and the parasitic transistor Q4 is formed by the drain region 8, the low concentration P type impurity region 2, and the substrate 1. Also, the resistance R1゜R
3, R5, R7 are resistances due to the N-type substrate 1, and the resistance R
2, R4, R6, and R8 are resistances due to the low concentration P-type impurity region 2. In the above structure, when an overcurrent flows into the output terminal 19, the current flows through the transistor Q2. Resistor R6
, R4 and exits to the ground terminal 21. At this time, resistance R4
If the voltage generated across the transistor Q3 is larger than the base-emitter forward voltage of the transistor Q3, the transistor Q3
turns on, passing through resistors R1, R3 and transistor Q3.
), current flows from the power supply terminal 20 to the ground terminal 21.
さらに、抵抗Ｒ１，Ｒ３及びトランジスタＱ３を通って
流れる電流により抵抗Ｒ１の両端に発生する電圧がトラ
ンジスタＱ１のエミッターベース間５ ヘ−ノ
順方向電圧よりも大きければトランジスタＱ１がＯＮし
、トランジスタＱ３及びＱｌによって構成されるサイリ
スタがＯＮした状態になり、電源をＯＦＦするまで電流
が流れ続は素子の破壊を起こしてしまう。従来は、基板
抵抗Ｒ１及び低濃度のＰ型不純物領域２による抵抗Ｒ４
を小さくするように設計しているが、製造プロセスのバ
ラツキにより設計値どおりの抵抗値にするのは難しいと
いう問題点があった。Further, if the voltage generated across the resistor R1 due to the current flowing through the resistors R1, R3 and the transistor Q3 is larger than the forward voltage between the emitter and base of the transistor Q1, the transistor Q1 turns on, and the transistor Q3 and The thyristor formed by Ql is turned on, and if the current continues to flow until the power is turned off, the device will be destroyed. Conventionally, the substrate resistance R1 and the resistance R4 due to the low concentration P-type impurity region 2
However, due to variations in the manufacturing process, it is difficult to achieve the designed resistance value.
問題点を解決するための手段
前記問題点を解決するために本発明は、０ＭＯ８−ＬＳ
Ｉの基板上のＭＯＳ−ＬＳＩが形成される前記基板と異
なる導電型の低濃度領域の近傍に前記内基板と同一導電
型の高濃度不純物領域を形成し、その高濃度不純物領域
を０ＭＯ８，ＬＩＩの電源に接続する構成の半導体集積
回路装置を特徴とするものである。Means for Solving the Problems In order to solve the above problems, the present invention provides 0MO8-LS
A high concentration impurity region of the same conductivity type as the inner substrate is formed near a low concentration region of a conductivity type different from that of the substrate on which the MOS-LSI is formed on the substrate of I, and the high concentration impurity region is 0MO8, LII. The present invention is characterized by a semiconductor integrated circuit device configured to be connected to a power source.
作 用
上記構成によれば、基板に電源と同電位の領域が、前記
高濃度不純物領域により広範囲に形成されることと、Ｍ
ＯＳ−ＬＳＩが形成される低濃度不純物領域から電源ま
での基板による抵抗を小さくし、ラッチアップの起こり
にくい構造にすることができる。Effect According to the above configuration, a region having the same potential as the power supply is formed in a wide range in the substrate by the high concentration impurity region, and
The resistance of the substrate from the low concentration impurity region where the OS-LSI is formed to the power supply can be reduced, and a structure in which latch-up is less likely to occur can be achieved.
実施例 以下本発明の一実施例を図面を用いて説明する。Example An embodiment of the present invention will be described below with reference to the drawings.
第１図は本発明の一実施例を示す断面図である。FIG. 1 is a sectional view showing one embodiment of the present invention.
低濃度Ｎ型半導体基板１上に高濃度Ｎ型不純物領域２３
を形成した上に低濃度Ｎ型不純物領域２４を形成し、低
濃度Ｎ型不純物領域２４に高濃度Ｎ型不純物領域２３ま
で貫通する高濃度Ｎ型不純物領域２５を形成すると共に
、低濃度Ｐ型不純物領域２及び高濃度Ｐ型不純物領域で
あるソース領域４とドレイン領域３が形成され、且つ、
低濃度Ｐ型不純物領域２に高濃度Ｎ型不純物領域である
ソース領域７とドレイン領域８が形成されている。High concentration N type impurity region 23 on low concentration N type semiconductor substrate 1
A low concentration N type impurity region 24 is formed on the low concentration N type impurity region 24, and a high concentration N type impurity region 25 penetrating through the low concentration N type impurity region 24 to the high concentration N type impurity region 23 is formed. An impurity region 2 and a source region 4 and a drain region 3 which are high concentration P-type impurity regions are formed, and
A source region 7 and a drain region 8, which are high concentration N-type impurity regions, are formed in the low concentration P-type impurity region 2.
ソース領域４及びドレイン領域３を結ぶ薄いゲート酸化
膜ｅ上にゲート電Ｗ１．１２が形成され、且つ、ソース
領域７及びドレイン領域８を結ぶ薄いゲート酸化膜１０
上にゲート電極１７が形成さね、ゲ−１−電極１２及び
ゲート電極１７は入力端子２２に接続されている。また
、ドレイン領域３上に導電性電ＷＬ１１が形成され、ド
レイン領域８上に導電イイ１：電極１８が形成されてお
り、導電性電極１１及び１８は出力端子１９に接続され
ている。ソース領域４上に導電性電極１３が形成され、
且つ、高濃度Ｎ型不純物領域２５上に導電性電極２６が
形成されており、導電性電極１３及び２６は電源端子２
０に接続されている。また、ソース領域Ｔ十に導電性電
極１６が形成され接地端子２１に接続されている。さら
に、低濃度Ｎ型不純物領域２４上に高濃度Ｎ型不純物領
域５が形成され、且つ、低濃度Ｐ型不純物領域２」二に
高濃度Ｐ型不純物領域６が形成されている。高濃度Ｎ型
不純物領域５上には導電性電極１４が形成され電源端子
２ｏに接続される古共に、高濃度Ｐ型不純物領域６上に
は導電性電極１６が形成され接地端子２１に接続されて
いる。前記構成によれば、低濃度Ｎ型半導体基板１に高
濃度Ｎ型不純物領域２３を形成し電源端子に接続するこ
とによって、基板１に電源と同電位の領域が広範囲に形
成されることになり、低濃度Ｐ型不純物領域２から電源
１での基板による抵抗を減少させることができる。従っ
て第３図における寄生トランジスタＱ１のベースから電
源端子２ｏに至る経路の抵抗分Ｒ１が減少し、寄生トラ
ンジスタＱ１がＯＮするのに必要な電流が大きくなりラ
ッチアップ強度を向上することができる。以上の説明は
Ｎ型基板を例としたが、導電型を逆にすることにより、
Ｐ型基板の０ＭＯ３−ＬＳＩにも適用されることは明白
である。A gate voltage W1.12 is formed on a thin gate oxide film e that connects the source region 4 and the drain region 3, and a thin gate oxide film 10 that connects the source region 7 and the drain region 8.
A gate electrode 17 is formed thereon, and the gate electrode 12 and the gate electrode 17 are connected to the input terminal 22 . Further, a conductive electrode WL11 is formed on the drain region 3, a conductive electrode 18 is formed on the drain region 8, and the conductive electrodes 11 and 18 are connected to an output terminal 19. A conductive electrode 13 is formed on the source region 4,
Further, a conductive electrode 26 is formed on the high concentration N-type impurity region 25, and the conductive electrodes 13 and 26 are connected to the power supply terminal 2.
Connected to 0. Further, a conductive electrode 16 is formed in the source region T1 and connected to a ground terminal 21. Further, a high concentration N type impurity region 5 is formed on the low concentration N type impurity region 24, and a high concentration P type impurity region 6 is formed on the low concentration P type impurity region 2''. A conductive electrode 14 is formed on the high concentration N-type impurity region 5 and connected to the power terminal 2o, and a conductive electrode 16 is formed on the high concentration P-type impurity region 6 and connected to the ground terminal 21. ing. According to the above configuration, by forming the high concentration N type impurity region 23 in the low concentration N type semiconductor substrate 1 and connecting it to the power supply terminal, a region having the same potential as the power supply is formed in a wide range in the substrate 1. , the resistance caused by the substrate in the power supply 1 from the low concentration P-type impurity region 2 can be reduced. Therefore, the resistance R1 of the path from the base of the parasitic transistor Q1 to the power supply terminal 2o in FIG. 3 is reduced, the current required to turn on the parasitic transistor Q1 is increased, and the latch-up strength can be improved. The above explanation uses an N-type substrate as an example, but by reversing the conductivity type,
It is clear that the present invention is also applicable to OMO3-LSI with a P-type substrate.
発明の効果
以上のように本発明は、基板上に基板と同一導電型で、
且つ、高濃度の不純物領域を形成し、該高濃度不純物領
域を導電体を用いて電源Ａ１１１子に接続することによ
って基板をベースとする寄生トランジスタがＯＮするの
に必要な電流を大きくし、ラッチアップに強い０ＭＯ８
，ＬＳＩを提供するものである。Effects of the Invention As described above, the present invention provides a substrate with the same conductivity type as the substrate,
In addition, by forming a high concentration impurity region and connecting the high concentration impurity region to the power supply A111 using a conductor, the current required to turn on the parasitic transistor based on the substrate is increased, and the latch is activated. 0MO8 strong against up
, LSI.
第１図は本発明の一実施例を示す半導体集積回９ ペー
ジ
路装置の断面図、第２図は従来の半導体集積回路装置を
示す断面図、第３図は従来の半導体集積回路装置の電気
的等価回路図である。
１・・・低濃度Ｎ型半導体基板、２・・・・・・低濃度
Ｐ型不純物領域、３，４．６・・・・・高濃度Ｐ型不純
物領域、６ 、７ 、８ 、２３ 、２５・・・・・・
高濃度Ｎ型不純物領域、２４・・・・・低濃度Ｎ型不純
物領域、９゜１０・・・ゲート酸化膜、１１ 、１３
、１４ 、１５゜１６．１８．２６・・・・・導電性電
極、１２．１７・・・・・・ゲート電極、１９・・・・
出力端子、２ｏ・・・・・・電源端子、２１・・・・・
・接地端子、２２・・・・・・入力端子。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名１−
−−イき、＆ｔＮ泗す半導４擾り嘆ζＰ之、３．４．ｌ
、、 −一一断濃度Ｐ型坏絶害惧戚２１− 膨池媚膠
？？−−−人力ｘ子
２４−へ渡友Ｎジ陳咋肩賊FIG. 1 is a cross-sectional view of a semiconductor integrated circuit device showing an embodiment of the present invention, FIG. 2 is a cross-sectional view showing a conventional semiconductor integrated circuit device, and FIG. 3 is a cross-sectional view of a conventional semiconductor integrated circuit device. FIG. 1...Low concentration N-type semiconductor substrate, 2...Low concentration P-type impurity region, 3,4.6...High concentration P-type impurity region, 6, 7, 8, 23, 25...
High concentration N-type impurity region, 24...Low concentration N-type impurity region, 9°10... Gate oxide film, 11, 13
, 14 , 15° 16.18.26... Conductive electrode, 12.17... Gate electrode, 19...
Output terminal, 2o...Power terminal, 21...
・Grounding terminal, 22...Input terminal. Name of agent: Patent attorney Toshio Nakao and 1 other person1-
--Iki, &tN 3.4. l
,, -One-stop concentration P-type perishable relative 21- Pochi aphrodisiac? ? ---Human power x child 24- to friend Nji Chen Kui shoulder bandit
Claims (1)
の第一の高濃度不純物領域を形成した上に前記基板と同
一導電型の第二の低濃度不純物領域を形成し、該第二の
低濃度不純物領域に前記基板と同一導電型で前記第一の
高濃度不純物領域まで貫通する第三の高濃度不純物領域
を形成すると共に、前記第二の低濃度不純物領域上にＭ
ＯＳ型電界効果トランジスタを形成し、前記第三の高濃
度不純物領域を前記ＭＯＳ型電界効果トランジスタの電
源に接続したことを特徴とする半導体集積回路装置。On a semiconductor substrate of one conductivity type, a first high concentration impurity region of the same conductivity type as the semiconductor substrate is formed, and then a second low concentration impurity region of the same conductivity type as the substrate is formed; A third high concentration impurity region having the same conductivity type as the substrate and penetrating to the first high concentration impurity region is formed in the low concentration impurity region, and a third high concentration impurity region is formed on the second low concentration impurity region.
1. A semiconductor integrated circuit device comprising an OS type field effect transistor formed therein, and the third high concentration impurity region being connected to a power source of the MOS type field effect transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61233528A JPS6388857A (en) | 1986-10-01 | 1986-10-01 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61233528A JPS6388857A (en) | 1986-10-01 | 1986-10-01 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6388857A true JPS6388857A (en) | 1988-04-19 |
Family
ID=16956452
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61233528A Pending JPS6388857A (en) | 1986-10-01 | 1986-10-01 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6388857A (en) |
-
1986
- 1986-10-01 JP JP61233528A patent/JPS6388857A/en active Pending
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