JPS63102249A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS63102249A JPS63102249A JP61247797A JP24779786A JPS63102249A JP S63102249 A JPS63102249 A JP S63102249A JP 61247797 A JP61247797 A JP 61247797A JP 24779786 A JP24779786 A JP 24779786A JP S63102249 A JPS63102249 A JP S63102249A
- Authority
- JP
- Japan
- Prior art keywords
- impurity region
- type impurity
- region
- low concentration
- high concentration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 239000012535 impurity Substances 0.000 claims abstract description 55
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 230000005669 field effect Effects 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 abstract description 29
- 230000005465 channeling Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、ＭＯ８型半導体集積回路装置に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an MO8 type semiconductor integrated circuit device.
従来の技術
ＭＯＳ型半導体集積回路装置のうち、相補型ＭＯＳ（以
下ｃＭＯＳ，Ｉ、Ｓ Ｉと称ス。） は消費を力が少な
いという利点があり、多く使用されるようになってきた
。第２図に従来のＣＭＯＳφＬＳＩの構造例を示す。Among conventional MOS type semiconductor integrated circuit devices, complementary MOS (hereinafter referred to as cMOS, I, SI) has the advantage of low power consumption, and has come to be widely used. FIG. 2 shows an example of the structure of a conventional CMOSφLSI.
低濃度のＮ型半導体基板１上に低濃度Ｐ型不純物領域２
及び高濃度Ｐ型不純物領域であるＰチャンネルトランジ
スタのソース領域４とドレイン領域３が形成され、且つ
、低濃度不純物領域２に高濃度Ｎ型不純物領域であるＮ
チャンネルトランジスタのソース領域７とドレイン領域
８が形成されてイル。Ｐチャンネルトランジスタのソー
ス領域４及びドレイン領域３を結ぶ薄いゲート酸化膜９
上にゲート電極１２が形成され、且つ、Ｎチャンネルト
ランジスタのソース領域７及びドレイン領域８を結ぶ薄
いゲート酸化膜１ｏ上にゲート電極１７が形成され、ゲ
ート電極１２及びゲート電極１７は入力端子２２に接続
されている。また、Ｐチャンネルトランジスタのドレイ
ン領域３上に導電性電極１１が形成され、Ｎチャンネル
トランジスタのドレイン領域８上に導電性電極１８が形
成されてお９、導電性１啄１１及び１８は出力端子１９
に接続されている。Ｐチャンネルトランジスタのソース
領域４上に導電性電極１３が形成され電源端子２０に接
続されており、また、Ｎチャンネルトランジスタソース
領域Ｔ上に導電性電極１ｅが形成され接地端子２１に接
続されている。さらに、Ｎ型半導体基板１上に高濃度Ｎ
型不純物領域５が形成され、且つ、低濃度Ｐ型不純物領
域２上に高濃度Ｐ型不純物領域６が形成されている。高
濃度Ｎ型不純物領域Ｓ上には導電性電極１４が形成され
電源端子２０に接続されると共に、高濃度Ｐ型不純物預
域ｅ上には導電性電極１５が形成され接地端子２１に接
続されている。Low concentration P type impurity region 2 on low concentration N type semiconductor substrate 1
A source region 4 and a drain region 3 of a P channel transistor, which are high concentration P type impurity regions, are formed in the low concentration impurity region 2, and a high concentration N type impurity region, which is a high concentration N type impurity region, is formed in the low concentration impurity region 2.
A source region 7 and a drain region 8 of the channel transistor are formed. Thin gate oxide film 9 connecting source region 4 and drain region 3 of P-channel transistor
A gate electrode 12 is formed thereon, and a gate electrode 17 is formed on a thin gate oxide film 1o connecting the source region 7 and drain region 8 of the N-channel transistor. It is connected. Further, a conductive electrode 11 is formed on the drain region 3 of the P-channel transistor, a conductive electrode 18 is formed on the drain region 8 of the N-channel transistor 9, and the conductive electrodes 11 and 18 are connected to the output terminal 19.
It is connected to the. A conductive electrode 13 is formed on the source region 4 of the P-channel transistor and connected to the power supply terminal 20, and a conductive electrode 1e is formed on the N-channel transistor source region T and connected to the ground terminal 21. . Furthermore, a high concentration of N on the N-type semiconductor substrate 1 is
A type impurity region 5 is formed, and a high concentration P type impurity region 6 is formed on the low concentration P type impurity region 2. A conductive electrode 14 is formed on the high concentration N-type impurity region S and connected to the power supply terminal 20, and a conductive electrode 15 is formed on the high concentration P-type impurity deposit region e and connected to the ground terminal 21. ing.
発明が解決しようとする問題点
前述の従来例では、その構造上の理由によシラッチアッ
プが起こり易いという欠点がある。以下、ラッチアップ
現象を第３図を用いて説明する。すなわち、第３図は第
２図の電気的等価回路である。Problems to be Solved by the Invention The above-mentioned conventional example has a disadvantage in that sillage build-up is likely to occur due to its structure. The latch-up phenomenon will be explained below with reference to FIG. That is, FIG. 3 is an electrical equivalent circuit of FIG. 2.
第３図において、寄生トランジスタＱ１はＰチャンネル
トランジスタのソース領域４とＮ型半導体基板１及び低
濃度Ｐ型不純物領域２によって形成され、寄生トランジ
スタＱ２はＰチャンネルトランジスタのドレイン領域３
とＮ型半導体基板１及び低濃度Ｐ型不純物領域２によっ
て形成されている。また、寄生トランジスタＱ３はＮチ
ャンネルトランジスタのソース領域子と低濃度Ｐ型不純
物領域２及びＮ型半導体基板１によって形成され、寄生
トランジスタＱ４はＮチャンネルトランジスタのドレイ
ン領域８と低濃度Ｐ型不純物領域２及びＮ型半導体基板
１によって形成されている。また、抵抗Ｒ１，Ｒ３，Ｒ
５，Ｒ了はＮ型半導体基板１による抵抗であシ、抵抗Ｒ
２，Ｒ４，Ｒ６゜Ｒ８は低濃度のＰ型不純物領域２によ
る抵抗である。前記構造において、出力端子１９に電源
端子２０よシも高い電圧が印加され、電流が寄生トラン
ジスタＱ２．抵抗Ｒｅ、抵抗Ｒ４を流れて接地端子２１
へ抜ける場合、抵抗Ｒ４の両端に発生する電圧が寄生ト
ランジスタＱ３のベース−エミッタ間順方向電圧よシも
大きければ寄生トランジスタＱ３がＯＮし、抵抗Ｒ１，
抵抗Ｒ３及び寄生トランジスタＱ３を通って電源端子２
ｏから接地端子２１に電流が流れる。さらに、抵抗Ｒ１
，抵抗Ｒ３及び寄生トランジスタＱ３を通って流れる電
流により抵抗Ｒ１の両端に発生する電圧が寄生トランジ
スタＱ１のエミッターベース間順方向電圧よりも大きけ
れば寄生トランジスタＱ１がＯＮＬ、、寄生トランジス
タＱ３及び寄生トランジスタＱ１によって構成されるサ
イリスタがＯＮした状態になり、電源ＯＦＦするまで電
流が流れ続は素子の破壊を起こしてしまう。また、出力
端子１９に接地端子２１よりも低い電圧が印加され、電
源端子２ｏから抵抗Ｒ１，抵抗Ｒ７，寄生トランジスタ
Ｑ４を通って出力端子１９へ電流が抜ける場合、抵抗Ｒ
１の両端に発生する電圧が寄生トランジスタＱ１のエミ
ッターペース間順方向電圧よりも大きければ寄生トラン
ジスタＱ１がＯＮＬ、寄生トランジスタＱ１．抵抗Ｒ２
，抵抗Ｒ４を通って電源端子２０から接地端子２１に電
流が流れる。このとき、抵抗Ｒ４の両端に発生する電圧
が寄生トランジスタＱ３のベース−エミッタ間順方向電
圧よりも大きければ寄生トランジスタＱ３がＯＮＩ、、
寄生トランジスタＱ３及び寄生トランジスタＱ１によっ
て構成されるサイリスタがＯＮした状態になり、電源を
ＯＦＦするまで電流が流れ続は素子の破壊を起こしてし
まう。従来は、基板による抵抗Ｒ１及び低濃度Ｐ型不純
物領域２による抵抗Ｒ４を小さくするように設計してい
るが、製造プロセスのバラツキによシ設計値どおシの抵
抗値にするのは難しいという問題点があった。In FIG. 3, a parasitic transistor Q1 is formed by a source region 4 of a P-channel transistor, an N-type semiconductor substrate 1, and a low concentration P-type impurity region 2, and a parasitic transistor Q2 is formed by a drain region 3 of a P-channel transistor.
, an N-type semiconductor substrate 1 and a low concentration P-type impurity region 2 . Further, the parasitic transistor Q3 is formed by the source region of the N-channel transistor, the low concentration P-type impurity region 2, and the N-type semiconductor substrate 1, and the parasitic transistor Q4 is formed by the drain region 8 of the N-channel transistor and the low concentration P-type impurity region 2. and an N-type semiconductor substrate 1. Also, resistors R1, R3, R
5, R is a resistance due to the N-type semiconductor substrate 1, and the resistance R
2, R4, R6° and R8 are resistances due to the low concentration P-type impurity region 2. In the above structure, a higher voltage than the power supply terminal 20 is applied to the output terminal 19, and a current flows through the parasitic transistors Q2. Flows through resistor Re and resistor R4 to ground terminal 21
If the voltage generated across the resistor R4 is larger than the base-emitter forward voltage of the parasitic transistor Q3, the parasitic transistor Q3 turns on and the resistors R1,
Power supply terminal 2 through resistor R3 and parasitic transistor Q3
A current flows from o to the ground terminal 21. Furthermore, resistance R1
, if the voltage generated across the resistor R1 due to the current flowing through the resistor R3 and the parasitic transistor Q3 is larger than the emitter-base forward voltage of the parasitic transistor Q1, then the parasitic transistor Q1 is ONL, the parasitic transistor Q3 and the parasitic transistor Q1 The thyristor constituted by is turned on, and if the current continues to flow until the power is turned off, the device will be destroyed. Furthermore, when a voltage lower than the ground terminal 21 is applied to the output terminal 19 and current flows from the power supply terminal 2o to the output terminal 19 through the resistor R1, resistor R7, and parasitic transistor Q4, the resistor R
1 is larger than the emitter-to-pace forward voltage of the parasitic transistor Q1, the parasitic transistor Q1 is ONL, and the parasitic transistor Q1. Resistance R2
, a current flows from the power supply terminal 20 to the ground terminal 21 through the resistor R4. At this time, if the voltage generated across the resistor R4 is larger than the forward voltage between the base and emitter of the parasitic transistor Q3, the parasitic transistor Q3 becomes ONI.
If the thyristor constituted by the parasitic transistor Q3 and the parasitic transistor Q1 is turned on, and the current continues to flow until the power is turned off, the device will be destroyed. Conventionally, the resistance R1 due to the substrate and the resistance R4 due to the low concentration P-type impurity region 2 are designed to be small, but it is said that it is difficult to achieve a resistance value as high as the design value due to variations in the manufacturing process. There was a problem.
問題点を解決するための手段
本発明は、０ＭＯＳ，ＬＳ Ｉの基板に基板と反対導電
型の低濃度不純物領域を形成し、該低濃度不純物領域の
底面に接して基板と反対導電型の高濃度不純物領域を形
成する構造の半導体集積回路装置である。Means for Solving the Problems The present invention forms a low concentration impurity region of a conductivity type opposite to that of the substrate on the substrate of 0MOS, LSI, and a high concentration impurity region of the opposite conductivity type to the substrate in contact with the bottom surface of the low concentration impurity region. This is a semiconductor integrated circuit device having a structure in which a concentrated impurity region is formed.
作 用
前記構成により、基板と反対導電型の高濃度不純物領域
による抵抗が基板と反対導電型の低濃度不純物領域によ
る抵抗（第３図に示す抵抗Ｒ４）に並列に加わるので第
３図の寄生トランジスタＱ３のベース−エミッタ間の抵
抗が小さくなり、寄生トランジスタＱ３がＯＮしにくく
なる。Operation With the above configuration, the resistance due to the high concentration impurity region of the opposite conductivity type to the substrate is added in parallel to the resistance due to the low concentration impurity region (resistance R4 shown in FIG. 3) of the opposite conductivity type to the substrate, so that the parasitic effect shown in FIG. The base-emitter resistance of transistor Q3 becomes smaller, making it difficult for parasitic transistor Q3 to turn on.
実施例
以下、本発明の一実施例を図面を用いて説明する。第１
図は本発明の一実施例を示す断面図である。低濃度のＮ
型半導体基板１上に、高濃度Ｐ型不純物領域２３を形成
した上に低濃度Ｐ型不純物領域２を形成すると共に高濃
度Ｐ型不純物領域であるＰチャンネルトランジスタのソ
ース領域４とドレイン領域３が形成され、且つ、低濃度
Ｐ型不純物領域２に高濃度Ｎ型不純物領域であるＮチャ
ンネルトランジスタのソース領域７とドレイン領域８が
形成されている。Ｐチャンネルトランジスタのソース領
域４及びドレイン領域３を結ぶ薄いゲート酸化膜９上に
ゲート電極１２が形成され、且つ、Ｎチャンネルトラン
ジスタのソース領域７及びドレイン領域８を結ぶ薄いゲ
ート酸化膜１゜上にゲート電極１７が形成され、ゲート
電極１２及びゲート電極１７は入力端子２２に接続され
ている。また、Ｐチャンネルトランジスタのドレイン領
域３上に導電性電極１１が形成され、Ｎチャンネルトラ
ンジスタのドレイン領域８上に導電性電極１１及び１８
は出力端子１９に接続されている。Ｐチャンネルトラン
ジスタのソース領域４上に導電性電極１３が形成され電
源端子２ｏに接続されておシ、Ｎチャンネルトランジス
タのソース領域７上に導電性電極１６が形成され接地端
子２１に接続されている。さらに、低濃度Ｎ型半導体基
板１上に高濃度Ｎ型不純物領域５が形成され、且つ、低
濃度Ｐ型不純物領域２上に高濃度Ｐ型不純物領域６が形
成されている。高濃度Ｎ型不純物領域６上には導電性電
極１４が形成され電源端子２゜に接続されると共に、高
濃度Ｐ型不純物領域θ上には導電性電極１５が形成され
接地端子２１に接続されている。前記高濃度Ｐ型不純物
領域２３を拡散、あるいはチャネリング現象を利用した
イオン注入、あるいは他の方法によって形成することに
よって、第３図に示す低濃度Ｐ型不純物領域２による抵
抗Ｒ４に並列に高濃度Ｐ型不純物領域２３による低抵抗
が付は加わることになり、第３図の寄生トランジスタＱ
３のベースから接地端子２１に至る抵抗Ｒ４が減少する
ことになシ寄生トランジスタＱ３がＯＮするのに必要な
電流が大きくなりラッチアップ強度を向上することがで
きる。以上の説明はＮ型基板を例としたが、導電性を逆
にすることにより、Ｐ型基板の０ＭＯ８，ＬＳ Ｉにも
適用されることは明白であるう
発明の効果
以上のように本発明は、基板上に基板と反対導電型、且
つ、低濃度の不純物領域を形成し、該低濃度の不純物領
域の底面に接して基板と反対導電型の高濃度不純物領域
を形成した構成の０ＭＯＳ・ＬＳＩとすることによって
、寄生サイリスタのサージ耐圧を向上できラッチアップ
に強い０ＭＯＳ・ＬＳＩを提供するものである。EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings. 1st
The figure is a sectional view showing one embodiment of the present invention. low concentration of N
A high concentration P type impurity region 23 is formed on a type semiconductor substrate 1, and then a low concentration P type impurity region 2 is formed, and a source region 4 and a drain region 3 of a P channel transistor, which are high concentration P type impurity regions, are formed. A source region 7 and a drain region 8 of an N-channel transistor, which are heavily doped N-type impurity regions, are formed in the lightly doped P-type impurity region 2 . A gate electrode 12 is formed on a thin gate oxide film 9 connecting the source region 4 and drain region 3 of the P-channel transistor, and on a thin gate oxide film 1° connecting the source region 7 and drain region 8 of the N-channel transistor. A gate electrode 17 is formed, and the gate electrode 12 and the gate electrode 17 are connected to the input terminal 22. Further, a conductive electrode 11 is formed on the drain region 3 of the P-channel transistor, and conductive electrodes 11 and 18 are formed on the drain region 8 of the N-channel transistor.
is connected to the output terminal 19. A conductive electrode 13 is formed on the source region 4 of the P-channel transistor and connected to the power supply terminal 2o, and a conductive electrode 16 is formed on the source region 7 of the N-channel transistor and connected to the ground terminal 21. . Further, a high concentration N type impurity region 5 is formed on the low concentration N type semiconductor substrate 1, and a high concentration P type impurity region 6 is formed on the low concentration P type impurity region 2. A conductive electrode 14 is formed on the high concentration N-type impurity region 6 and connected to the power supply terminal 2°, and a conductive electrode 15 is formed on the high concentration P-type impurity region θ and connected to the ground terminal 21. ing. By forming the high-concentration P-type impurity region 23 by diffusion, ion implantation using a channeling phenomenon, or other method, a high-concentration P-type impurity region 23 is formed in parallel with the resistor R4 formed by the low-concentration P-type impurity region 2 shown in FIG. A low resistance due to the P-type impurity region 23 is additionally added, and the parasitic transistor Q in FIG.
As the resistance R4 from the base of transistor Q3 to the ground terminal 21 decreases, the current required to turn on the parasitic transistor Q3 increases, and the latch-up strength can be improved. Although the above explanation has been made using an N-type substrate as an example, it is obvious that it can also be applied to P-type substrates such as 0MO8 and LSI by reversing the conductivity. The 0MOS has a structure in which a low concentration impurity region of the opposite conductivity type to the substrate is formed on the substrate, and a high concentration impurity region of the opposite conductivity type to the substrate is formed in contact with the bottom surface of the low concentration impurity region. By using an LSI, it is possible to improve the surge withstand voltage of the parasitic thyristor and provide a 0MOS LSI that is resistant to latch-up.
第１図は本発明の０ＭＯ８，ＬＳ Ｉの一実施例を示す
断面図、第２図はＣＭＯＳ 、 Ｌ Ｓ Ｉの従来例を
示す断面図、第３図は０ＭＯ８−ＬＳ Ｉの従来例の電
気的等価回路図である。
１・・・・・・低濃度Ｎ型半導体基板、２・・・・・・
低濃度Ｐ型不純物領域、３，４，６．２３・・・・・・
高濃度Ｐ型不純物領域、５，７，８・・・・・・高濃度
Ｎ型不純物領域、９，１ｏ・・・・・・ゲート酸化膜、
１１ 、１３，１４゜１５．１６．１８・・・・・・導
電性電極、１２，１７・・・・・・ゲート電極、１９・
・・・・・出力端子、２０・・・・・・電源端子、２１
・・・・・・接地端子、２２・・・・・・入力端子。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名イ一
一−イｔ）ミ、二＠ノＩＳ【、〜二！１１（顯２−９
ｐり８剋疋入
３．４６．２３− 糺１１Ｆ配 ＋７５．７．３−−
−ノーパイＳ：”
１？、＋７−−−ゲーＬ−ｔ’極
＋９−−一出、ｆｌ扉壬
２０−−−を源γ
２ｆ−、＃罠 “
２２−一一人７］ Ｉｒ
；７．ｊ
第３図Fig. 1 is a sectional view showing an embodiment of 0MO8, LSI of the present invention, Fig. 2 is a sectional view showing a conventional example of CMOS, LSI, and Fig. 3 is an electrical diagram of a conventional example of 0MO8-LSI. FIG. 1...Low concentration N-type semiconductor substrate, 2...
Low concentration P type impurity region, 3, 4, 6.23...
High concentration P type impurity region, 5, 7, 8... High concentration N type impurity region, 9, 1o... Gate oxide film,
11, 13, 14゜15.16.18... Conductive electrode, 12, 17... Gate electrode, 19.
...Output terminal, 20...Power terminal, 21
...Ground terminal, 22...Input terminal. Name of agent: Patent attorney Toshi Nakao and 1 other person I11-IT) Mi, 2 @ IS [, ~ 2! 11 (Han 2-9
3.46.23- 11th floor +75.7.3--
-No Pie S: "1?, +7---Game L-t' pole +9--Ichide, fl door 20-- Source γ 2f-, #Trap "22-Each person 7] Ir;7 ．． j Figure 3
Claims (1)
第一の低濃度不純物領域を形成し、さらに、該第一の低
濃度不純物領域の底面に接して前記半導体基板と反対導
電型の第二の高濃度不純物領域を形成すると共に、前記
半導体基板上及び第一の低濃度不純物領域上にＭＯＳ型
電界効果トランジスタを形成することを特徴とする半導
体集積回路装置。A first low concentration impurity region of a conductivity type opposite to that of the semiconductor substrate is formed on a semiconductor substrate of one conductivity type; A semiconductor integrated circuit device, characterized in that a second high concentration impurity region is formed, and a MOS type field effect transistor is formed on the semiconductor substrate and the first low concentration impurity region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61247797A JPS63102249A (en) | 1986-10-17 | 1986-10-17 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61247797A JPS63102249A (en) | 1986-10-17 | 1986-10-17 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63102249A true JPS63102249A (en) | 1988-05-07 |
Family
ID=17168795
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61247797A Pending JPS63102249A (en) | 1986-10-17 | 1986-10-17 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63102249A (en) |
-
1986
- 1986-10-17 JP JP61247797A patent/JPS63102249A/en active Pending
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